Specifications

86 IBM Flex System p260 and p460 Planning and Implementation Guide
Figure 4-16 shows the FLR-L3 cache regions for the cores on the POWER7
processor die.
Figure 4-16 FLR-L3 cache regions on the POWER7 processor
The innovation of using eDRAM on the POWER7 processor die is significant for
several reasons:
򐂰 Latency improvement
A six-to-one latency improvement occurs by moving the L3 cache on-chip,
compared to L3 accesses on an external (on-ceramic) application-specific
integrated circuit (ASIC).
򐂰 Bandwidth improvement
A 2x bandwidth improvement occurs with on-chip interconnect. Frequency
and bus sizes are increased to and from each core.
򐂰 No off-chip drivers or receivers
Removing drivers and receivers from the L3 access path lowers interface
requirements, conserves energy, and lowers latency.
Core
L2 Cache
Core
L2 Cache
Core
L2 Cache
Core
L2 Cache
Core
L2 Cache
Core
L2 Cache
Core
L2 Cache
Core
L2 Cache
Mem Ctrl Mem Ctrl
L3 Cache and Chip Interconnect
Local SMP Links
Remote SMP + I/O Links
Fast local L3
Cache Region
Fast local L3
Cache Region
Fast local L3
Cache Region
Fast local L3
Cache Region
Fast local L3
Cache Region
Fast local L3
Cache Region
Fast local L3
Cache Region
Fast local L3
Cache Region