Specifications

Chapter 4. Product information and technology 79
4.5.3 Architecture
IBM uses innovative methods to achieve the required levels of throughput and
bandwidth. Areas of innovation for the POWER7 processor and POWER7
processor-based systems include (but are not limited to) the following elements:
򐂰 On-chip L3 cache implemented in embedded dynamic random access
memory (eDRAM)
򐂰 Cache hierarchy and component innovation
򐂰 Advances in memory subsystem
򐂰 Advances in off-chip signaling
The superscalar POWER7 processor design also provides various
capabilities, including:
򐂰 Binary compatibility with the prior generation of POWER processors
򐂰 Support for PowerVM virtualization capabilities, including PowerVM Live
Partition Mobility to and from IBM POWER6® and IBM POWER6+™
processor-based systems
Figure 4-12 shows the POWER7 processor die layout with major areas identified:
eight POWER7 processor cores, L2 cache, L3 cache and chip power bus
interconnect, SMP links, GX++ interface, and memory controller.
Figure 4-12 POWER7 processor architecture
C1
Core
L2
4 MB L3
L2
C1
Core
4 MB L3
Memory Controller
C1
Core
L2
4 MB L3
C1
Core
L2
4 MB L3
C1
Core
L2
4 MB L3
L2
C1
Core
4 MB L3
L2
C1
Core
4 MB L3
L2
C1
Core
4 MB L3
SMP
GX++ Bridge
Memory Buffers