Specifications

Chapter 4. Product information and technology 81
POWER7 processor core
Each POWER7 processor core implements aggressive out of order (OoO)
instruction execution to drive high efficiency in the use of available execution
paths. The POWER7 processor has an instruction sequence unit that can
dispatch up to six instructions per cycle to a set of queues. Up to eight
instructions per cycle can be issued to the instruction execution units. The
POWER7 processor has a set of 12 execution units, as follows:
򐂰 Two fixed-point units
򐂰 Two load store units
򐂰 Four double precision floating point units
򐂰 One vector unit
򐂰 One branch unit
򐂰 One condition register unit
򐂰 One decimal floating point unit
The caches that are tightly coupled to each POWER7 processor core are
as follows:
򐂰 Instruction cache: 32 KB
򐂰 Data cache: 32 KB
򐂰 L2 cache: 256 KB, implemented in fast SRAM
򐂰 L3 cache: 4 MB eDRAM
Simultaneous multithreading
An enhancement in the POWER7 processor is the addition of simultaneous
multithreading (SMT) mode, known as SMT4 mode, which enables four
instruction threads to run simultaneously in each POWER7 processor core.
Thus, the instruction thread execution modes of the POWER7 processor are
as follows:
򐂰 SMT1: Single instruction execution thread per core
򐂰 SMT2: Two instruction execution threads per core
򐂰 SMT4: Four instruction execution threads per core
SMT4 mode enables the POWER7 processor to maximize the throughput of the
processor core by offering an increase in processor-core efficiency. SMT4 mode
is the latest step in an evolution of multithreading technologies introduced
by IBM.