User`s manual

6 . 2. 5 S t at u s S ys t em D et ai l : S t at us R eg is t er S et s 95
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6.2.4.8 Clearing Registers
The methods to clear each register are detailed in TABLE 6-3.
Register clear methods
Register Method Example
Condition registers None: registers are not latched —
Event registers:
Standard event status register
Operation event register
Query the event register
*ESR? (clears Standard Event
Status Register
Send *CLS *CLS (clears both registers)
Power on instrument
—
Enable registers:
Standard Event Status Enable Register
Operation Event Enable Register
Service Request Enable Register
Write 0 to the
enable register
*ESE 0 (clears Standard Event
S
tatus Enable register)
Power on instrument
—
Status byte There are no commands that directly clear the status byte as the bits are
non-latching; to clear individual summary bits clear the event register that
corresponds to the summary bit; sending *CLS will clear all event
registers which in turn clears the status byte
If bit 5 (ESB) of the status byte is
set
, send *ESR? to read the
standard event status register
and bit 5 will clear
Power on instrument —
6.2.5 Status System
Detail: Status Register
Sets
As shown in FIGURE 6-1, there are two register sets in the status system of the
Model 335: Standard Event Status Register and Operation Event Register.
6.2.5.1 Standard Event Status Register Set
The Standard Event Status Register reports
the following interface related instru-
ment events: power on detected, command syntax e
rrors, command execution errors,
query errors, operation complete. Any or all of these events may be reported in the
standard event summary bit through the enable register (FIGURE 6-2). The Standard
Event Status Enable command (*ESE) programs the enable register and the query
com
mand (*ESE?) reads it. *ESR? reads and clears the Standard Event Status Register.
The used bits of the Standard Event Register are described as follows:
D P
ower On (PON), Bit (7): this bit is set to indicate an instrument off-on 
transition.
D Command
Error (CME), Bit (5): this bit is set if a command error has been detected
since the last reading. This means that the instrument could not interpret the
command due to a syntax error, an unrecognized header, unrecognized termina-
tors, or an unsupported command.
D Ex
ecution Error (EXE), Bit (4): this bit is set if an execution error has been
detected. This occurs when the instrument is instructed to do something not
within its capabilities.
D Qu
ery Error (QYE), Bit (2): this bit indicates a query error. It occurs rarely and
involves loss of data because the output queue is full.
D Op
eration Complete (OPC), Bit (0): when *OPC is sent, this bit will be set when the
instrument has completed all pending operations. The operation of this bit is not
related to the *OPC? command, which is a separate interface feature
(section 6.2.6.6).
TABLE 6-3