Specifications

Table Of Contents

TIMING

FIXED TIMING:

H1, H2

VARIABLE TIMING:

V1, V2 (binning modes)

RESET (binning modes)

CLAMP (binning modes)

SAMPLE (binning modes)

A/D Clock (binning modes)

See Timing Diagram 1 – Figure 4: Pixel Rate Timing

See Timing Diagram 3 -Figure 12: Binning Mode Timing (2x2 binning shown)

Note: Not available with the KAF-16801E, KAF-16801LE and KAF-4301E image sensors.

OTHER PARAMETERS

FIXED PARAMETERS:

Flush Duration: (4000 lines)

VARIABLE PARAMETERS:

Pixel frequency: The pixel frequency is 1/8 the master clock. The maximum pixel frequency is 6MHz. To run the board at a

slower pixel rate, decrease the system clock frequency, keeping in mind the 1/8 relationship. (e.g. for a 4 MHz pixel rate,

use a 32 MHz system clock)

Line length (Depends on CCD mode)

Frame length (Depends on CCD mode)

Vwidth (Depends on pixel frequency, 64 pixel counts wide)

Unit Integration: The integration clock frequency is set by a RC circuit of R6 and C6 and is adjusted to 100Hz at the factory,

creating a unit integration time of 10ms. By adjusting R6, the unit integration time can be varied. Because all of the

integration time settings in Table 6: Integration Time Modes are multiples of this unit integration time, the values would

need to be recalculated for any new unit integration time.