Installation Manual

PART 3 – Analog SocketModems Chapter 7 – SocketModem (MT9234SMI)
Multi-Tech Systems, Inc. Universal Socket Hardware Guide for Developers (S000342M) 116
Register Functional Definitions
The following table delineates the assigned bit functions for the twelve internal registers. The assigned bit functions are
more fully defined in the following paragraphs.
Internal Registers
A2 A1 A0 Registe
r
[Default]
Note *3
BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0
General Register Set: Note 1*
0 0 0 RBR [XX] Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
0 0 0 THR [XX] Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
0 0 1 IER [00] 0 0 0 0 Modem
Status
Interrupt
Receive
Line
Status
interrupt
Transmit
Holding
Register
interrupt
Receive
Holding
Register
interrupt
0 1 0 IIR [XX] FIFO
enable
FIFO
enable
0 0 Interrupt
ID
Interrupt
ID
Interrupt
ID
Interrupt
Pending
0 1 0 FCR [00] RX
Trigger
(MSB)
RX
trigger
(LSB)
Detect
change
in FCR
TX FIFO
overrun
bit
0 XMIT
FIFO
reset
RCVR
FIFO
reset
FIFO
enable
0 1 1 LCR [00] Divisor
latch
access
(DLAB)
Set
break
Stick
parity
Even
parity
Parity
enable
0 Word
length
bit-1
Word
length
bit-0
1 0 0 MCR [00] 0 0 0 0 INT enable OUT 1 -RTS -DTR
1 0 1 LSR [60] RX FIFO
data
error
TX
empty
THR
empty
THR
Empty
Break
interrupt
Framing
error
Parity
error
Overrun
error
Receive
data
ready
1 1 0 MSR [X0] CD RI DSR CTS Delta
-CD
Delta
-RI
Delta
-DSR
Delta
-CTS
1 1 1 SCR [FF] Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Special Register Set: Note *2
0 0 0 DLL [00] Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
0 0 1 DLM [00] Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Notes: 1* The General Register set is accessible only when DS is a logic 0.
2* The Baud Rate register set is accessible only when DS is a logic 0 and LCR bit-7 is a logic 1.
3* The value between the square brackets represents the register's initialized HEX value, X = N/A.
RBR – Receive Buffer (RX FIFO)
All eight bits are used for receive channel data (host read/data in; host write/data out). The three error bits
per byte are copied into bits 2, 3, and 4 of the LSR during each host I/O read; therefore, they are available
for monitoring on a per-byte basis.
THR – Transmit Holding Register (TX FIFO)
All eight bits are used for transmit channel data (host write/data out; host read/data in).
IER – Interrupt Enable
Bits 4–7: Reserved and will always read 0.
Bits 0-3: Set by host software only and cleared by software control or host reset.
Bit 3: Enables modem status IRQ. If bits 0–3 of the MSR are set and this bit is set to 1 (enabled), a
host interrupt is generated.
Bit 2: Enables receive line status IRQ. If bits 1–4 (overrun, parity, framing, break errors) of the LSR
are set and this bit is set to a logic 1, a host interrupt is generated.
Bit 1: Enables transmit holding register IRQ. If bit 5 (transmit holding register empty) of the LSR is set
and this bit is set to a 1, a host interrupt is generated.
Bit 0: Enables received data available IRQ. If bit 0 (data ready) of the LSR is set and this bit is set to a
1, a host interrupt is generated.