User's Manual

RPT 633
TM1184 Issue 1 Page 3 - 3
Mode Select Circuit
3. With the mode input at 5V the Speech mode is selected. The output of IC6d is low,
inhibiting the passage of Data by shorting the data path to 0V via D11 and
enabling the passage of Audio by forward biasing D9. Variable resistor RV3
together with R102, R103, R108 and R116 hold the output of IC12d at
approximately 0V, which in turn sets the voltage on varactor diode D8 to give the
nominal carrier frequency of the transmitter.
4. With the mode input at 0V the Data mode is selected and the output of IC6d goes
high, inhibiting the audio path by reverse biasing D9 and allowing data to pass
from IC6b to IC6a.
Audio Input
5. The audio input is amplified and pre-emphasised by IC13b before passing through
the audio gate D9 to the limiting amplifier IC13a, the output of which is limited to
approximately 10V peak to peak. After limiting, the maximum speech deviation is
set by RV4. The signal is then passed to TR12, IC10b and associated components,
which form a modified 0.4dB four section Chebyshev Filter, which has a cut off
frequency of 2.6kHz and a modified frequency response to give an approximate
2dB lift at 2.55kHz. This compensates for the fall off in deviation caused by the
characteristics of the phase locked loop. Filtered audio passes through summing
amplifier IC10a and unity gain buffer IC10d to modulating varactor diode D8.
Summing amplifier IC10a also superimposes the audio signal onto the DC voltage
produced by IC12b.
Data Input
6. Input data may be selected to either pass through IC6c, which inverts it, or bypass
IC6c depending on the setting of data polarity selector link LK3. The data passes
through IC6b and IC6a, the output of which switches between being high impedance
or low impedance to 0V. The frequency of the crystal oscillator does not vary
linearly with the voltage on D8 so the values of resistors R102, R103, R108, R116
and RV5 have been chosen to give a voltage swing, at the output of IC12d, of
approximately +3V to -4.8V as the voltage on the input of IC6b switches between
0V and 5V. The data signal then passes through IC12a, IC12b and associated
components, which form a fourth order Bessel filter, which give the data edges a
controlled risetime of 250µs. After filtering, the signal passes through IC10a and
IC10d to varactor diode D8, RV2 being used to set the data deviation level. The
whole of this modulation path is DC coupled so that a constant logic level on the
input produces a constant deviation of the output frequency.