Technical Manual

TLA 852/FLA 872
TM1205 Issue 2Page 3 - 6
Due to the characteristics of filters FL401, FL402 and FL403, the signal at the input
to the IF amplifier has amplitude modulation (AM). The AM must be removed before
the signal reaches the detector stage. This is performed by the IF amplifier in IC401
which has very high gain and is designed to limit the amplitude of the signal to
remove the AM component and give a ‘square’ output. C479 and C480 provide
de-coupling for the IF amplifier.
The output from the IF amplifier passes to the detector in IC401. This circuit is a
Quadrature Demodulator which has two inputs. One input connects directly to the
IF amplifier, the other receives the signal from the IF amplifier through a phase delay
circuit connected to pins 9 and 10 of the IC. The phase delay depends on the
frequency of the IF signal and is 90 degrees at the centre frequency of the unit’s
allocated channel. The phase shift is provided by ceramic discriminator FL404,
capacitor C426 and resistor R416. C425 is a de-coupling capacitor.
The RSSI circuit in IC401 provides an optional Automatic Gain Control (AGC) signal
for the receiver. The circuit detects the received signal strength and gives a DC
current out. R426 sets the level at which the circuit starts to operate. The value of
68 kilohms sets it to approximately 16 dB above the noise floor. The DC output from
pin 22 of the IC connects to the AGC control circuit. When there is no RSSI output,
transistor TR404 is biased off and keeps the RF amplifier at full gain. At strong
signal levels the output from the RSSI causes TR404 to gradually start conducting,
thus reducing the gain of the RF amplifier. C451 determines the rise and fall times
of the AGC.
The output from the detector stage, pin 11, gives an audio output to TP401. This test
point is used in the final stages of production to align the receiver circuits. TP 401
is also used to program the decoder section of the unit. Pin 11 of IC401 also
connects through R425, R429 and R428 to pin 12. These resistors together with
capacitors C448, C483, C484 and the internal filter amplifier of IC401 form the data
filter; a unity-gain, low-pass filter which reduces high frequency noise.
The output of the data filter connects internally to the FSK Comparator. The data
output of the comparator, from pin 18, connects to the POCSAG Decoder, IC402,
pin 4. A logic signal from IC402, pin 2 to IC401, pin 16 controls the Fast/Slow charge
of the FSK Comparator. At switch-on the logic level is high and the circuit is set to
Fast Charge to allow the voltage on capacitor C492 to be set to the voltage level on
C486. The logic level at pin 16 is then set low which sets the comparator to normal
operation.