Data Sheet

Preliminary Specification Number : SP-ZZ1PJ-331-K
10 / 44
Preliminary & Confidential
< Specification may be changed by Murata without notice >
Murata(China) Investment Co., Ltd.
12. POWER SEQUENCE Timing
12.1. Case 1: 3.3 V power down after 1.8 V
If the battery source can be removed from the end user device (battery removed, AC/DC plugged
in), this is the recommended power sequence. It will avoid violating the power off sequence by
allowing the 3.3 V rail to shut down after the 1.8 V rail.
Notes:
1. VDDIO_GPIO voltage should match VIO voltage from the host. In some applications,
VDDIO_GPIO may connected to 3.3 V upon Host VIO voltage.
2. In this case, both WLAN_EN and BT_EN on the 1PJ are at 3.3 V due to using the VDD_AO
power rail. If the host VIO voltage is 1.8 V, it must have level shifters to interface with host.
3. All host interface signals must stay floating or low before valid power on sequence (WLAN_EN
and BT-EN goes high).
Symbol
Parameter
Min
Max
Units
t
a1
No requirement if VDDIO_AO connected to 3.3 V
0
-
μs
t
a2
90% of 3.3 V to 10% of 1.8 V
0
-
μs
t
a3
90% of VDDIO_GPIO to 0.7 V of both WLAN_EN and BT_EN
10
-
μs
t
a4
WLAN_EN valid to LF_CLK_IN input
0
-
μs
t
a5
WLAN_EN de-assert (“low”) to LF_CLK_IN de-assert
(tristate or low)
0
-
μs
t
a6
Both WLAN_EN = low and BT_EN = low to 90% of 1.8 V
10
-
μs
t
a7
3.3 V always higher than 1.8 V during operation, with power
off by removing battery or unplugging AC/DC
0
-
μs
t
a8
VDDIO_AO and VDDIO_XTAL should be connected to 3.3 V
power rail
0
-
μs