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Manual SDs-01 D 3.2.2003 17:45 Uhr Seite 16

»CLK MULTIPLIER« 6

Both S/P-DIF outputs, optical and coaxial, transmit same clock rate settings.

For the S/P-DIF output pair no. 6 are 3 multiply functions available:

x 1, x 2, x 4

Due to the maximum possible S/P-DIF clock frequency of 192.0kHz, the

functions of these multipliers are depending on the basis clock rate of the

incoming reference signal. The factory default is set at x 1.

Example 1

The incoming basis clock runs at 32.0kHz, 44.1kHz or 48.0kHz:

x 1: S/PDIF outputs run at 32.0kHz, 44.1kHz or 48.0kHz

x 2: S/PDIF outputs run at 64.0kHz, 88.2kHz or 96.0kHz

x 4: S/PDIF outputs run at 128.0kHz, 176.4kHz or 192.0kHz

Example 2

The incoming basis clock runs at 88.2kHz or 96.0kHz:

x 1: S/PDIF outputs run at 88.2kHz or 96.0kHz

x 2: S/PDIF outputs run at 176.4kHz or 192.0kHz

x 4: S/PDIF outputs run at 176.4kHz or 192.0kHz

Example 3

The incoming basis clock runs at 176.4kHz or 192.0kHz:

x 1: S/PDIF outputs run at 176.4kHz or 192.0kHz

x 2: S/PDIF outputs run at 176.4kHz or 192.0kHz

x 4: S/PDIF outputs run at 176.4kHz or 192.0kHz

STATUS

This area displays different system conditions of your MC-7. There is no

access for changing settings.

»LOCK«

This blue LED lights when the internal PLL circuit has detected the incoming

clock reference signal as valid. If the reference signal is unstable or lost, the

»LOCK« LED does not light.

»HOLD«

This red LED lights when the external reference clock signal is interrupted

or lost and the HOLD functionality is selected in the REFERENCE menu.

During this, all output signals are available continuously.

»AUDIO«

This red LED lights when a valid AES3 or S/P-DIF optical or coaxial digital

audio reference signal is detected at the corresponding input.

CLOCK IN

This area displays the clock rate of the incoming reference clock signal. The

following basis reference clock rates are supported and will be analyzed:

32.0kHz

44.1kHz

48.0kHz

88.2kHz

96.0kHz

176.4kHz 192.0kHz

Word Clock Rates

These indications are only available if

the internal PLL circuit is locked stably

to the external reference signal and the

corresponding blue LOCK LED lights

permanently.

Regarding the display of incoming Super Clock rates, please refer to page

16 under „Locking so-called »Super Clocks«“.

CLOCK IN

STATUS