Technical data
Clock References for the
X-SRC Modes
Using the X-SRC mode, the MC-6 extracts
the needed clock rates out of the incoming
digital audio signals. Thereby, the system
does not need and does not accept any
additional external applied clock reference
signals.
!
23
This setting allows to receive an AES3 signal and an AES3id simultaneously.
The AES3 input signal is converted to AES3id and the AES3id signal is con-
verted to the AES3. The clock rate of the incoming AES3 signal is extracted
by the second PLL synthesizer and supplied as clock reference to the first
SRC, which feeds the AES3 output. The clock rate of the incoming AES3id si-
gnal is extracted by the first PLL synthesizer and supplied as clock reference
to the second SRC, which feeds the AES3id output.
That means, the AES3 input is predefined as clock source for the first SRC,
the AES3 output. The AES3id input is predefined as clock source for the
second SRC, the AES3id output. There are no other adjustments for clock
sources possible within the X-SRC mode.
When the incoming digital audio signals can be locked as clock references
by the PLLs, the blue LEDs »LOCK« in the STATUS menu will light constant-
ly. The clock rate of the clock sources are displayed in the »REF CLOCK
IN«
menu under »1« and »2«. The identifier »1« generally indicates the samp-
ling rate of the first digital audio format selected in the »AUDIO IN« menu,
seen from above of the LED row. The identifier »2« generally indicates the
sampling rate of the second digital audio format, displayed below the first
one.
X-SRC Mode between
AES3 and S/P-DIF optical
X-SRC
BI-DIR
UNI-DIR AES3
S/P-DIF op SRC
REFERENCE
88.2
48.0
44.1
32.0
192.0
96.0
176.4
MODE
AES3id
S/P-DIF co
AUDIO
IN
AES11
WCLK AES3
S/P-DIF op
AES3id
S/P-DIF co
This setting allows to receive an AES3 and S/P-DIF optical signal simultane-
ously for bidirectional fomat and sampling rate conversion using the X-SRC
mode. The procedure is the same as described above.
X-SRC Mode between
AES3 and S/P-DIF coaxial
X-SRC
BI-DIR
UNI-DIR AES3
S/P-DIF op SRC
REFERENCE
88.2
48.0
44.1
32.0
192.0
96.0
176.4
MODE
AES3id
S/P-DIF co
AUDIO
IN
AES11
WCLK AES3
S/P-DIF op
AES3id
S/P-DIF co
This setting allows to receive an AES3 and S/P-DIF coaxial signal simultane-
ously for bidirectional fomat and sampling rate conversion using the X-SRC
mode. The procedure is the same as described above.
Input:
AES3id
44.1kHz
Output:
AES3id
44.1kHz
Output:
AES3
48.0kHz
Input:
AES3
48.0kHz
1. PLL:
Clock Extraction
44.1kHz
2. SRC:
Clock Conversion
44.1kHz
k
48.0kHz
2. PLL:
Clock Extraction
48.0kHz
1. SRC:
Clock Conversion
44.1kHz
m
48.0kHz
Clock
44.1kHz
Clock
48.0kHz
MC-6: X-SRC Mode
Effects Processor
44.1kHz
Digital Mixing Desk
48.0kHz