Specifications

Principles of Operation

All Myrinet/PCI-X NICs include a RISC processor to execute the Myrinet Control

Program (MCP), local memory, a packet interface to and from the Myrinet port, and a

versatile DMA controller to support zero-copy APIs. Each of these parts supports high-

availability and data-integrity features, such as “heartbeat” link-continuity monitoring,

packet checksums, and memory parity.

The difference between the PCIXD and PCIXE or PCIXF NICs is the allowed clock rate

of the RISC and local memory: 225MHz for the PCIXD, and 333MHz for the PCIXE and

PCIXF. The Fiber NICs contain conversion circuitry between the SAN port of the Lanai

chip and the external port. For the Fiber (M3F) NIC pictured below, the conversion

circuitry consists of a SerDes-SAN chip, a SerDes (Serializer-Deserializer) chip, and the

Fiber transceiver.

Memory

Power

Regulator

Test

Connector

Lanai

EEPROM

Serializer-Deserializer

(SerDes)

PCIXD NIC

PCI connector

LEDs Fiber connecto

The front panel of the PCI-Short-Card NIC pictured above is the vertical metal plate on

the left-hand side of the NIC. Two LEDs and the cable connector penetrate this PCI front

panel (also known as a face plate).