User manual

8X96 ADC and DAC User Manual Page 11 of 54
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and cleaned up from jitter. The data path is 24 bit. No noise shaping can be performed on
digital input data. If a bit splitting method is used , a bit-split signal arriving at the digital
input can be decoded and output digitally at the proper wordlength (see the next chapter).
During normal operation, when the analog input (ADC) is selected as the signal source,
the digital signal is present at both the AES outputs and the output of one the optional
DIO card. If the A/D is outfitted with two such cards, the active one is selected using
internal DIP Switch (see “Special DIP Switch Options”).
It is also possible to select either AES/EBU or any of the installed optional DIO (MDM
card) as inputs. In this case the digital signal is looped through to the AES outputs as
well as the outputs of the optional interface. Any interface specific flags except emphasis
are dropped. Output sampling rate flags are set according to that of the sampling rate
selector switch. There are only flags for 44.1 and 48k: 88.2 and 96k are not flagged as
there is currently no AES/EBU standard for flagging high sample rates. The signal clock
is regenerated and the internal clock PLL removes incoming clock jitter, so jitter is
attenuated from the ADC digital output.
The AES/EBU interface will pass through (from its inputs to outputs) even 4
asynchronous signals. The format conversion, however, requires pairs to be synchronous
as only the clock of pair #1/2 is used for format conversion. If less than 4 pairs are used,
at least one pair should be feeding channels #1/2.
For example: if you need to record a stereo AES/EBU signal on your eight channel MDM
machine on tracks #7/8 only, feed the signal to input #1/2 and the loop the AES output
#1/2 to the AES input #7/8. Arm only tracks #7/8 and you are ready to go.
A stripped wordclock is present at the wordclock output. This signal is stripped off the
clock of incoming signal. If AES/EBU input is selected, the wordclock is stripped from
the pair #1/2 only. The chapter “Special DIP Switch Options” describes how to set
wordclock output to be either 44/48 or 88/96, depending on application.
The 8X96 ADC does not do sample rate conversion.