Click here to comment on this document via the National Instruments website at http://www.natinst.com/documentation/daq/ AT-MIO/AI E Series User Manual Multifunction I/O Boards for the PC AT May 1996 Edition Part Number 320517E-01 Copyright 1994, 1996 National Instruments Corporation. All Rights Reserved.
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Important Information Warranty The AT-MIO/AI E Series boards are warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
Table of Contents About This Manual Organization of This Manual ........................................................................................xi Conventions Used in This Manual ................................................................................xii National Instruments Documentation ...........................................................................xiii Related Documentation .................................................................................................
Table of Contents Chapter 3 Hardware Overview Analog Input ................................................................................................................. 3-6 Input Mode ..................................................................................................... 3-6 Input Polarity and Input Range ...................................................................... 3-7 Considerations for Selecting Input Ranges ...................................... 3-10 Dither ..................
Table of Contents Power Connections ........................................................................................................4-30 Timing Connections ......................................................................................................4-30 Programmable Function Input Connections ...................................................4-31 Data Acquisition Timing Connections ...........................................................4-32 SCANCLK Signal .............................
Table of Contents Appendix A Specifications AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 ................................................ A-1 AT-MIO-16E-10 and AT-MIO-16DE-10 .................................................................... A-11 AT-MIO-16XE-10 and AT-AI-16XE-10 ..................................................................... A-19 AT-MIO-16XE-50 ........................................................................................................
Table of Contents Figure 4-1. I/O Connector Pin Assignment for the AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-16E-10, AT-MIO-16XE-10, AT-AI-16XE-10, and AT-MIO-16XE-50 ..............................................4-2 Figure 4-2. I/O Connector Pin Assignment for the AT-MIO-64E-3 ..........................4-3 Figure 4-3. I/O Connector Pin Assignment for the AT-MIO-16DE-10 .....................4-4 Figure 4-4. AT E Series PGIA ....................................................................................
Table of Contents Figure B-1. Figure B-2. Figure B-3. Figure B-4. Figure B-5. Figure B-6. 68-Pin MIO Connector Pin Assignments ................................................ B-2 68-Pin DIO Connector Pin Assignments ................................................ B-3 68-Pin Extended Analog Input Connector Pin Assignments .................. B-4 50-Pin MIO Connector Pin Assignments ................................................ B-5 50-Pin DIO Connector Pin Assignments ...................................
About This Manual This manual describes the electrical and mechanical aspects of each board in the AT E Series product line and contains information concerning their operation and programming. Unless otherwise noted, text applies to all boards in the AT E Series.
About This Manual • Chapter 4, Signal Connections, describes how to make input and output signal connections to your AT E Series board via the board I/O connector. • Chapter 5, Calibration, discusses the calibration procedures for your AT E Series board. • Appendix A, Specifications, lists the specifications of each board in the AT E Series. • Appendix B, Optional Cable Connector Descriptions, describes the connectors on the optional cables for the AT E Series boards.
About This Manual ♦ The ♦ indicates that the text following it applies only to specific AT E Series boards. <> Angle brackets containing numbers separated by an ellipsis represent a range of values associated with a bit, port, or signal name (for example, ACH<0..7> stands for ACH0 through ACH7). Abbreviations, acronyms, metric prefixes, mnemonics, symbols, and terms are listed in the Glossary at the end of this manual.
About This Manual relevant pieces of the system. Consult these guides when you are making your connections. • SCXI chassis manuals—If you are using SCXI, read these manuals for maintenance information on the chassis and installation instructions.
Chapter Introduction 1 This chapter describes the AT E Series boards, lists what you need to get started, describes the optional software and optional equipment, and explains how to unpack your AT E Series board. About the AT E Series Thank you for buying a National Instruments AT E Series board. The AT E Series boards are the first completely Plug and Play-compatible multifunction analog, digital, and timing I/O boards for the PC AT and compatible computers.
Chapter 1 Introduction timing event. The AT E Series boards have the Real-Time System Integration (RTSI) bus to solve this problem. The RTSI bus consists of our RTSI bus interface and a ribbon cable to route timing and trigger signals between several functions on as many as five DAQ boards in your PC. The AT E Series boards can interface to an SCXI system so that you can acquire over 3,000 analog signals from thermocouples, RTDs, strain gauges, voltage sources, and current sources.
Chapter 1 Introduction Software Programming Choices There are several options to choose from when programming your National Instruments DAQ and SCXI hardware. You can use LabVIEW, LabWindows/CVI, NI-DAQ, or register-level programming. LabVIEW and LabWindows/CVI Application Software LabVIEW and LabWindows/CVI are innovative program development software packages for data acquisition and control applications.
Chapter 1 Introduction NI-DAQ has both high-level DAQ I/O functions for maximum ease of use and low-level DAQ I/O functions for maximum flexibility and performance. Examples of high-level functions are streaming data to disk or acquiring a certain number of data points. An example of a low-level function is writing directly to registers on the DAQ device. NI-DAQ does not sacrifice the performance of National Instruments DAQ devices because it lets multiple devices operate at their peak performance.
Chapter 1 Introduction You can use your AT E Series board, together with other PC, AT, EISA, DAQCard, and DAQPad Series DAQ and SCXI hardware, with NI-DAQ software for PC compatibles. Register-Level Programming The final option for programming any National Instruments DAQ hardware is to write register-level software. Writing register-level programming software can be very time-consuming and inefficient and is not recommended for most users.
Chapter 1 Introduction Custom Cabling National Instruments offers cables and accessories for you to prototype your application or to use if you frequently change board interconnections. If you want to develop your own cable, however, the following guidelines may be useful: • For the analog input signals, shielded twisted-pair wires for each analog input pair yield the best results, assuming that you use differential inputs. Tie the shield for each signal pair to the ground reference at the source.
Chapter 1 Introduction Unpacking Your AT E Series board is shipped in an antistatic package to prevent electrostatic damage to the board. Electrostatic discharge can damage several components on the board. To avoid such damage in handling the board, take the following precautions: • Ground yourself via a grounding strap or by holding a grounded object. • Touch the antistatic package to a metal part of your computer chassis before removing the board from the package.
Chapter Installation and Configuration 2 This chapter explains how to install and configure your AT E Series board. Software Installation You may need to install your software before you install your AT E Series board. Refer to the appropriate release notes indicated below for specific instructions on the software installation sequence. If you are using NI-DAQ, refer to the NI-DAQ User Manual for PC Compatibles Version 4.9.0 Release Notes.
Chapter 2 Installation and Configuration 1. Write down the AT E Series board serial number in the AT E Series Hardware and Software Configuration Form in Appendix D at the back of this manual. You will need this serial number when you install and configure your software. 2. Turn off and unplug your computer. 3. Remove the top cover or access port to the I/O channel. 4. Remove the expansion slot cover on the back panel of the computer. 5.
Chapter 2 Installation and Configuration Plug and Play The AT E Series boards are fully compatible with the industry-standard Plug and Play ISA specification. A Plug and Play system arbitrates and assigns resources through software, freeing you from manually setting switches and jumpers. These resources include the board base I/O address, DMA channels, and interrupt channels. Each AT E Series board is configured at the factory to request these resources from the Plug and Play Configuration Manager.
Chapter 2 Installation and Configuration 16-bit DMA channels, which correspond to channels 5, 6, and 7 in an ISA computer and channels 0, 1, 2, 3, 5, 6, and 7 in an EISA computer. These selections are all software configured and do not require you to manually change any settings on the board. Interrupt Channel Selection The AT E Series boards can increase bus efficiency by using an interrupt channel. You can use an interrupt channel for event notification without the use of polling techniques.
Chapter 2 Table 2-1.
Chapter 2 Installation and Configuration Table 2-2.
Chapter 2 Table 2-3. PC AT 16-bit DMA Channel Assignment Map Channel Note: Installation and Configuration Device 7 AT-MIO-16 series – default 6 AT-MIO-16 series – default AT-DIO-32F – default 5 AT-DIO-32F – default 4 Cascade for DMA Controller #1 (channels 0 through 3) EISA computers also have channels 0–3 available as 16-bit DMA channels.
Chapter 3 Hardware Overview This chapter presents an overview of the hardware functions on your AT E Series board.
Chapter 3 Hardware Overview Figure 3-2 shows the block diagram for the AT-MIO-64E-3.
Chapter 3 Hardware Overview Figure 3-3 shows the block diagram for the AT-MIO-16E-10 and AT-MIO-16DE-10.
Chapter 3 Hardware Overview Figure 3-4 shows a block diagram for the AT-MIO-16XE-10.
Chapter 3 Hardware Overview Figure 3-5 shows a block diagram for the AT-AI-16XE-10.
Chapter 3 Hardware Overview Figure 3-6 shows a block diagram for the AT-MIO-16XE-50.
Chapter 3 Hardware Overview programmed on a per channel basis for multimode scanning. For example, you can configure the circuitry to scan 12 channels—four differentially configured channels and eight single-ended channels. Table 3-1 describes the three input configurations. Table 3-1. Available Input Configurations for the AT E Series Configuration Description DIFF A channel configured in DIFF mode uses two analog channel input lines.
Chapter 3 Hardware Overview You can program polarity and range settings on a per channel basis so that you can configure each input channel uniquely. The software-programmable gain on these boards increases their overall flexibility by matching the input signal ranges to those that the ADC can accommodate. The AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-64E-3, AT-MIO-16E-10, and AT-MIO-16DE-10 have gains of 0.5, 1, 2, 5, 10, 20, 50, and 100 and are suited for a wide variety of signal levels.
Chapter 3 ♦ Hardware Overview AT-MIO-16XE-10, AT-AI-16XE-10, AT-MIO-16XE-50 These boards have two input polarities—unipolar and bipolar. Unipolar input means that the input voltage range is between 0 and Vref, where Vref is a positive reference voltage. Bipolar input means that the input voltage range is between -Vref and +Vref. The AT-MIO-16XE-10, AT-AI-16XE-10, and AT-MIO-16XE-50 have a unipolar input range of 10 V (0 to 10 V) and a bipolar input range of 20 V (±10 V).
Chapter 3 Hardware Overview Table 3-3. Actual Range and Measurement Precision, AT-MIO-16XE-10, AT-AI-16XE-10, and AT-MIO-16XE-50 Range Configuration Gain Actual Input Range Precision1 0 to +10 V 1.0 2.0 5.02 10.0 20.02 50.02 100.0 0 to +10 V 0 to +5 V 0 to +2 V 0 to +1 V 0 to +500 mV 0 to +200 mV 0 to 100 mV 152.59 µV 76.29 µV 30.52 µV 15.26 µV 7.63µV 3.05 µV 1.53 µV -10 to +10 V 1.0 2.0 5.02 10.0 20.02 50.02 100.
Chapter 3 Hardware Overview Dither When you enable dither, you add approximately 0.5 LSB rms of white Gaussian noise to the signal to be converted by the ADC. This addition is useful for applications involving averaging to increase the resolution of your AT E Series board, as in calibration or spectral analysis. In such applications, noise modulation is decreased and differential linearity is improved by the addition of the dither.
Chapter 3 Hardware Overview LSBs 6.0 LSBs 6.0 4.0 4.0 2.0 2.0 0.0 0.0 -2.0 -2.0 -4.0 -4.0 -6.0 -6.0 0 100 200 300 400 0 500 a. Dither disabled; no averaging 100 200 300 400 500 b. Dither disabled; average of 50 acquisitions LSBs 6.0 LSBs 6.0 4.0 4.0 2.0 2.0 0.0 0.0 -2.0 -2.0 -4.0 -4.0 -6.0 -6.0 0 100 200 300 400 500 0 c. Dither enabled; no averaging 100 200 300 400 500 d. Dither enabled; average of 50 acquisitions Figure 3-7.
Chapter 3 Hardware Overview constant and source impedances are low. Refer to Appendix A, Specifications, for a complete listing of settling times for each of the AT E Series boards. When scanning among channels at various gains, the settling times may increase. When the PGIA switches to a higher gain, the signal on the previous channel may be well outside the new, smaller range.
Chapter 3 Hardware Overview Analog Output ♦ AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-64E-3, AT-MIO-16E-10, AT-MIO-16DE-10 The AT E Series boards supply two channels of analog output voltage at the I/O connector. You can select the reference and range for the analog output circuitry through software. The reference can be either internal or external, whereas the range can be either bipolar or unipolar. ♦ AT-MIO-16XE-50 The AT-MIO-16XE-50 supplies two channels of analog output voltage at the I/O connector.
Chapter 3 Hardware Overview Selecting a bipolar range for a particular DAC means that any data written to that DAC will be interpreted as two’s complement format. In two’s complement mode, data values written to the analog output channel can be either positive or negative. If you select unipolar range, data is interpreted in straight binary format. In straight binary mode, data values written to the analog output channel range must be positive.
Chapter 3 Hardware Overview shown in Figure 3-8. The trigger-level range for the direct analog channel is ±10 V in 78 mV steps for the AT-MIO-16E-1, AT-MIO-16E-2, and AT-MIO-64E-3, and ±10 V in 4.9 mV steps for the AT-MIO-16XE-10 and AT-AI-16XE-10.
Chapter 3 Hardware Overview lowValue Trigger Figure 3-9. Below-Low-Level Analog Triggering Mode In above-high-level analog triggering mode, the trigger is generated when the signal value is greater than highValue. LowValue is unused. highValue Trigger Figure 3-10. Above-High-Level Analog Triggering Mode In inside-region analog triggering mode, the trigger is generated when the signal value is between the lowValue and the highValue. highValue lowValue Trigger Figure 3-11.
Chapter 3 Hardware Overview In high-hysteresis analog triggering mode, the trigger is generated when the signal value is greater than highValue, with the hysteresis specified by lowValue. highValue lowValue Trigger Figure 3-12. High-Hysteresis Analog Triggering Mode In low-hysteresis analog triggering mode, the trigger is generated when the signal value is less than lowValue, with the hysteresis specified by highValue. highValue lowValue Trigger Figure 3-13.
Chapter 3 Hardware Overview Digital I/O The AT E Series boards contain eight lines of digital I/O for general-purpose use. You can individually configure each line through software for either input or output. The AT-MIO-16DE-10 has 24 additional DIO lines, configured as three 8-bit ports: PA<0..7>, PB<0..7>, and PC<0..7>. You can configure each port for both input and output in various combinations, with some handshaking capabilities.
Chapter 3 Hardware Overview RTSI Trigger <0..6> CONVERT* PFI<0..9> Sample Interval Counter TC GPCTR0_OUT Figure 3-14. CONVERT* Signal Routing This figure shows that CONVERT* can be generated from a number of sources, including the external signals RTSI<0..6> and PFI<0..9> and the internal signals Sample Interval Counter TC and GPCTR0_OUT.
Chapter 3 Hardware Overview You can also individually enable each of the PFI pins to output a specific internal timing signal. For example, if you need the UPDATE* signal as an output on the I/O connector, software can turn on the output driver for the PFI5/UPDATE* pin. Board and RTSI Clocks Many functions performed by the AT E Series boards require a frequency timebase to generate the necessary timing signals for controlling A/D conversions, DAC updates, or general-purpose signals at the I/O connector.
Chapter 3 Hardware Overview DAQ-STC TRIG1 TRIG2 CONVERT* UPDATE* GPCTR0_SOURCE Trigger 7 RTSI Switch RTSI Bus Connector WFTRIG GPCTR0_GATE GPCTR0_OUT STARTSCAN AIGATE SISOURCE UISOURCE GPCTR1_SOURCE GPCTR1_GATE Clock switch RTSI_OSC (20 MHz) Figure 3-15. RTSI Bus Signal Connection Refer to the Timing Connections section of Chapter 4 for a description of the signals shown in Figure 3-15.
Chapter 4 Signal Connections This chapter describes how to make input and output signal connections to your AT E Series board via the board I/O connector. The I/O connector for the AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-16E-10, AT-MIO-16XE-10, AT-AI-16XE-10, and AT-MIO-16XE-50 has 68 pins that you can connect to 68-pin accessories with the SH6868 shielded cable or the R6868 ribbon cable.
Chapter 4 Signal Connections ACH8 ACH1 AIGND ACH10 ACH3 AIGND ACH4 AIGND ACH13 ACH6 AIGND ACH15 1 DAC0OUT 1 DAC1OUT 2 EXTREF DIO4 DGND DIO1 DIO6 DGND +5 V DGND DGND PFI0/TRIG1 PFI1/TRIG2 DGND +5 V DGND PFI5/UPDATE* PFI6/WFTRIG DGND PFI9/GPCTR0_GATE GPCTR0_OUT FREQ_OUT 1 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 ACH0 AIGND ACH9 ACH2 AIGND ACH11 AISENSE
Chapter 4 AIGND AIGND ACH0 ACH8 ACH1 ACH9 ACH2 ACH10 ACH3 ACH11 ACH4 ACH12 ACH5 ACH13 ACH6 ACH14 ACH7 ACH15 AISENSE DAC0OUT DAC1OUT EXTREF AOGND DGND DIO0 DIO4 DIO1 DIO5 DIO2 DIO6 DIO3 DIO7 DGND +5 V +5 V SCANCLK EXTSTROBE* PFI0/TRIG1 PFI1/TRIG2 PFI2/CONVERT* PFI3/GPCTR1_SOURCE PFI4/GPCTR1_GATE GPCTR1_OUT PFI5/UPDATE* PFI6/WFTRIG PFI7/STARTSCAN PFI8/GPCTR0_SOURCE PFI9/GPCTR0_GATE GPCTR0_OUT FREQ_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Chapter 4 Signal Connections AIGND AIGND ACH0 ACH8 ACH1 ACH9 ACH2 ACH10 ACH3 ACH11 ACH4 ACH12 ACH5 ACH13 ACH6 ACH14 ACH7 ACH15 AISENSE DAC0OUT DAC1OUT EXTREF AOGND DGND DIO0 DIO4 DIO1 DIO5 DIO2 DIO6 DIO3 DIO7 DGND +5 V +5 V SCANCLK EXTSTROBE* PFI0/TRIG1 PFI1/TRIG2 PFI2/CONVERT* PFI3/GPCTR1_SOURCE PFI4/GPCTR1_GATE GPCTR1_OUT PFI5/UPDATE* PFI6/WFTRIG PFI7/STARTSCAN PFI8/GPCTR0_SOURCE PFI9/GPCTR0_GATE GPCTR0_OUT FREQ_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Chapter 4 Signal Connections I/O Connector Signal Descriptions Reference Direction Description AIGND — — Analog Input Ground—These pins are the reference point for single-ended measurements and the bias current return point for differential measurements. All three ground references—AIGND, AOGND, and DGND—are connected together on your AT E Series board. ACH<0..15> AIGND Input Analog Input Channels 0 through 15—Each channel pair, ACH (i = 0..
Chapter 4 Signal Connections Reference Direction Description DIO<0..7> DGND Input or Output Digital I/O signals—DIO6 and 7 can control the up/down signal of general-purpose counters 0 and 1, respectively. PA<0..7> DGND Input or Output Port A—These pins are port A of the extra digital I/O signals on the AT-MIO-16DE-10. PB<0..7> DGND Input or Output Port B—These pins are port B of the extra digital I/O signals on the AT-MIO-16DE-10. PC<0..
Chapter 4 Signal Name PFI2/CONVERT* PFI3/GPCTR1_SOURCE PFI4/GPCTR1_GATE Signal Connections Reference Direction Description DGND Input PFI2/Convert—As an input, this is one of the PFIs. Output As an output, this is the CONVERT* signal. A high-to-low edge on CONVERT* indicates that an A/D conversion is occurring. Input PFI3/Counter 1 Source—As an input, this is one of the PFIs. Output As an output, this is the GPCTR1_SOURCE signal.
Chapter 4 Signal Connections Signal Name PFI9/GPCTR0_GATE Reference Direction Description DGND Input PFI9/Counter 0 Gate—As an input, this is one of the PFIs. Output As an output, this is the GPCTR0_GATE signal. This signal reflects the actual gate signal connected to the general-purpose counter 0. (Continued) GPCTR0_OUT DGND Output Counter 0 Output—This output is from the general-purpose counter 0 output.
Chapter 4 Table 4-1. Signal Connections I/O Signal Summary, AT-MIO-16E-1, AT-MIO-16E-2, and AT-MIO-64E-3 (Continued) Signal Name Drive Impedance Input/ Output Protection (Volts) On/Off Source (mA at V) Sink (mA at V) Rise Time (ns) Bias 1.1 50 kΩ pu1 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu 10 kΩ Vcc +0.5/±35 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu2 DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu PFI2/CONVERT* DIO — Vcc +0.
Chapter 4 Signal Connections Table 4-2 shows the I/O signal summary for the AT-MIO-16E-10 and AT-MIO-16DE-10. Table 4-2. Signal Name Drive I/O Signal Summary, AT-MIO-16E-10 and AT-MIO-16DE-10 Impedance Input/ Output Protection (Volts) On/Off Source (mA at V) Sink Rise (mA at V) Time (ns) Bias ACH<0..15> AI 100 GΩ in parallel with 50 pF 35/25 — — — ±200 pA AISENSE AI 100 GΩ in parallel with 50 pF 35/25 — — — ±200 pA AIGND AO — — — — — — DAC0OUT AO 0.
Chapter 4 Table 4-2. Signal Connections I/O Signal Summary, AT-MIO-16E-10 and AT-MIO-16DE-10 (Continued) Signal Name Drive PFI3/GPCTR1_SOURCE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu PFI4/GPCTR1_GATE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu GPCTR1_OUT DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu PFI5/UPDATE* DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu PFI6/WFTRIG DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.
Chapter 4 Signal Connections Table 4-3 shows the I/O signal summary for the AT-MIO-16XE-10 and AT-AI-16XE-10. Table 4-3. Signal Name I/O Signal Summary, AT-MIO-16XE-10 and AT-AI-16XE-10 Drive Impedance Input/ Output Sink (mA at V) Rise Time (ns) ACH<0..15> AI 100 GΩ in parallel with 100 pF 25/15 — — — ±1 nA AISENSE AI 100 GΩ in parallel with 100 pF 25/15 — — — ±1 nA AIGND AO — — — — — — DAC0OUT AO 0.1 Ω Short-circuit to ground 5 at 10 5 at -10 5 V/µs — DAC1OUT AO 0.
Chapter 4 Table 4-3. Signal Name Signal Connections I/O Signal Summary, AT-MIO-16XE-10 and AT-AI-16XE-10 (Continued) Drive Impedance Input/ Output Protection (Volts) On/Off Source (mA at V) Sink (mA at V) Rise Time (ns) Bias PFI5/UPDATE* DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu PFI6/WFTRIG DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu PFI7/STARTSCAN DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu PFI8/GPCTR0_SOURCE DIO — Vcc +0.5 3.
Chapter 4 Signal Connections Table 4-4 shows the I/O signal summary for the AT-MIO-16XE-50. Table 4-4. Signal Name I/O Signal Summary, AT-MIO-16XE-50 Drive Impedance Input/ Output Sink (mA at V) Rise Time (ns) ACH<0..15> AI 20 GΩ in parallel with 100 pF 25/15 — — — ±3 nA AISENSE AI 20 GΩ in parallel with 100 pF 25/15 — — — ±3 nA AIGND AO — — — — — — DAC0OUT AO 0.1 Ω Short-circuit to ground 5 at 10 5 at -10 2 V/µs — DAC1OUT AO 0.
Chapter 4 Table 4-4. Signal Name Drive Signal Connections I/O Signal Summary, AT-MIO-16XE-50 (Continued) Impedance Input/ Output Protection (Volts) On/Off Source (mA at V) Sink (mA at V) Rise Time (ns) Bias PFI5/UPDATE* DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu PFI6/WFTRIG DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu PFI7/STARTSCAN DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu PFI8/GPCTR0_SOURCE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.
Chapter 4 Signal Connections Analog Input Signal Connections ♦ AT-MIO-16E-1, ΑΤ-MIO-16E-2, AT-MIO-16E-10, AT-MIO-16DE-10, AT-MIO-16XE-10, AT-AI-16XE-10, AT-MIO-16XE-50 The analog input signals are ACH<0..15>, AISENSE, and AIGND. The ACH<0..15> signals are tied to the 16 analog input channels of your AT E Series board. In single-ended mode, signals connected to ACH<0..15> are routed to the positive input of the board PGIA. In differential mode, signals connected to ACH<0..
Chapter 4 Signal Connections use the PGIA in different ways. Figure 4-4 shows a diagram of your AT E Series board PGIA. Instrumentation Amplifier Vin+ + + PGIA Vm - Vin- Measured Voltage Vm = [Vin+ - Vin-]* Gain Figure 4-4. AT E Series PGIA The PGIA applies gain and common-mode voltage rejection and presents high input impedance to the analog input signals connected to your AT E Series board.
Chapter 4 Signal Connections Types of Signal Sources When configuring the input channels and making signal connections, you must first determine whether the signal sources are floating or ground-referenced. The following sections describe these two types of signals. Floating Signal Sources A floating signal source is one that is not connected in any way to the building ground system but, rather, has an isolated ground-reference point.
Chapter 4 Signal Connections Figure 4-5 summarizes the recommended input configuration for both types of signal sources.
Chapter 4 Signal Connections Differential Connection Considerations (DIFF Input Configuration) A differential connection is one in which the AT E Series board analog input signal has its own reference signal or signal return path. These connections are available when the selected channel is configured in DIFF input mode. The input signal is tied to the positive input of the PGIA, and its reference signal, or return, is tied to the negative input of the PGIA.
Chapter 4 Signal Connections Differential Connections for Ground-Referenced Signal Sources Figure 4-6 shows how to connect a ground-referenced signal source to an AT E Series board channel configured in DIFF input mode. ACH<0..7> GroundReferenced Signal Source + Vs + - Instrumentation Amplifier PGIA + ACH<8..15> CommonMode Noise and Ground Potential Measured Voltage Vm - + V cm - Input Multiplexers AISENSE AIGND I/O Connector Selected Channel in DIFF Configuration Figure 4-6.
Chapter 4 Signal Connections Differential Connections for Nonreferenced or Floating Signal Sources Figure 4-7 shows how to connect a floating signal source to an AT E Series board channel configured in DIFF input mode. ACH<0..7> Floating Signal Source + Bias resistors (see text) VS + - Instrumentation Amplifier PGIA + ACH<8..15> Measured Voltage Vm - Bias Current Return Paths Input Multiplexers AISENSE AIGND I/O Connector Selected Channel in DIFF Configuration Figure 4-7.
Chapter 4 Signal Connections any resistors at all. This connection works well for DC-coupled sources with low source impedance (less than 100 Ω). However, for larger source impedances, this connection leaves the differential signal path significantly out of balance. Noise that couples electrostatically onto the positive line does not couple onto the negative line because it is connected to ground.
Chapter 4 Signal Connections Single-Ended Connection Considerations A single-ended connection is one in which the AT E Series board analog input signal is referenced to a ground that can be shared with other input signals. The input signal is tied to the positive input of the PGIA, and the ground is tied to the negative input of the PGIA. When every channel is configured for single-ended input, up to 16 analog input channels are available (up to 64 channels on the AT-MIO-64E-3).
Chapter 4 Signal Connections Single-Ended Connections for Floating Signal Sources (RSE Configuration) Figure 4-8 shows how to connect a floating signal source to an AT E Series board channel configured for RSE mode. ACH<0..15> Floating Signal Source + + Vs Instrumentation Amplifier PGIA - + Input Multiplexers AISENSE Measured Voltage Vm - AIGND I/O Connector Selected Channel in RSE Configuration Figure 4-8.
Chapter 4 Signal Connections Figure 4-9 shows how to connect a grounded signal source to an AT E Series board channel configured for NRSE mode. ACH<0..15> + GroundReferenced Signal Source + Vs Instrumentation Amplifier PGIA - + Input Multiplexers CommonMode Noise and Ground Potential + AISENSE AIGND Vcm Measured Voltage Vm - - Selected Channel in NRSE Configuration I/O Connector Figure 4-9.
Chapter 4 Signal Connections Analog Output Signal Connections The analog output signals are DAC0OUT, DAC1OUT, EXTREF, and AOGND. DAC0OUT and DAC1OUT are not available on the AT-AI-16XE-10. EXTREF is not available on the AT-MIO-16XE-10, AT-AI-16XE-10, or AT-MIO-16XE-50. DAC0OUT is the voltage output signal for analog output channel 0. DAC1OUT is the voltage output signal for analog output channel 1. EXTREF is the external reference input for both analog output channels.
Chapter 4 Signal Connections Figure 4-10 shows how to make analog output connections and the external reference input connection to your AT E Series board. EXTREF DAC0OUT External Reference Signal (Optional) + Channel 0 + V ref - VOUT 0 Load - AO GND VOUT 1 Load DAC1OUT + Channel 1 Analog Output Channels AT E Series Board Figure 4-10. Analog Output Connections The external reference signal can be either a DC or an AC signal.
Chapter 4 Signal Connections Warning: Exceeding the maximum input voltage ratings, which are listed in Tables 4-1 through 4-4, can damage the AT E Series board and the PC. National Instruments is NOT liable for any damages resulting from such signal connections. Figure 4-11 shows signal connections for three typical digital I/O applications. +5 V LED DIO<4..7> TTL Signal DIO<0..3> +5 V Switch DGND I/O Connector AT E Series Board Figure 4-11. Digital I/O Connections Figure 4-11 shows DIO<0..
Chapter 4 Signal Connections Power Connections Two pins on the I/0 connector supply +5 V from the PC power supply via a self-resetting fuse. The fuse will reset automatically within a few seconds after the overcurrent condition is removed. These pins are referenced to DGND and can be used to power external digital circuitry. • Power rating +4.65 VDC to +5.
Chapter 4 Signal Connections external TRIG1 source and an external CONVERT* source to two of the AT E Series board PFI pins. PFI0/TRIG1 PFI2/CONVERT* TRIG1 Source CONVERT* Source DGND I/O Connector AT E Series Board Figure 4-12. Timing I/O Connections Programmable Function Input Connections There are a total of 13 internal timing signals that you can externally control from the PFI pins. The source for each of these signals is software selectable from any of the PFIs when you want external control.
Chapter 4 Signal Connections detection requirements for each timing signal are listed within the section that discusses that individual signal. In edge-detection mode, the minimum pulse width required is 10 ns. This applies for both rising-edge and falling-edge polarity settings. There is no maximum pulse-width requirement in edge-detect mode.
Chapter 4 Signal Connections TRIG1 TRIG2 Don't Care STARTSCAN CONVERT* Scan Counter 3 2 1 0 2 2 2 1 0 Figure 4-14. Typical Pretriggered Acquisition SCANCLK Signal SCANCLK is an output-only signal that generates a pulse with the leading edge occurring approximately 50 to 100 ns after an A/D conversion begins.
Chapter 4 Signal Connections EXTSTROBE* signal. A 10 µs and a 1.2 µs clock are available for generating a sequence of eight pulses in the hardware-strobe mode. Figure 4-16 shows the timing for the hardware-strobe mode EXTSTROBE* signal. V OH V OL tw tw tw = 600 ns or 5 µs Figure 4-16. EXTSTROBE* Signal Timing TRIG1 Signal Any PFI pin can externally input the TRIG1 signal, which is available as an output on the PFI0/TRIG1 pin.
Chapter 4 Signal Connections tw Rising-edge polarity Falling-edge polarity t w = 10 ns minimum Figure 4-17. TRIG1 Input Signal Timing tw t w = 50-100 ns Figure 4-18. TRIG1 Output Signal Timing The board also uses the TRIG1 signal to initiate pretriggered data acquisition operations. In most pretriggered applications, the TRIG1 signal is generated by a software trigger.
Chapter 4 Signal Connections TRIG2 Signal Any PFI pin can externally input the TRIG2 signal, which is available as an output on the PFI1/TRIG2 pin. Refer to Figure 4-13 for the relationship of TRIG2 to the data acquisition sequence. As an input, the TRIG2 signal is configured in the edge-detection mode. You can select any PFI pin as the source for TRIG2 and configure the polarity selection for either rising or falling edge.
Chapter 4 Signal Connections tw t w = 50-100 ns Figure 4-20. TRIG2 Output Signal Timing STARTSCAN Signal Any PFI pin can externally input the STARTSCAN signal, which is available as an output on the PFI7/STARTSCAN pin. Refer to Figures 4-13 and 4-14 for the relationship of STARTSCAN to the data acquisition sequence. As an input, the STARTSCAN signal is configured in the edge-detection mode.
Chapter 4 Signal Connections Figures 4-21 and 4-22 show the input and output timing requirements for the STARTSCAN signal tw Rising-edge polarity Falling-edge polarity t w = 10 ns minimum Figure 4-21. STARTSCAN Input Signal Timing tw STARTSCAN t w = 50-100 ns a. Start of Scan Start Pulse CONVERT* STARTSCAN toff toff = 10 ns minimum b. Scan in Progress, Two Conversions per Scan Figure 4-22.
Chapter 4 Signal Connections The CONVERT* pulses are masked off until the board generates the STARTSCAN signal. If you are using internally generated conversions, the first CONVERT* will appear when the onboard sample interval counter reaches zero. If you select an external CONVERT*, the first external pulse after STARTSCAN will generate a conversion. The STARTSCAN pulses should be separated by at least one scan period.
Chapter 4 Signal Connections Figures 4-23 and 4-24 show the input and output timing requirements for the CONVERT* signal. tw Rising-edge polarity Falling-edge polarity t w = 10 ns minimum Figure 4-23. CONVERT* Input Signal Timing tw t w = 50-100 ns Figure 4-24. CONVERT* Output Signal Timing The ADC switches to hold mode within 60 ns of the selected edge. This hold-mode delay time is a function of temperature and does not vary from one conversion to the next.
Chapter 4 Signal Connections AIGATE Signal Any PFI pin can externally input the AIGATE signal, which is not available as an output on the I/O connector. The AIGATE signal can mask off scans in a data acquisition sequence. You can configure the PFI pin you select as the source for the AIGATE signal in either the level-detection or edge-detection mode. You can configure the polarity selection for the PFI pin for either active high or active low.
Chapter 4 Signal Connections Either the 20 MHz or 100 kHz internal timebase generates the SISOURCE signal unless you select some external source. Figure 4-25 shows the timing requirements for the SISOURCE signal. tp tw tw t p = 50 ns minimum t w = 23 ns minimum Figure 4-25. SISOURCE Signal Timing Waveform Generation Timing Connections The analog group defined for your AT E Series board is controlled by WFTRIG, UPDATE*, and UISOURCE.
Chapter 4 Signal Connections Figures 4-26 and 4-27 show the input and output timing requirements for the WFTRIG signal. tw Rising-edge polarity Falling-edge polarity t w = 10 ns minimum Figure 4-26. WFTRIG Input Signal Timing tw t w = 50-100 ns Figure 4-27. WFTRIG Output Signal Timing UPDATE* Signal Any PFI pin can externally input the UPDATE* signal, which is available as an output on the PFI5/UPDATE* pin. As an input, the UPDATE* signal is configured in the edge-detection mode.
Chapter 4 Signal Connections Figures 4-28 and 4-29 show the input and output timing requirements for the UPDATE* signal. tw Rising-edge polarity Falling-edge polarity t w = 10 ns minimum Figure 4-28. UPDATE* Input Signal Timing tw t w = 300-350 ns Figure 4-29. UPDATE* Output Signal Timing The DACs are updated within 100 ns of the leading edge. Separate the UPDATE* pulses with enough time that new data can be written to the DAC latches.
Chapter 4 Signal Connections UISOURCE Signal Any PFI pin can externally input the UISOURCE signal, which is not available as an output on the I/O connector. The UI counter uses the UISOURCE signal as a clock to time the generation of the UPDATE* signal. You must configure the PFI pin you select as the source for the UISOURCE signal in the level-detection mode. You can configure the polarity selection for the PFI pin for either active high or active low.
Chapter 4 Signal Connections General-Purpose Timing Signal Connections The general-purpose timing signals are GPCTR0_SOURCE, GPCTR0_GATE, GPCTR0_OUT, GPCTR0_UP_DOWN, GPCTR1_SOURCE, GPCTR1_GATE, GPCTR1_OUT, GPCTR1_UP_DOWN, and FREQ_OUT. GPCTR0_SOURCE Signal Any PFI pin can externally input the GPCTR0_SOURCE signal, which is available as an output on the PFI8/GPCTR0_SOURCE pin. As an input, the GPCTR0_SOURCE signal is configured in the edge-detection mode.
Chapter 4 Signal Connections GPCTR0_GATE Signal Any PFI pin can externally input the GPCTR0_GATE signal, which is available as an output on the PFI9/GPCTR0_GATE pin. As an input, the GPCTR0_GATE signal is configured in the edge-detection mode. You can select any PFI pin as the source for GPCTR0_GATE and configure the polarity selection for either rising or falling edge.
Chapter 4 Signal Connections TC GPCTR0_SOURCE GPCTR0_OUT (Pulse on TC) GPCTR0_OUT (Toggle output on TC) Figure 4-33. GPCTR0_OUT Signal Timing GPCTR0_UP_DOWN Signal This signal can be externally input on the DIO6 pin and is not available as an output on the I/O connector. The general-purpose counter 0 will count down when this pin is at a logic low and count up when it is at a logic high.
Chapter 4 Signal Connections Figure 4-34 shows the timing requirements for the GPCTR1_SOURCE signal. tp tw tw t p = 50 ns minimum t w = 23 ns minimum Figure 4-34. GPCTR1_SOURCE Signal Timing The maximum allowed frequency is 20 MHz, with a minimum pulse width of 23 ns high or low. There is no minimum frequency limitation. The 20 MHz or 100 kHz timebase normally generates the GPCTR1_SOURCE unless you select some external source.
Chapter 4 Signal Connections Figure 4-35 shows the timing requirements for the GPCTR1_GATE signal. tw Rising-edge polarity Falling-edge polarity t w = 10 ns minimum Figure 4-35. GPCTR1_GATE Signal Timing in Edge-Detection Mode GPCTR1_OUT Signal This signal is available only as an output on the GPCTR1_OUT pin. The GPCTR1_OUT signal monitors the TC board general-purpose counter 1. You have two software-selectable output options—pulse on TC and toggle output polarity on TC.
Chapter 4 Signal Connections GPCTR1_UP_DOWN Signal This signal can be externally input on the DIO7 pin and is not available as an output on the I/O connector. General-purpose counter 1 counts down when this pin is at a logic low and counts up at a logic high. This input can be disabled so that software can control the up-down functionality and leave the DIO7 pin free for general use.
Chapter 4 Signal Connections The GATE and OUT signal transitions shown in Figure 4-37 are referenced to the rising edge of the SOURCE signal. This timing diagram assumes that the counters are programmed to count rising edges. The same timing diagram, but with the source signal inverted and referenced to the falling edge of the source signal, would apply when the counter is programmed to count falling edges.
Chapter 4 Signal Connections Timing Specifications for Digital I/O Ports A, B, and C ♦ AT-MIO-16DE-10 only In addition to its function as a digital I/O port, digital port C, PC<0..7>, can also be used for handshaking when performing data transfers with ports A and B. The signals assigned to port C depend on the mode in which it is programmed. In mode 0, port C is considered two 4-bit I/O ports. In modes 1 and 2, port C is used for status and handshaking signals with two or three additional I/O bits.
Chapter 4 Signal Connections This section lists the timing specifications for handshaking with the AT-MIO-16DE-10 port C circuitry. The handshaking lines STB* and IBF synchronize input transfers. The handshaking lines OBF* and ACK* synchronize output transfers. The following signals are used in the timing diagrams that follow. Name Type Description STB* input Strobe Input—A low signal on this handshaking line loads data into the input latch.
Chapter 4 Signal Connections Mode 1 Input Timing The following are the timing specifications for an input transfer in Mode 1: T1 T2 T4 STB * T7 IBF T6 INTR RD * T3 T5 DATA Figure 4-38. Mode 1 Input Timing Description Name STB* Pulse Width T1 T2 STB* = 0 to IBF = 1 T3 Data before STB* = 1 T4 STB* = 1 to INTR = 1 T5 Data after STB* = 1 T6 RD* = 0 to INTR = 0 T7 RD* = 1 to IBF = 0 All timing values are in nanoseconds.
Chapter 4 Signal Connections Mode 1 Output Timing The following are the timing specifications for an output transfer in Mode 1: T3 WR* T4 OBF* T1 INTR T6 T5 ACK* DATA T2 Figure 4-39. Mode 1 Output Timing Name Description T1 WR* = 0 to INTR = 0 T2 WR* = 1 to Output T3 WR* = 1 to OBF* = 0 T4 ACK* = 0 to OBF* = 1 T5 ACK* Pulse Width T6 ACK* = 1 to INTR = 1 All timing values are in nanoseconds.
Chapter 4 Signal Connections Mode 2 Bidirectional Timing The following are the timing specifications for bidirectional transfers in Mode 2: T1 WR * T6 OBF * INTR T7 ACK * T3 STB * T10 T4 IBF RD * T2 T5 T8 T9 DATA Figure 4-40.
Chapter 4 Signal Connections Field Wiring Considerations Environmental noise can seriously affect the accuracy of measurements made with your AT E Series board if you do not take proper care when running signal wires between signal sources and the board. The following recommendations apply mainly to analog input signal routing to the board, although they also apply to signal routing in general.
Chapter 5 Calibration This chapter discusses the calibration procedures for your AT E Series board. If you are using the NI-DAQ device driver, that software includes calibration functions for performing all of the steps in the calibration process. Calibration refers to the process of minimizing measurement and output voltage errors by making small circuit adjustments. On the AT E Series boards, these adjustments take the form of writing values to onboard calibration DACs (CalDACs).
Chapter 5 Calibration This method of calibration is not very accurate because it does not take into account the fact that the board measurement and output voltage errors can vary with time and temperature. It is better to self-calibrate when the board is installed in the environment in which it will be used. Self-Calibration Your AT E Series board can measure and correct for almost all of its calibration-related errors without any external signal connections.
Chapter 5 Calibration To externally calibrate your board, be sure to use a very accurate external reference. The reference should be several times more accurate than the board itself. For example, to calibrate a 12-bit board, the external reference should be at least ±0.005% (±50 ppm) accurate. To calibrate a 16-bit board, the external reference should be at least ±0.001% (±10 ppm) accurate.
Appendix A Specifications This appendix lists the specifications of each board in the AT E Series. These specifications are typical at 25° C unless otherwise noted. AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 Analog Input Input Characteristics Number of channels AT-MIO-16E-1, AT-MIO-16E-2 ........................... 16 single-ended or 8 differential (software selectable) AT-MIO-64E-3 ........................... 64 single-ended or 32 differential (software selectable) Type of ADC.........................
Appendix A Specifications for AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 Input signal ranges................. Board Gain (Software Selectable) Board Range (Software Selectable) Bipolar Unipolar 0.5 ±10 V — 1 ±5 V 0 to 10 V 2 ±2.5 V 0 to 5 V 5 ±1 V 0 to 2 V 10 ±500 mV 0 to 1 V 20 ±250 mV 0 to 500 mV 50 ±100 mV 0 to 200 mV 100 ±50 mV 0 to 100 mV Input coupling....................................DC Max working voltage (signal + common mode).................
Appendix A Specifications for AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 Transfer Characteristics Relative accuracy ............................. ±0.5 LSB typ dithered, ±1.5 LSB max undithered DNL .................................................. ±0.5 LSB typ, ±1.0 LSB max No missing codes .............................. 12 bits, guaranteed Offset error Pregain error after calibration ..... ±12 µV max Pregain error before calibration... ±2.5 mV max Postgain error after calibration.... ±0.
Appendix A Specifications for AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 Dynamic Characteristics Bandwidth ......................... Small signal (-3dB) Large signal (1% THD) AT-MIO-16E-1 1.6 MHz 1 MHz AT-MIO-16E-2, AT-MIO-64E-3 1 MHz 300 kHz Settling time for full-scale step .................... ±0.012% (±0.5 LSB) ±0.024% (±1 LSB) ±0.098% (±4 LSB) 0.5 2 µs typ 3 µs max 1.5 µs typ 2 µs max 1.5 µs typ 2 µs max 1 1.5 µs typ 2 µs max 1.3 µs typ 1.5 µs max 1.1 µs typ 1.
Appendix A Specifications for AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 System noise (LSBrms) (not including quantization) ....... AT-MIO-16E-1 AT-MIO-16E-2, AT-MIO-64E-3 Gain Noise, dither off Noise, dither on 0.5 to 10 0.25 0.5 20 0.4 0.6 50 0.5 0.7 100 0.8 0.9 0.5 to 20 0.15 0.5 50 0.3 0.6 100 0.5 0.7 Crosstalk ........................................... -80 dB, DC to 100 kHz Stability Recommended warm-up time ............ 15 min Offset temperature coefficient Pregain......
Appendix A Specifications for AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 Analog Output Output Characteristics Number of channels ...........................2 voltage Resolution..........................................12 bits, 1 in 4,096 Max update rate FIFO mode waveform generation Internally timed ................... 1 MS/s per channel Externally timed .................. 950 kS/s per channel Non-FIFO mode waveform generation 1 channel .............................
Appendix A Specifications for AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 Gain error (relative to external reference)........... +0% to +0.5% of output max, not adjustable Voltage Output Ranges .............................................. ±10 V, 0 to 10 V, ±EXTREF, 0 to EXTREF (software selectable) Output coupling................................. DC Output impedance ............................. 0.1 Ω max Current drive ..................................... ±5 mA max Protection .........................
Appendix A Specifications for AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 Onboard calibration reference Level .......................................... 5.000 V (±2.5 mV) (actual value stored in EEPROM) Temperature coefficient.............. ±5 ppm/°C max Long-term stability ..................... ±15 ppm/ 1, 000 h Digital I/O Number of channels ...........................8 input/output Compatibility .....................................TTL/CMOS Digital logic levels............
Appendix A Specifications for AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 Base clocks available Counter/timers ............................ 20 MHz, 100 kHz Frequency scalers........................ 10 MHz, 100 kHz Base clock accuracy .......................... ±0.01% Max source frequency ....................... 20 MHz Min source pulse duration ................. 10 ns in edge-detect mode Min gate pulse duration ..................... 10 ns in edge-detect mode Data transfers .................................
Appendix A Specifications for AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 Digital Trigger Compatibility .....................................TTL Response............................................Rising or falling edge Pulse width ........................................10 ns min RTSI Trigger lines.......................................7 Bus Interface Type...................................................Slave Power Requirement +5 VDC (±5%)...................................1.
AT-MIO-16E-10 and AT-MIO-16DE-10 Analog Input Input Characteristics Number of channels ...........................16 single-ended or 8 differential, software selectable Type of ADC .....................................Successive approximation Resolution ..........................................12 bits, 1 in 4,096 Max sampling rate..............................100 kS/s guaranteed Input signal ranges ................. Board Gain (Software Selectable) Board Range (Software Selectable) ±5 V 0-10 V 0.
Appendix A Specifications for AT-MIO-16E-10 and AT-MIO-16DE-10 Data transfers.....................................DMA, interrupts, programmed I/O DMA modes.......................................Single transfer, demand transfer Configuration memory size ................512 words Transfer Characteristics Relative accuracy ..............................±0.2 LSB typ dithered, ±1.0 LSB max undithered DNL...................................................±0.2 LSB typ, ±0.5 LSB max No missing codes ............
Appendix A Specifications for AT-MIO-16E-10 and AT-MIO-16DE-10 System noise (not including quantization) .............. Gain Noise 0.5 to 10 0.07 LSB rms 20 0.12 LSB rms 50 0.25 LSB rms 100 0.5 LSB rms dither on, any gain 0.5 LSB rms Crosstalk ........................................... -80 dB, DC to 100 kHz Stability Recommended warm-up time ............ 15 min Offset temperature coefficient Pregain........................................ ±15 µV/°C Postgain .................................
Appendix A Specifications for AT-MIO-16E-10 and AT-MIO-16DE-10 Data transfers.....................................DMA, interrupts, programmed I/O DMA modes.......................................Single transfer Transfer Characteristics Relative accuracy (INL) After calibration.................................±0.3 LSB typ, ±0.5 LSB max Before calibration ..............................±4 LSB max DNL After calibration ......................... ±0.3 LSB typ, ±1.0 LSB max Before calibration ...................
Appendix A Specifications for AT-MIO-16E-10 and AT-MIO-16DE-10 External reference input Range.......................................... ±11 V Overvoltage protection................ ±35 V powered on, ±25 V powered off Input impedance.......................... 10 kΩ Bandwidth (-3 dB) ...................... 300 kHz Dynamic Characteristics Settling time for full-scale step.......... 10 µs to ±0.5 LSB accuracy Slew rate ........................................... 15 V/µs Noise ................................
Appendix A Specifications for AT-MIO-16E-10 and AT-MIO-16DE-10 Digital logic levels............ Level Min Max Input low voltage 0V 0.8 V Input high voltage 2V 5V Input low current (Vin = 0 V) — -320 µA Input high current (Vin = 5 V) — 10 µA — 0.4 V (IOH = 13 mA) 4.35 V — Level Min Max Input low voltage 0V 0.8 V Input high voltage 2V 5V Input low current (Vin = 0 V) — -60 µA Input high current (Vin = 5 V) — 10 µA — 0.4 V 3.
Appendix A Specifications for AT-MIO-16E-10 and AT-MIO-16DE-10 Power-on state................................... Input (High-Z) Data transfers AT-MIO-16E-10 ......................... Programmed I/O AT-MIO-16DE-10 ...................... Interrupts, programmed I/O Timing I/O Number of channels .......................... 2 up/down counter/timers, 1 frequency scaler Resolution ......................................... Counter/timers ............................ 24 bits Frequency scalers......................
Appendix A Specifications for AT-MIO-16E-10 and AT-MIO-16DE-10 Power Requirement +5 VDC (±5%)...................................0.7 A Power available at I/O connector .......+4.65 VDC to +5.25 VDC at 1 A Physical Dimensions (not including connectors) .................33.8 by 9.9 cm (13.3 by 3.9 in.) I/O connector AT-MIO-16E-10......................... 68-pin male SCSI-II type AT-MIO-16DE-10 ...................... 100-pin female 0.050 D-type Environment Operating temperature........................
AT-MIO-16XE-10 and AT-AI-16XE-10 Analog Input Input Characteristics Number of channels ...........................16 single-ended or 8 differential (software-selectable) Type of ADC .....................................Successive approximation Resolution ..........................................16 bits, 1 in 65,536 Maximum sampling rate.....................100 kS/s guaranteed Input signal ranges .................
Appendix A Specifications for AT-MIO-16XE-10 and AT-AI-16XE-10 Configuration memory size ................512 words Transfer Characteristics Relative accuracy ...............................±0.75 LSB typ, ±1 LSB max DNL...................................................±0.5 LSB typ, ±1 LSB max No missing codes ...............................16 bits, guaranteed Offset error Pregain error after calibration ..... ±3 µV max Pregain error before calibration .. ±2.2 mV max Postgain error after calibration ...
Appendix A Specifications for AT-MIO-16XE-10 and AT-AI-16XE-10 Dynamic Characteristics Bandwidth All gains ..................................... 255 kHz Settling time for full-scale step, all gains and ranges To ±0.5 LSB ............................... 40 µs typ To ±1 LSB .................................. 20 µs typ To ±4 LSB .................................. 10 µs typ System noise (including quantization noise) Gain = 1, 2, 5, 10 ........................ 0.6 LSB rms bipolar, 0.
Appendix A Specifications for AT-MIO-16XE-10 and AT-AI-16XE-10 Analog Output (AT-MIO-16XE-10 only) Output Characteristics Number of channels ...........................2 voltage Resolution..........................................16 bits, 1 in 65,536 Max update rate .................................100 kS/s Type of DAC ....................................Double-buffered FIFO buffer size.................................2,048 samples Data transfers.....................................
Appendix A Specifications for AT-MIO-16XE-10 and AT-AI-16XE-10 Dynamic Characteristics Settling time for full-scale step.......... 10 µs to ±1 LSB accuracy Slew rate ........................................... 5 V/µs Noise ................................................. 60 µVrms, DC to 1 MHz Stability Offset temperature coefficient ........... ±50 µV/°C Gain temperature coefficient ............. ±7.5 ppm/°C Onboard calibration reference Level........................................... 5.000 V (±0.
Appendix A Specifications for AT-MIO-16XE-10 and AT-AI-16XE-10 Timing I/O Number of channels ...........................2 up/down counter/timers, 1 frequency scaler Resolution Counter/timers ............................ 24 bits Frequency scaler......................... 4 bits Compatibility .....................................TTL/CMOS Base clocks available Counter/timers ............................ 20 MHz, 100 kHz Frequency scaler......................... 10 MHz, 100 kHz Base clock accuracy .............
Appendix A Specifications for AT-MIO-16XE-10 and AT-AI-16XE-10 External input (PFI0/TRIG1) Impedance................................... 10 kΩ Coupling ..................................... DC Protection.................................... -0.5 to Vcc +0.5 V when configured as a digital signal ±35 V when configured as an analog trigger signal or disabled ±35 V powered off Accuracy ........................................... ±1% of full-scale range Digital Trigger Compatibility ............................
AT-MIO-16XE-50 Analog Input Input Characteristics Number of channels ...........................16 single-ended or 8 differential (software-selectable) Type of ADC .....................................Successive approximation Resolution ..........................................16 bits, 1 in 65,536 Maximum sampling rate.....................20 kS/s guaranteed Input signal ranges .................
Appendix A Specifications for AT-MIO-16XE-50 Transfer Characteristics Relative accuracy .............................. ±0.5 LSB typ, ±1 LSB max DNL .................................................. ±0.5 LSB typ, ±1 LSB max No missing codes .............................. 16 bits, guaranteed Offset error Pregain error after calibration ..... ±3 µV max Pregain error before calibration... ±1 mV max Postgain error after calibration.... ±76 µV max Postgain error before calibration .
Appendix A Specifications for AT-MIO-16XE-50 Settling time for full-scale step ..........50 µs max to ± 1 LSB, all gains and ranges System noise (including quantization noise) Gain = 1, 2, 10............................ 0.5 LSB rms Gain = 100.................................. 0.8 LSB rms bipolar, 1.4 LSB rms unipolar Crosstalk ............................................-85 dB max, DC to 20 kHz Stability Recommended warm-up time.............15 min Offset temperature coefficient Pregain ..................
Appendix A Specifications for AT-MIO-16XE-50 Offset error After calibration.......................... ±0.5 mV max Before calibration ....................... ±85 mV max Gain error (relative to calibration reference) After calibration.......................... ±0.01% of output max Before calibration ....................... ±1% of output max Voltage Output Range ................................................ ±10 V Output coupling................................. DC Output impedance .......................
Appendix A Specifications for AT-MIO-16XE-50 Digital I/O Number of channels ...........................8 input/output Compatibility .....................................TTL/CMOS Digital logic levels............ Level Min Max Input low voltage 0V 0.8 V Input high voltage 2V 5V Input low current — -320 µA Input high current — 10 µA — 0.4 V 4.35 V — Output low voltage (IOL = 24 mA) Output high voltage (IOH = 13 mA) Power-on state ...................................
Appendix A Specifications for AT-MIO-16XE-50 Min gate pulse duration .................... 10 ns, edge-detect mode Data transfers .................................... DMA, interrupts, programmed I/O DMA modes ...................................... Single transfer Triggers Digital Trigger Compatibility .................................... TTL Response ........................................... Rising or falling edge Pulse width........................................ 10 ns min RTSI Trigger Lines.........
Appendix Optional Cable Connector Descriptions B This appendix describes the connectors on the optional cables for the AT E Series boards. Figure B-1 shows the pin assignments for the 68-pin MIO connector. This connector is available when you use the SH6868 or R6868 cable assemblies with the AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-16E-10, AT-MIO-16XE-10, AT-AI-16XE-10, or AT-MIO-16XE-50.
Appendix B Optional Cable Connector Descriptions ACH8 ACH1 AIGND ACH10 ACH3 AIGND ACH4 AIGND ACH13 ACH6 AIGND ACH15 1 DAC0OUT 1 DAC1OUT 2 EXTREF DIO4 DGND DIO1 DIO6 DGND +5 V DGND DGND PFI0/TRIG1 PFI1/TRIG2 DGND +5 V DGND PFI5/UPDATE* PFI6/WFTRIG DGND PFI9/GPCTR0_GATE GPCTR0_OUT FREQ_OUT 1 34 33 32 31 30 29 28 27 26 25 68 67 66 65 64 63 62 61 60 59 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 ACH0 AIGND ACH9 AC
Appendix B Optional Cable Connector Descriptions Figure B-2 shows the pin assignments for the 68-pin DIO connector. This is the other 68-pin connector available when you use the SH1006868 cable assembly with the AT-MIO-16DE-10.
Appendix B Optional Cable Connector Descriptions Figure B-3 shows the pin assignments for the 68-pin extended analog input connector. This is the other 68-pin connector available when you use the SH1006868 cable assembly with the AT-MIO-64E-3.
Appendix B Optional Cable Connector Descriptions Figure B-4 shows the pin assignments for the 50-pin MIO connector. This connector is available when you use the SH6850 or R6850 cable assemblies with the AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-16E-10, AT-MIO-16XE-10, AT-AI-16XE-10, or AT-MIO-16XE-50. It is also one of the two 50-pin connectors available when you use the R1005050 cable assembly with the AT-MIO-16DE-10 or AT-MIO-64E-3.
Appendix B Optional Cable Connector Descriptions Figure B-5 shows the pin assignments for the 50-pin DIO connector. This is the other 50-pin connector available when you use the R1005050 cable assembly with the AT-MIO-16DE-10.
Appendix B Optional Cable Connector Descriptions Figure B-6 shows the pin assignments for the 50-pin extended analog input connector. This is the other 50-pin connector available when you use the R1005050 cable assembly with the AT-MIO-64E-3.
Appendix C Common Questions This appendix contains a list of commonly asked questions and their answers relating to usage and special features of your AT E Series board. General Information 1. What are the AT E Series boards? The AT E Series boards are switchless and jumperless, enhanced MIO boards that use the DAQ-STC for timing. 2.
Appendix C Common Questions that some AT E Series boards have settling times that vary with gain and accuracy. See Appendix A for exact specifications. 4. What type of 5 V protection do the AT E Series boards have? The AT E Series boards have 5 V lines equipped with a self-resetting 1 A fuse. Installation and Configuration 5.
Appendix C Common Questions 10. What special calls must be made in DOS or LabWindows to use AT E Series boards? To link in the AT E Series function calls, you must call USE_E_Series or one of its subsets. 11. What is the best way to test my board without having to program the board? If you are using Windows, the WDAQCONF utility has a Test menu with some excellent tools for doing simple functional tests of the board, such as analog input and output, digital I/O, and counter/timer tests.
Appendix C Common Questions 15. Can I sample across a number of channels on an AT E Series board while each channel is being sampled at a different rate? NI-DAQ for PC compatibles version 4.5.1 or later features a new function called SCAN_Sequence_Setup, which allows for multirate scanning of your analog input channels. Refer to the NI-DAQ Function Reference Manual for PC Compatibles for more details. 16.
Appendix C Common Questions b. Set up data acquisition timing so that the timing signal for A/D conversion comes from PFI5, as follows: • If you are using NI-DAQ, call Select_Signal(deviceNumber, ND_IN_CONVERT, ND_PFI_5, ND_HIGH_TO_LOW). • If you are using LabVIEW, invoke AI Clock Config VI with clock source code set to PFI pin, high to low, and clock source string set to 5. c. Initiate analog input data acquisition, which will start only when the analog output waveform generation starts.
Appendix C Common Questions 20. What is the difference in timebases between the Am9513 counter/timer and the DAQ-STC? The DAQ-STC-based MIO boards have a 20 MHz timebase. The Am9513-based MIO boards have a 1 MHz or 5 MHz timebase. 21. The counter/timer examples supplied with NI-DAQ are not compatible with an AT E Series board.
Appendix C Common Questions errors. NI-DAQ takes a snapshot of transfers and counts how many points have been transferred. If all the points have been transferred and the first instance of this error occurs, NI-DAQ returns a gpctrDataTransferWarning indicating that the error could be bogus. If all the points have not been transferred, NI-DAQ returns the genuine error. The error continues to be returned until the acquisition completes.
Appendix C Common Questions a 50 kΩ pull-up resistor. This pull-up resistor will set the DIO(0) pin to a logic high when the output is in a high impedance state.
Click here to comment on this document via the National Instruments website at http://www.natinst.com/documentation/daq/ Customer Communication Appendix D For your convenience, this appendix contains forms to help you gather the information necessary to help us solve your technical problems and a form you can use to comment on the product documentation.
Click here to comment on this document via the National Instruments website at http://www.natinst.com/documentation/daq/ FaxBack Support FaxBack is a 24-hour information retrieval system containing a library of documents on a wide range of technical information. You can access FaxBack from a touch-tone telephone at (512) 418-1111. E-Mail Support (currently U.S.
Technical Support Form Click here to comment on this document via the National Instruments website at http://www.natinst.com/documentation/daq/ Photocopy this form and update it each time you make changes to your software or hardware, and use the completed copy of this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.
AT E Series Hardware and Software Click here to comment on this document Configuration Form via the National Instruments website at http://www.natinst.com/documentation/daq/ Record the settings and revisions of your hardware and software on the line to the right of each item. Complete a new copy of this form each time you revise your software or hardware configuration, and use this form as a reference for your current configuration.
Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs. Title: AT-MIO/AI E Series User Manual Edition Date: May 1996 Part Number: 320517E-01 Click here to comment on this document via the National Instruments website at http://www.natinst.com/documentation/daq/ Please comment on the completeness, clarity, and organization of the manual.
Glossary Prefix Meaning Value p- pico- 10-12 n- nano- 10-9 µ- micro- 10-6 m- milli- 10-3 k- kilo- 103 M- mega- 106 G- giga- 109 Symbols % percent ± plus or minus ˚ degrees / per + positive of, or plus – negative of, or minus Ω ohms square root of +5V National Instruments Corporation +5 VDC source signal G-1 AT-MIO/AI E Series User Manual
Glossary A A amperes AC alternating current ACH analog input channel signal A/D analog-to-digital ADC A/D converter AIGATE analog input gate signal AIGND analog input ground signal AISENSE analog input sense signal AISENSE2 analog input sense 2 signal ANSI American National Standards Institute AOGND analog output ground signal ASIC application-specific integrated circuit B BIOS basic input/output system or built-in operating system C C Celsius CalDAC calibration DAC CMOS comp
Glossary D D/A digital-to-analog DAC D/A converter DAC0OUT analog channel 0 output signal DAC1OUT analog channel 1 output signal DAQ data acquisition DC direct current DGND digital ground signal DIFF differential mode DIO digital input/output DMA direct memory access DNL differential nonlinearity E EEPROM electrically erasable programmable read-only memory EISA Extended Industry Standard Architecture EXTREF external reference signal EXTSTROBE external strobe signal F FIFO fir
Glossary G GPCTR0_GATE general purpose counter 0 gate signal GPCTR1_GATE general purpose counter 1 gate signal GPCTR0_OUT general purpose counter 0 output signal GPCTR1_OUT general purpose counter 1 output signal GPCTR0_SOURCE general purpose counter 0 clock source signal GPCTR1_SOURCE general purpose counter 1 clock source signal H h hour hex hexadecimal Hz hertz I I/O input/output IOH current, output high IOL current, output low ISA Industry Standard Architecture L LASTCHAN las
Glossary MSB most significant bit N NRSE nonreferenced single-ended mode O OUT output P PC personal computer PFI Programmable Function Input PGIA Programmable Gain Instrumentation Amplifier ppm parts per million R rms root mean square RSE referenced single-ended mode RTD resistive temperature device RTSI Real-Time System Integration S s seconds S samples SCANCLK scan clock signal SCXI Signal Conditioning eXtensions for Instrumentation SE single-ended inputs SISOURCE SI coun
Glossary STARTSCAN start scan signal T TC terminal count THD total harmonic distortion TRIG trigger signal TTL transistor-transistor logic U UI update interval UISOURCE update interval counter clock signal UPDATE update signal V V volts VDC volts direct current VIH volts, input high VIL volts, input low Vin volts in VOH volts, output high VOL volts, output low Vref reference voltage W WFTRIG AT-MIO/AI E Series User Manual waveform generation trigger signal G-6 National
Index Symbols differential connections for floating signal sources, 4-22 to 4-23 AISENSE signal analog input connections, 4-16 AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 (table), 4-8 AT-MIO-16E-10 and AT-MIO-16DE-10 (table), 4-10 AT-MIO-16XE-10 and AT-AI-16XE-10 (table), 4-12 AT-MIO-16XE-50 (table), 4-14 description (table), 4-5 AISENSE2 signal analog input connections, 4-16 AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 (table), 4-8 description (table), 4-5 amplifier characteristics AT-MIO-16E-1, AT-MIO-16
Index AT-MIO-16E-10 and AT-MIO-16DE-10 dynamic characteristics, A-15 output characteristics, A-13 to A-14 stability, A-15 transfer characteristics, A-14 voltage output, A-14 to A-15 AT-MIO-16XE-10 dynamic characteristics, A-23 output characteristics, A-22 stability, A-23 transfer characteristics, A-22 voltage output, A-22 AT-MIO-16XE-50 dynamic characteristics, A-29 output characteristics, A-28 stability, A-29 transfer characteristics, A-28 to A-29 voltage output, A-29 analog trigger, 3-15 to 3-18 block di
Index calibration, 5-1 to 5-3 adjusting for gain error, 5-3 external calibration, 5-2 to 5-3 loading calibration constants, 5-1 to 5-2 self-calibration, 5-2 charge injection, 3-13 clocks, board and RTSI, 3-21 commonly asked questions. See questions about AT E series boards. common-mode signal rejection, 4-26 configuration. See also input configurations.
Index grounded signal sources (NRSE), 4-25 when to use, 4-20 digital I/O common questions about, C-5 to C-8 operation, 3-19 signal connections, 4-28 to 4-29 specifications AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3, A-8 AT-MIO-16E-10 and AT-MIO-16DE-10, A-15 to A-17 AT-MIO-16XE-10 and AT-AI-16XE-10, A-23 AT-MIO-16XE-50, A-30 digital ports A, B, and C timing specifications, 4-53 to 4-57 mode 1 input timing, 4-55 mode 1 output timing, 4-56 mode 2 bidirectional timing, 4-57 Port C signal assignments (table),
Index equipment, optional, 1-5 EXTREF signal analog output reference connections, 4-27 to 4-28 analog output reference selection, 3-14 AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 (table), 4-8 AT-MIO-16E-10 and AT-MIO-16DE-10 (table), 4-10 description (table), 4-5 EXTSTROBE* signal AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 (table), 4-9 AT-MIO-16E-10 and AT-MIO-16DE-10 (table), 4-10 AT-MIO-16XE-10 and AT-AI-16XE-10 (table), 4-12 AT-MIO-16XE-50 (table), 4-14 description (table), 4-6 timing connections, 4-30
Index waveform generation timing connections, 4-50 GPCTR1_SOURCE signal, 4-48 to 4-49 GPCTR1_UP_DOWN signal, 4-51 to 4-52 ground-referenced signal sources description, 4-18 differential connections, 4-21 single-ended connections (NRSE configuration), 4-25 frequently asked questions. See questions about AT E series boards.
Index I AT-MIO-16DE-10, 3-7 to 3-8 actual range and measurement precision (table), 3-8 AT-MIO-16XE-10, AT-AI-16XE-10, and AT-MIO-16XE-50, 3-9 to 3-10 AT-MIO-16XE-10, AT-MIO-16XE-50 actual range and measurement precision (table), 3-10 mixing bipolar and unipolar channels (note), 3-9 selection considerations, 3-10 installation. See also configuration.
Index N PFI1/TRIG2 signal AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 (table), 4-9 AT-MIO-16E-10 and AT-MIO-16DE-10 (table), 4-10 AT-MIO-16XE-10 and AT-AI-16XE-10 (table), 4-12 AT-MIO-16XE-50 (table), 4-14 description (table), 4-6 PFI2/CONVERT* signal AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 (table), 4-9 AT-MIO-16E-10 and AT-MIO-16DE-10 (table), 4-10 AT-MIO-16XE-10 and AT-AI-16XE-10 (table), 4-12 AT-MIO-16XE-50 (table), 4-14 description (table), 4-7 PFI3/GPCTR1_SOURCE signal AT-MIO-16E-1, AT-MIO-16E-2
Index PGIA (programmable gain instrumentation amplifier) common-mode signal rejection, 4-26 differential connections floating signal sources, 4-22 to 4-23 ground-referenced signal sources, 4-21 physical specifications AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3, A-10 AT-MIO-16E-10 and AT-MIO-16DE-10, A-18 AT-MIO-16XE-10 and AT-AI-16XE-10, A-25 AT-MIO-16XE-50, A-31 pin assignments. See I/O connectors.
Index Q description (table), 4-6 timing connections, 4-33 settling time, 3-12 to 3-13, C-1 to C-2 signal connections analog input, 4-16 to 4-17 analog output, 4-27 to 4-28 digital I/O, 4-28 to 4-29 field wiring considerations, 4-58 I/O connector, 4-1 to 4-15 exceeding maximum ratings (warning), 4-1, 4-16, 4-29 I/O signal summary (table) AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3, 4-8 to 4-9 AT-MIO-16E-10 and AT-MIO-16DE-10, 4-10 to 4-11 AT-MIO-16XE-10 and AT-AI-16XE-10, 4-12 to 4-13 AT-MIO-16XE-50, 4-14
Index software programming choices LabVIEW and LabWindows/CVI, 1-3 NI-DAQ driver software, 1-3 to 1-5 register-level programming, 1-5 specifications AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 analog input, A-1 to A-5 amplifier characteristics, A-3 dynamic characteristics, A-4 to A-5 input characteristics, A-1 to A-2 stability, A-5 transfer characteristics, A-3 analog output, A-6 to A-8 dynamic characteristics, A-7 output characteristics, A-6 stability, A-7 to A-8 transfer characteristics, A-7 voltage outp
Index dynamic characteristics, A-27 to A-28 input characteristics, A-26 stability, A-28 transfer characteristics, A-27 analog output, A-28 to A-29 dynamic characteristics, A-29 output characteristics, A-28 stability, A-29 transfer characteristics, A-28 to A-29 voltage output, A-29 bus interface, A-31 digital I/O, A-30 environment, A-31 physical, A-31 power requirement, A-31 timing I/O, A-30 to A-31 triggers digital trigger, A-31 RTSI, A-31 output characteristics, A-13 to A-14 stability, A-15 transfer char
Index T UPDATE* signal, 4-43 to 4-44 WFTRIG signal, 4-42 to 4-43 timing I/O specifications AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3, A-8 to A-9 AT-MIO-16E-10 and AT-MIO-16DE-10, A-17 AT-MIO-16XE-10 and AT-AI-16XE-10, A-24 AT-MIO-16XE-50, A-30 to A-31 timing signal routing, 3-19 to 3-22 board and RTSI clocks, 3-21 programmable function inputs, 3-20 to 3-21 RTSI triggers, 3-21 to 3-22 transfer characteristics analog input AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3, A-3 AT-MIO-16E-10 and AT-MIO-16DE-10,
Index AT-MIO-16E-10 and AT-MIO-16DE-10, A-14 to A-15 AT-MIO-16XE-10, A-22 AT-MIO-16XE-50, A-29 AT-MIO-16E-10 and AT-MIO-16DE-10 digital trigger, A-17 RTSI, A-17 AT-MIO-16XE-10 and AT-AI-16XE-10 analog trigger, A-24 to A-25 digital trigger, A-25 RTSI, A-25 AT-MIO-16XE-50 digital trigger, A-31 RTSI, A-31 troubleshooting. See questions about AT E series boards.