User's Manual

Chapter 4 Register-Level Programming

Status Register

The Status Register indicates the status of the current A/D conversion. The bits in this register

determine if a conversion is being performed or if data is available and any errors have been

found.

Address: Base address + 0 8000 (hex)

Type: Read-only

Word Size: 8-bit

Bit Map:

76543 210

X X X GATA1 OVERRUN OVERFLOW GATA0 DAVAIL

Bit Name Description

7–5 X Don’t care bits.

4 GATA1 Gate 1 Input Status Bit—This bit indicates the status of the GATE

1 input on the counter/timer chip (counter group A).

3 OVERRUN Overrun Error Status Bit—This bit indicates if an overrun error has

occurred. If this bit is cleared, no error occurred. This bit is set if

a convert command is issued to the ADC while the last conversion

is still in progress.

2 OVERFLOW Overflow Error Status Bit—This bit indicates if an overflow error

has occurred. If this bit is cleared, no error was encountered. If

this bit is set, the A/D FIFO has overflowed because the DAQ

servicing operation could not keep up with the sampling rate.

1 GATA0 Gate 0 Input Status Bit—This bit indicates the status of the GATE

0 input on the counter/timer chip (counter group A). This bit can

be used as a busy indicator for DAQ operations because

conversions are enabled as long as GATE 0 is high and counter A0

is programmed appropriately.

0 DAVAIL Data Available Bit—This bit indicates whether conversion output

is available. If this bit is set, the ADC is finished with the last

conversion and the result can be read from the FIFO. This bit is

cleared if the FIFO is empty.