User's Manual

Chapter 4 Register-Level Programming

Programming in Freerun Acquisition Mode

Freerun acquisition mode uses only counter A0 as the sample-interval counter. The number of

A/D conversions that have occurred (that is, the sample count) is maintained by software in this

case. With this arrangement, DAQ operations can acquire more than 65,535 samples.

The following programming steps are required for a DAQ operation in freerun acquisition mode:

1. Select analog input channel, gain, and timebase for counter A0.

2. Program counter B0 (if necessary).

3. Program counter A0 to force OUT0 high.

4. Clear the A/D circuitry.

5. Program counter A1 to force OUT1 low.

6. Program the sample-interval counter (counter A0).

7. Service the DAQ operation.

Each of these programming steps is explained below.

1. Select analog input channel, gain, and timebase for counter A0.

The analog input channel and gain are selected by writing to the A/D Configuration Register.

The SCANEN bit must be cleared for DAQ operations on a single channel. See the A/D

Configuration Register bit description earlier in this chapter for gain and analog input channel bit

patterns. If counter B0 is being used as a timebase for counter A0, then the TBSEL bit in the

ADC Configuration Register should be set at this time.

The A/D Configuration Register needs to be written to only when the analog input channel, gain

setting, or other function needs to be changed.

2. Program counter B0 (if necessary).

The following sequence should be used to program counter B0 if it is being used. If counter B0

is not being used, skip to step 3. All writes are 8-bit write operations. All values given are

hexadecimal.

a. Write 36 to the Counter B Mode Register (select mode 3).

b. Write the least significant byte of the timebase count to the Counter B Data Register.