DAQ 6023E/6024E/6025E User Manual Multifunction I/O Devices for PCI, PXI ™, CompactPCI, and PCMCIA Bus Computers 6023E/6024E/6025E User Manual December 2000 Edition Part Number 322072C-01
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Important Information Warranty The DAQCard-6024E, PCI-6023E, PCI-6024E, PCI-6025E, and PXI-6025E devices are warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
Contents About This Manual Conventions Used in This Manual.................................................................................xi Related Documentation..................................................................................................xii Chapter 1 Introduction Features of the 6023E, 6024E, and 6025E.....................................................................1-1 Using PXI with CompactPCI......................................................................................
Contents Chapter 4 Signal Connections I/O Connector ................................................................................................................ 4-1 Analog Input Signal Overview...................................................................................... 4-8 Types of Signal Sources.................................................................................. 4-8 Floating Signal Sources ....................................................................
Contents Waveform Generation Timing Connections ...................................................4-40 WFTRIG Signal ................................................................................4-40 UPDATE* Signal..............................................................................4-41 UISOURCE Signal ...........................................................................4-42 General-Purpose Timing Signal Connections .................................................
Contents Figures Figure 1-1. The Relationship Between the Programming Environment, NI-DAQ, and Your Hardware............................................................... 1-5 Figure 3-1. PCI-6023E, PCI-6024E, PCI-6025E, and PXI-6025E Block Diagram ...................................................................................... 3-1 DAQCard-6024E Block Diagram......................................................... 3-2 Dithering .....................................................................
Contents Figure 4-30. Figure 4-31. Figure 4-32. Figure 4-33. Figure 4-34. Figure 4-35. Figure 4-36. Figure 4-37. Figure 4-38. Figure 4-39. Figure 4-40. Figure 4-41. WFTRIG Input Signal Timing ..............................................................4-41 WFTRIG Output Signal Timing............................................................4-41 UPDATE* Input Signal Timing............................................................4-42 UPDATE* Output Signal Timing ......................................
About This Manual The 6023, 6024, and 6025 E Series boards are high-performance multifunction analog, digital, and timing I/O boards for PCI, PXI, PCMCIA, and CompactPCI bus computers. Supported functions include analog input, analog output, digital I/O, and timing I/O. This manual describes the electrical and mechanical aspects of the PCI-6023E, PCI-6024E, DAQCard-6024E, PCI-6025E, and PXI-6025E boards from the E Series product line and contains information concerning their operation and programming.
About This Manual programs, subprograms, subroutines, device names, functions, operations, variables, filenames and extensions, and code excerpts. NI-DAQ NI-DAQ refers to the NI-DAQ driver software for PC compatible computers unless otherwise noted. PXI PXI stands for PCI eXtensions for Instrumentation. PXI is an open specification that builds off the CompactPCI specification by adding instrumentation-specific features.
1 Introduction This chapter describes the 6023E, 6024E, and 6025E devices, lists what you need to get started, gives unpacking instructions, and describes the optional software and equipment. Features of the 6023E, 6024E, and 6025E The 6025E features 16 channels (eight differential) of analog input, two channels of analog output, a 100-pin connector, and 32 lines of digital I/O.
Chapter 1 Introduction These devices can interface to an SCXI system—the instrumentation front end for plug-in DAQ devices—so that you can acquire analog signals from thermocouples, RTDs, strain gauges, voltage sources, and current sources. You can also acquire or generate digital signals for communication and control. Using PXI with CompactPCI Using PXI compatible products with standard CompactPCI products is an important feature provided by PXI Specification, Revision 1.0.
Chapter 1 Introduction ❑ 6023E/6024E/6025E User Manual ❑ One of the following software packages and documentation: – LabVIEW for Windows – Measurement Studio – VirtualBench ❑ NI-DAQ for PC Compatibles ❑ Your computer equipped with one of the following: – PCI bus for a PCI device – PXI or CompactPCI chassis and controller for a PXI device – Type II PCMCIA slot for a DAQCard device Read Chapter 2, Installation and Configuration, before installing your device.
Chapter 1 Introduction programming interface for building virtual instruments. For Visual C++ developers, Measurement Studio offers a set of Visual C++ classes and tools to integrate those classes into Visual C++ applications. The libraries, ActiveX controls, and classes are available with Measurement Studio and the NI-DAQ software.
Chapter 1 Conventional Programming Environment Introduction LabVIEW, Measurement Studio, or VirtualBench NI-DAQ Driver Software DAQ or SCXI Hardware Personal Computer or Workstation Figure 1-1. The Relationship Between the Programming Environment, NI-DAQ, and Your Hardware To download a free copy of the most recent version of NI-DAQ, click Download Software at ni.com.
Chapter 1 Introduction For more information about these products, refer to the National Instruments catalogue or web site or call the office nearest you. 6023E/6024E/6025E User Manual 1-6 ni.
2 Installation and Configuration This chapter explains how to install and configure your 6023E, 6024E, or 6025E device. Software Installation Install your software before installing your device. If you are using LabVIEW, LabWindows/CVI, ComponentWorks, or VirtualBench, install this software before installing the NI-DAQ driver software. Refer to the software release notes of your software for installation instructions. If you are using NI-DAQ, refer to your NI-DAQ release notes.
Chapter 2 Installation and Configuration Hardware Installation After installing your software, you are ready to install your hardware. Your device will fit in any available slot in your computer. However, to achieve best noise performance, leave as much room as possible between your device and other devices. The following are general installation instructions. Consult your computer user manual or technical reference manual for specific instructions and warnings. ♦ ♦ PCI device installation 1.
Chapter 2 Installation and Configuration 4. Touch any metal part of your computer chassis to discharge any static electricity that might be on your clothes or body. 5. Insert the device into a 5 V PXI slot. Use the injector/ejector handle to fully insert the device into the chassis. 6. Screw the front panel of the device to the front panel mounting rail of the system. 7. Visually verify the installation. 8. Plug in and turn on your computer. The device is installed.
3 Hardware Overview This chapter presents an overview of the hardware functions on your device. Figure 3-1 shows a block diagram for the PCI-6023E, PCI-6024E, PCI-6025E, and PXI-6025E.
Chapter 3 Hardware Overview Figure 3-2 shows the block diagram for the DAQCard-6024E.
Chapter 3 Hardware Overview Table 3-1. Available Input Configurations Configuration Description DIFF A channel configured in DIFF mode uses two analog input lines. One line connects to the positive input of the programmable gain instrumentation amplifier (PGIA) of the device, and the other connects to the negative input of the PGIA. RSE A channel configured in RSE mode uses one analog input line, which connects to the positive input of the PGIA.
Chapter 3 Hardware Overview Dithering When you enable dithering, you add approximately 0.5 LSBrms of white Gaussian noise to the signal to be converted by the ADC. This addition is useful for applications involving averaging to increase the resolution of your device, as in calibration or spectral analysis. In such applications, noise modulation is decreased and differential linearity is improved by the addition of dithering.
Chapter 3 LSBs 6.0 LSBs 6.0 4.0 4.0 2.0 2.0 0.0 0.0 -2.0 -2.0 -4.0 -4.0 Hardware Overview -6.0 -6.0 0 100 200 300 400 0 500 a. Dither disabled; no averaging 100 200 300 400 500 b. Dither disabled; average of 50 acquisitions LSBs 6.0 LSBs 6.0 4.0 4.0 2.0 2.0 0.0 0.0 -2.0 -2.0 -4.0 -4.0 -6.0 -6.0 0 100 200 300 400 500 0 c. Dither enabled; no averaging 100 200 300 400 500 d. Dither enabled; average of 50 acquisitions Figure 3-3.
Chapter 3 Hardware Overview The approximately 4 V step from 4 V to 1 mV is 4,000% of the new full-scale range. It can take as long as 100 µs for the circuitry to settle to 1 LSB after such a large transition. In general, this extra settling time is not needed when the PGIA is switching to a lower gain.
Chapter 3 Hardware Overview Digital I/O The devices contain eight lines of digital I/O (DIO<0..7>) for general-purpose use. You can individually software-configure each line for either input or output. At system startup and reset, the digital I/O ports are all high impedance. The hardware up/down control for general-purpose counters 0 and 1 are connected onboard to DIO6 and DIO7, respectively. Thus, you can use DIO6 and DIO7 to control the general-purpose counters.
Chapter 3 Hardware Overview † RTSI Trigger <0..6> CONVERT* PFI<0..9> Sample Interval Counter TC GPCTR0_OUT † PCI and PXI Buses Only Figure 3-4. CONVERT* Signal Routing Figure 3-4 shows that CONVERT* can be generated from a number of sources, including the external signals RTSI<0..6> (PCI and PXI buses only) and PFI<0..9> and the internal signals Sample Interval Counter TC and GPCTR0_OUT.
Chapter 3 Hardware Overview scheme reduces the need to change physical connections to the I/O connector for different applications. You can also individually enable each of the PFI pins to output a specific internal timing signal. For example, if you need the UPDATE* signal as an output on the I/O connector, software can turn on the output driver for the PFI5/UPDATE* pin.
Chapter 3 Hardware Overview DAQ-STC TRIG1 TRIG2 CONVERT* WFTRIG GPCTR0_SOURCE Trigger 7 RTSI Switch RTSI Bus Connector UPDATE* GPCTR0_GATE GPCTR0_OUT STARTSCAN AIGATE SISOURCE UISOURCE GPCTR1_SOURCE Clock GPCTR1_GATE switch RTSI_OSC (20 MHz) Figure 3-5. PCI RTSI Bus Signal Connection 6023E/6024E/6025E User Manual 3-10 ni.
Chapter 3 Hardware Overview DAQ-STC TRIG1 TRIG2 CONVERT* UPDATE* PXI Star (6) GPCTR0_SOURCE RTSI Switch PXI Bus Connector WFTRIG PXI Trigger (0..5) GPCTR0_GATE GPCTR0_OUT STARTSCAN AIGATE SISOURCE UISOURCE GPCTR1_SOURCE GPCTR1_GATE PXI Trigger (7) RTSI_OSC (20 MHz) switch Figure 3-6. PXI RTSI Bus Signal Connection Table 3-3 lists the name and number of pins used by the PXI-6025E. Table 3-3. Pins Used by PXI E Series Device PXI E Series Signal PXI Pin Name PXI J2 Pin Number RTSI<0..
4 Signal Connections This chapter describes how to make input and output signal connections to your device through the I/O connector. Table 4-1 shows the cables that can be used with the I/O connectors to connect to different accessories. Table 4-1.
Chapter 4 Signal Connections assignments of the optional 50- and 68-pin connectors. A signal description follows the figures.
Chapter 4 AIGND AIGND ACH0 ACH8 ACH1 ACH9 ACH2 ACH10 ACH3 ACH11 ACH4 ACH12 ACH5 ACH13 ACH6 ACH14 ACH7 ACH15 AISENSE DAC0OUT DAC1OUT RESERVED AOGND DGND DIO0 DIO4 DIO1 DIO5 DIO2 DIO6 DIO3 DIO7 DGND +5 V +5 V SCANCLK EXTSTROBE* PFI0/TRIG1 PFI1/TRIG2 PFI2/CONVERT* PFI3/GPCTR1_SOURCE PFI4/GPCTR1_GATE GPCTR1_OUT PFI5/UPDATE* PFI6/WFTRIG PFI7/STARTSCAN PFI8/GPCTR0_SOURCE PFI9/GPCTR0_GATE GPCTR0_OUT FREQ_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
Chapter 4 Signal Connections Table 4-2 shows the I/O connector signal descriptions for the 6023E, 6024E, and 6025E. Table 4-2. I/O Connector Signal Descriptions Signal Name Reference Direction Description — — Analog input ground—these pins are the reference point for single-ended measurements in RSE configuration and the bias current return point for DIFF measurements. All three ground references—AIGND, AOGND, and DGND—are connected on your device. ACH<0..
Chapter 4 Signal Connections Table 4-2. I/O Connector Signal Descriptions (Continued) Signal Name Reference Direction Description SCANCLK DGND Output scan clock—this pin pulses once for each A/D conversion in scanning mode when enabled. The low-to-high edge indicates when the input signal can be removed from the input or switched to another signal. EXTSTROBE* DGND Output External strobe—you can toggle this output under software control to latch signals or trigger events on external devices.
Chapter 4 Signal Connections Table 4-2. I/O Connector Signal Descriptions (Continued) Signal Name PFI5/UPDATE* Reference Direction DGND Input Description PFI5/Update—as an input, this is one of the PFIs. Output PFI6/WFTRIG DGND As an output, this is the UPDATE* (AO Update) signal. A high-to-low edge on UPDATE* indicates that the analog output primary group is being updated for the 6024E or 6025E. Input PFI6/Waveform Trigger—as an input, this is one of the PFIs.
Chapter 4 Signal Connections Table 4-3 shows the I/O signal summary for the 6023E, 6024E, and 6025E. Table 4-3. I/O Signal Summary Signal Type and Direction Impedance Input/ Output Protection (Volts) On/Off Source (mA at V) Sink (mA at V) Rise Time (ns) Bias ACH<0..15> AI 100 GΩ in parallel with 100 pF 42/35 — — — ±200 pA AISENSE AI 100 GΩ in parallel with 100 pF 40/25 — — — ±200 pA AIGND AO — — — — — — DAC0OUT (6024E and 6025E only) AO 0.
Chapter 4 Signal Connections Table 4-3. I/O Signal Summary (Continued) Signal Type and Direction Impedance Input/ Output Protection (Volts) On/Off Source (mA at V) Sink (mA at V) Rise Time (ns) Bias PFI4/GPCTR1_GATE DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu GPCTR1_OUT DO — — 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu PFI5/UPDATE* DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.5 50 kΩ pu PFI6/WFTRIG DIO — Vcc +0.5 3.5 at (Vcc -0.4) 5 at 0.4 1.
Chapter 4 Signal Connections Floating Signal Sources A floating signal source is not connected in any way to the building ground system, but has an isolated ground-reference point. Some examples of floating signal sources are outputs of transformers, thermocouples, battery-powered devices, optical isolators, and isolation amplifiers. An instrument or device that has an isolated output is a floating signal source.
Chapter 4 Signal Connections Vin+ Programmable Gain Instrumentation Amplifier + + PGIA Vm - Vin- Measured Voltage Vm = [Vin+ - Vin-]* Gain Figure 4-3. Programmable Gain Instrumentation Amplifier (PGIA) In single-ended mode (RSE and NRSE), signals connected to ACH<0..15> are routed to the positive input of the PGIA. In DIFF mode, signals connected to ACH<0..7> are routed to the positive input of the PGIA, and signals connected to ACH<8..15> are routed to the negative input of the PGIA.
Chapter 4 Signal Connections gain setting of the amplifier. The amplifier output voltage is referenced to the ground for the device. The A/D converter (ADC) of your device measures this output voltage when it performs A/D conversions. Reference all signals to ground either at the source device or at the device.
Chapter 4 Signal Connections Signal Source Type Grounded Signal Source Floating Signal Source (Not Connected to Building Ground) Input Examples • Ungrounded Thermocouples • Signal conditioning with isolated outputs • Battery devices ACH(+) + V1 - ACH (-) Examples • Plug-in instruments with nonisolated outputs ACH(+) + + V1 - - + ACH (-) - R Differential (DIFF) AIGND AIGND See text for information on bias resistors.
Chapter 4 Signal Connections Differential Connection Considerations (DIFF Input Configuration) A DIFF connection is one in which the analog input signal has its own reference signal or signal return path. These connections are available when the selected channel is configured in DIFF input mode. The input signal is connected to the positive input of the PGIA, and its reference signal, or return, is connected to the negative input of the PGIA.
Chapter 4 Signal Connections Differential Connections for Ground-Referenced Signal Sources Figure 4-5 shows how to connect a ground-referenced signal source to a channel on the device configured in DIFF input mode. ACH+ GroundReferenced Signal Source + Programmable Gain Instrumentation Amplifier + Vs – PGIA + ACH– – CommonMode Noise and Ground Potential Measured Voltage Vm – + Vcm – Input Multiplexers AISENSE AIGND I/O Connector Selected Channel in DIFF Configuration Figure 4-5.
Chapter 4 Signal Connections Differential Connections for Nonreferenced or Floating Signal Sources Figure 4-6 shows how to connect a floating signal source to a channel configured in DIFF input mode. ACH+ Floating Signal Source + Bias resistors (see text) Vs + – Programmable Gain Instrumentation Amplifier PGIA + ACH– – Measured Voltage Vm – Bias Current Return Paths Input Multiplexers AISENSE AIGND I/O Connector Selected Channel in DIFF Configuration Figure 4-6.
Chapter 4 Signal Connections You must reference the source to AIGND. The easiest way is to connect the positive side of the signal to the positive input of the PGIA and connect the negative side of the signal to AIGND as well as to the negative input of the PGIA, without any resistors at all. This connection works well for DC-coupled sources with low source impedance (less than 100 Ω). However, for larger source impedances, this connection leaves the DIFF signal path significantly out of balance.
Chapter 4 Signal Connections Single-Ended Connection Considerations A single-ended connection is one in which the device analog input signal is referenced to a ground that it can share with other input signals. The input signal is tied to the positive input of the PGIA, and the ground is tied to the negative input of the PGIA. When every channel is configured for single-ended input, up to 16 analog input channels are available.
Chapter 4 Signal Connections Single-Ended Connections for Floating Signal Sources (RSE Configuration) Figure 4-7 shows how to connect a floating signal source to a channel configured for RSE mode. ACH + Floating Signal Source + Programmable Gain Instrumentation Amplifier Vs PGIA – + Input Multiplexers – AISENSE Measured Voltage Vm – AIGND I/O Connector Selected Channel in RSE Configuration Figure 4-7.
Chapter 4 Signal Connections Figure 4-8 shows how to connect a grounded signal source to a channel configured for NRSE mode. ACH<0..15> Instrumentation Amplifier + GroundReferenced Signal Source + Vs PGIA – + Input Multiplexers CommonMode Noise and Ground Potential + AISENSE AIGND Vcm Measured Voltage Vm – – – Selected Channel in NRSE Configuration I/O Connector Figure 4-8.
Chapter 4 Signal Connections AOGND is the ground reference signal for both analog output channels and the external reference signal. Figure 4-9 shows how to make analog output connections to your device. DAC0OUT Channel 0 + VOUT 0 Load – AOGND – VOUT 1 Load + DAC1OUT Channel 1 Analog Output Channels I/O Connector Figure 4-9. Analog Output Connections Digital I/O Signal Connections All Devices All devices have digital I/O signals DIO<0..7> and DGND. DIO<0..
Chapter 4 Signal Connections +5 V LED DIO<4..7> TTL Signal DIO<0..3> +5 V Switch DGND I/O Connector Figure 4-10. Digital I/O Connections Figure 4-10 shows DIO<0..3> configured for digital input and DIO<4..7> configured for digital output. Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch shown in the Figure 4-11.
Chapter 4 Signal Connections +5 V LED Port A PA<3..0> Port B TTL Signal PB<7..4> +5 V Switch GND I/O Connector DIO Device Figure 4-11. Digital I/O Connections Block Diagram Programmable Peripheral Interface (PPI) ♦ 6025E only The 6025E device uses an 82C55A PPI to provide an additional 24 lines of digital I/O that represent three 8-bit ports—PA, PB, and PC. You can program each port as an input or output port.
Chapter 4 Signal Connections TTL signals and driving external devices such as the LED shown in Figure 4-11. Port C Pin Assignments ♦ 6025 only The signals assigned to port C depend on how the 82C55A is configured. In mode 0, or no handshaking configuration, port C is configured as two 4-bit I/O ports. In modes 1 and 2, or handshaking configuration, port C is used for status and handshaking signals with any leftover lines available for general-purpose I/O.
Chapter 4 Signal Connections Power-up State ♦ 6025E only The 6025E contains bias resistors that control the state of the digital I/O lines PA<0..7>,PB<0..7>,PC<0..7> at power up. Each digital I/O line is configured as an input, pulled high by a 100 kΩ bias resistor. You can change individual lines from pulled up to pulled down by adding your own external resistors. This section describes the procedure.
Chapter 4 2. Signal Connections Using the following formula, calculate the largest possible load to maintain a logic low level of 0.4 V and supply the maximum driving current: V = I × RL ⇒ RL = V/I where: V = 0.4 V Voltage across RL I = 46 µA + 10 µA 4.6 V across the 100 kΩ pull-up resistor and 10 µA maximum leakage current Therefore: ; 0.4 V/56 µA RL = 7.1 kΩ This resistor value, 7.1 kΩ, provides a maximum of 0.4 V on the DIO line at power up.
Chapter 4 Signal Connections Table 4-5. Signal Names Used in Timing Diagrams (Continued) Name Type Description ACK* Input Acknowledge input—a low signal on this handshaking line indicates that the data written to the port has been accepted. This signal is a response from the external device indicating that it has received the data from your DIO device. OBF* Output Output buffer full—a low signal on this handshaking line indicates that data has been written to the port.
Chapter 4 Signal Connections Mode 1 Input Timing Timing specifications for an input transfer in mode 1 are shown in Figure 4-13. T1 T2 T4 STB * T7 IBF T6 INTR RD * T3 T5 DATA Name Description Minimum Maximum T1 STB* Pulse Width 100 — T2 STB* = 0 to IBF = 1 — 150 T3 Data before STB* = 1 20 — T4 STB* = 1 to INTR = 1 — 150 T5 Data after STB* = 1 50 — T6 RD* = 0 to INTR = 0 — 200 T7 RD* = 1 to IBF = 0 — 150 All timing values are in nanoseconds. Figure 4-13.
Chapter 4 Signal Connections Mode 1 Output Timing Timing specifications for an output transfer in mode 1 are shown in Figure 4-14. T3 WR* T4 OBF* T1 T6 INTR T5 ACK* DATA T2 Name Description Minimum Maximum T1 WR* = 0 to INTR = 0 — 250 T2 WR* = 1 to Output — 200 T3 WR* = 1 to OBF* = 0 — 150 T4 ACK* = 0 to OBF* = 1 — 150 T5 ACK* Pulse Width 100 — T6 ACK* = 1 to INTR = 1 — 150 All timing values are in nanoseconds. Figure 4-14.
Chapter 4 Signal Connections Mode 2 Bidirectional Timing Timing specifications for a bidirectional transfer in mode 2 are shown in Figure 4-15.
Chapter 4 Signal Connections Power Connections Two pins on the I/0 connector supply +5 V from the computer power supply through a self-resetting fuse. The fuse resets automatically within a few seconds after the overcurrent condition is removed. These pins are referenced to DGND and you can use them to power external digital circuitry. The power rating is +4.65 to +5.25 VDC at 1 A for the PCI and PXI devices, and +4.65 to +5.25 VDC at 0.75A for PCMCIA cards.
Chapter 4 Signal Connections PFI0/TRIG1 PFI2/CONVERT* TRIG1 Source CONVERT* Source DGND I/O Connector Figure 4-16. Timing I/O Connections Programmable Function Input Connections There are a total of 13 internal timing signals that you can externally control from the PFI pins. The source for each of these signals is software-selectable from any of the PFIs when you want external control.
Chapter 4 Signal Connections depends upon the particular timing signal you are controlling. The detection requirements for each timing signal are listed within the section that discusses that individual signal. In edge-detection mode, the minimum pulse width required is 10 ns. This applies for both rising-edge and falling-edge polarity settings. There is no maximum pulse-width requirement in edge-detect mode.
Chapter 4 Signal Connections TRIG1 TRIG2 Don't Care STARTSCAN CONVERT* Scan Counter 3 2 1 0 2 2 2 1 0 Figure 4-18. Typical Pretriggered Acquisition SCANCLK Signal SCANCLK is an output-only signal that generates a pulse with the leading edge occurring approximately 50 to 100 ns after an A/D conversion begins.
Chapter 4 Signal Connections V OH V OL tw tw t w = 600 ns or 5 µs Figure 4-20. EXTSTROBE* Signal Timing TRIG1 Signal Any PFI pin can externally input the TRIG1 signal, which is available as an output on the PFI0/TRIG1 pin. Refer to Figures 4-17 and 4-18 for the relationship of TRIG1 to the DAQ sequence. As an input, the TRIG1 signal is configured in the edge-detection mode. You can select any PFI pin as the source for TRIG1 and configure the polarity selection for either rising or falling edge.
Chapter 4 Signal Connections tw tw = 50-100 ns Figure 4-22. TRIG1 Output Signal Timing The device also uses the TRIG1 signal to initiate pretriggered DAQ operations. In most pretriggered applications, the TRIG1 signal is generated by a software trigger. Refer to the TRIG2 signal description for a complete description of the use of TRIG1 and TRIG2 in a pretriggered DAQ operation. TRIG2 Signal Any PFI pin can externally input the TRIG2 signal, which is available as an output on the PFI1/TRIG2 pin.
Chapter 4 Signal Connections Figures 4-23 and 4-24 show the input and output timing requirements for the TRIG2 signal. tw Rising-Edge Polarity Falling-Edge Polarity t w = 10 ns minimum Figure 4-23. TRIG2 Input Signal Timing tw tw = 50-100 ns Figure 4-24. TRIG2 Output Signal Timing STARTSCAN Signal Any PFI pin can externally input the STARTSCAN signal, which is available as an output on the PFI7/STARTSCAN pin. Refer to Figures 4-17 and 4-18 for the relationship of STARTSCAN to the DAQ sequence.
Chapter 4 Signal Connections deasserted toff after the last conversion in the scan is initiated. This output is set to high impedance at startup. Figures 4-25 and 4-26 show the input and output timing requirements for the STARTSCAN signal. tw Rising-Edge Polarity Falling-Edge Polarity t w = 10 ns minimum Figure 4-25. STARTSCAN Input Signal Timing tw STARTSCAN t w = 50-100 ns a. Start of Scan Start Pulse CONVERT* STARTSCAN toff = 10 ns minimum toff b.
Chapter 4 Signal Connections A counter on your device internally generates the STARTSCAN signal unless you select some external source. This counter is started by the TRIG1 signal and is stopped either by software or by the sample counter. Scans generated by either an internal or external STARTSCAN signal are inhibited unless they occur within a DAQ sequence. Scans occurring within a DAQ sequence can be gated by either the hardware (AIGATE) signal or software command register gate.
Chapter 4 Signal Connections tw t w = 50-150 ns Figure 4-28. CONVERT* Output Signal Timing The sample interval counter on the device normally generates the CONVERT* signal unless you select some external source. The counter is started by the STARTSCAN signal and continues to count down and reload itself until the scan is finished. It then reloads itself in preparation for the next STARTSCAN pulse.
Chapter 4 Signal Connections SISOURCE Signal Any PFI pin can externally input the SISOURCE signal, which is not available as an output on the I/O connector. The onboard scan interval counter uses the SISOURCE signal as a clock to time the generation of the STARTSCAN signal. You must configure the PFI pin you select as the source for the SISOURCE signal in the level-detection mode. You can configure the polarity selection for the PFI pin for either active high or active low.
Chapter 4 Signal Connections As an output, the WFTRIG signal reflects the trigger that initiates waveform generation. This is true even if the waveform generation is externally triggered by another PFI. The output is an active high pulse with a pulse width of 50 to 100 ns. This output is set to high impedance at startup. Figures 4-30 and 4-31 show the input and output timing requirements for the WFTRIG signal. tw Rising-Edge Polarity Falling-Edge Polarity t w = 10 ns minimum Figure 4-30.
Chapter 4 Signal Connections As an output, the UPDATE* signal reflects the actual update pulse that is connected to the DACs. This is true even if the updates are externally generated by another PFI. The output is an active low pulse with a pulse width of 300 to 350 ns. This output is set to high impedance at startup. Figures 4-32 and 4-33 show the input and output timing requirements for the UPDATE* signal. tw Rising-Edge Polarity Falling-Edge Polarity t w = 10 ns minimum Figure 4-32.
Chapter 4 Signal Connections signal. You must configure the PFI pin you select as the source for the UISOURCE signal in the level-detection mode. You can configure the polarity selection for the PFI pin for either active high or active low. Figure 4-34 shows the timing requirements for the UISOURCE signal. tp tw tw t p = 50 ns minimum t w = 23 ns minimum Figure 4-34. UISOURCE Signal Timing The maximum allowed frequency is 20 MHz, with a minimum pulse width of 23 ns high or low.
Chapter 4 Signal Connections Figure 4-35 shows the timing requirements for the GPCTR0_SOURCE signal. tp tw tw t p = 50 ns minimum t w = 23 ns minimum Figure 4-35. GPCTR0_SOURCE Signal Timing The maximum allowed frequency is 20 MHz, with a minimum pulse width of 23 ns high or low. There is no minimum frequency limitation. The 20 MHz or 100 kHz timebase normally generates the GPCTR0_SOURCE signal unless you select some external source.
Chapter 4 Signal Connections tw Rising-Edge Polarity Falling-Edge Polarity t w = 10 ns minimum Figure 4-36. GPCTR0_GATE Signal Timing in Edge-Detection Mode GPCTR0_OUT Signal This signal is available only as an output on the GPCTR0_OUT pin. The GPCTR0_OUT signal reflects the terminal count (TC) of general-purpose counter 0. You have two software-selectable output options—pulse on TC and toggle output polarity on TC. The output polarity is software-selectable for both options.
Chapter 4 Signal Connections GPCTR1_SOURCE Signal Any PFI pin can externally input the GPCTR1_SOURCE signal, which is available as an output on the PFI3/GPCTR1_SOURCE pin. As an input, the GPCTR1_SOURCE signal is configured in the edge-detection mode. You can select any PFI pin as the source for GPCTR1_SOURCE and configure the polarity selection for either rising or falling edge. As an output, the GPCTR1_SOURCE monitors the actual clock connected to general-purpose counter 1.
Chapter 4 Signal Connections As an output, the GPCTR1_GATE signal monitors the actual gate signal connected to general-purpose counter 1. This is true even if the gate is externally generated by another PFI. This output is set to high impedance at startup. Figure 4-39 shows the timing requirements for the GPCTR1_GATE signal. tw Rising-Edge Polarity Falling-Edge Polarity t w = 10 ns minimum Figure 4-39.
Chapter 4 Signal Connections leave the DIO7 pin free for general use. Figure 4-41 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals of your device.
Chapter 4 Signal Connections If you use an internal timebase clock, the gate signal cannot be synchronized with the clock. In this case, gates applied close to a source edge take effect either on that source edge or on the next one. This arrangement results in an uncertainty of one source clock period with respect to unsynchronized gating sources. The OUT output timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated clock signals on the devices.
5 Calibration This chapter discusses the calibration procedures for your device. If you are using the NI-DAQ device driver, that software includes calibration functions for performing all of the steps in the calibration process. Calibration refers to the process of minimizing measurement and output voltage errors by making small circuit adjustments. For these devices, these adjustments take the form of writing values to onboard calibration DACs (CalDACs).
Chapter 5 Calibration This method of calibration is not very accurate because it does not take into account the fact that the device measurement and output voltage errors can vary with time and temperature. It is better to self-calibrate the device when it is installed in the environment in which it will be used. Self-Calibration Your device can measure and correct for almost all of its calibration-related errors without any external signal connections.
Chapter 5 Calibration Other Considerations The CalDACs adjust the gain error of each analog output channel by adjusting the value of the reference voltage supplied to that channel. This calibration mechanism is designed to work only with the internal 10 V reference. Thus, in general, it is not possible to calibrate the analog output gain error when using an external reference.
A Specifications This appendix individually lists the specifications of each bus type and are typical at 25 °C. PCI and PXI Buses Analog Input Input Characteristics Number of channels ............................... 16 single-ended or 8 differential (software-selectable per channel) Type of ADC.......................................... Successive approximation Resolution .............................................. 12 bits, 1 in 4,096 Sampling rate .........................................
Appendix A Specifications for PCI and PXI Buses Overvoltage protection Signal Powered On Powered Off ACH<0..15> ±42 ±35 AISENSE ±40 ±25 FIFO buffer size......................................512 S Data transfers ..........................................DMA, interrupts, programmed I/O DMA modes ...........................................Scatter-gather (single transfer, demand transfer) Configuration memory size ....................
Appendix A Specifications for PCI and PXI Buses Transfer Characteristics Relative accuracy ................................... ±0.5 LSB typ dithered, ±1.5 LSB max undithered DNL ....................................................... ±0.5 LSB typ, ±1.0 LSB max No missing codes ................................... 12 bits, guaranteed Offset error Pregain error after calibration ......... ±12 µV max Pregain error before calibration ...... ±28 mV max Postgain error after calibration ....... ±0.
Appendix A Specifications for PCI and PXI Buses Dynamic Characteristics Bandwidth Signal Bandwidth Small (–3 dB) 500 kHz Large (1% THD) 225 kHz Settling time for full-scale step...............5 µs max to ±1.0 LSB accuracy System noise (LSBrms, not including quantization) Gain Dither Off Dither On 0.5 to 10 0.1 0.6 100 0.7 0.8 Crosstalk .................................................–60 dB, DC to 100 kHz Stability Recommended warm-up time.................15 min.
Appendix A Specifications for PCI and PXI Buses FIFO buffer size ..................................... None Data transfers ......................................... DMA, interrupts, programmed I/O DMA modes........................................... Scatter-gather (Single transfer, demand transfer) Accuracy Information Absolute Accuracy Positive FS Negative FS 24 Hours 90 Days 1 Year Offset (mV) Temp Drift (%/ °C) Absolute Accuracy at Full Scale (mV) 10 –10 0.0177 0.0197 0.0219 5.93 0.
Appendix A Specifications for PCI and PXI Buses Voltage Output Range ......................................................± 10 V Output coupling ......................................DC Output impedance...................................0.1 Ω max Current drive...........................................±5 mA max Protection................................................Short-circuit to ground Power-on state (steady state) ..................±200 mV Initial power-up glitch Magnitude.........................
Appendix A Specifications for PCI and PXI Buses Digital I/O Number of channels 6025E .............................................. 32 input/output 6023E and 6024E............................ 8 input/output Compatibility ......................................... TTL/CMOS DIO<0..7> Digital logic levels Level Min Max Input low voltage 0V 0.8 V Input high voltage 2V 5V Input low current (Vin = 0 V) — –320 µA Input high current (Vin = 5 V) — 10 µA Output low voltage (IOL = 24 mA) — 0.
Appendix A Specifications for PCI and PXI Buses Handshaking ...........................................2-wire Power-on state PA<0..7> .........................................Input (High-Z), 100 kΩ pull-up to +5 VDC PB<0..7>..........................................Input (High-Z), 100 kΩ pull-up to +5 VDC PC<0..7>..........................................Input (High-Z), 100 kΩ pull-up to +5 VDC Data transfers ..........................................
Appendix A Specifications for PCI and PXI Buses Triggers Digital Trigger Compatibility ......................................... TTL Response ................................................ Rising or falling edge Pulse width............................................. 10 ns min RTSI Trigger lines ........................................... 7 Calibration Recommended warm-up time ................ 15 min Interval ................................................... 1 year External calibration reference ..
Appendix A Specifications for PCI and PXI Buses I/O connector 6023E/6024E ...................................68-pin male SCSI-II type 6025E...............................................100-pin female 0.05D type Operating Environment Ambient temperature ..............................0 to 55 °C Relative humidity ...................................10 to 90% noncondensing ♦ PXI-6025E only Functional shock.....................................MIL-T-28800 E Class 3 (per Section 4.5.5.4.
Appendix A Specifications for PCMCIA Bus PCMCIA Bus Analog Input Input Characteristics Number of channels ............................... 16 single-ended or 8 differential (software-selectable per channel) Type of ADC.......................................... Successive approximation Resolution .............................................. 12 bits, 1 in 4,096 Sampling rate ........................................ 200 kS/s guaranteed Input signal ranges ................................
Appendix A Specifications for PCMCIA Bus Accuracy Information Absolute Accuracy Nominal Range (V) Relative Accuracy Noise + Quantization (mV) % of Reading Absolute Accuracy at Full Scale (mV) Single Pt. Averaged Resolution (mV) Positive FS Negative FS 24 Hours 1 Year Offset (mV) Single Pt. Averaged Temp Drift (%/ °C) 10 –10 0.0872 0.0914 8.83 3.91 1.042 0.0010 19.012 5.89 1.37 5 –5 0.0272 0.0314 4.42 1.95 0.521 0.0005 6.517 2.95 0.686 0.5 –0.5 0.0872 0.0914 0.
Appendix A Specifications for PCMCIA Bus Amplifier Characteristics Input impedance Normal powered on ........................ 100 GΩ in parallel with 100 pF Powered off..................................... 4 kΩ min Overload.......................................... 4 kΩ min Input bias current ................................... ±200 pA Input offset current................................. ±100 pA CMRR (DC to 60 Hz) Gain 0.5, 1.0.................................... 85 dB Gain 10, 100.......................
Appendix A Specifications for PCMCIA Bus Gain temperature coefficient ..................±20 ppm/°C Analog Output Output Characteristics Number of channels................................2 voltage Resolution ...............................................12 bits, 1 in 4,096 Max update rate Interrupts..........................................1 kHz, system dependent Type of DAC ..........................................Double buffered, multiplying FIFO buffer size......................................
Appendix A Specifications for PCMCIA Bus Offset error After calibration .............................. ±1.0 mV max Before calibration ........................... ±200 mV max Gain error (relative to internal reference) After calibration .............................. ±0.01% of output max Before calibration ........................... ±0.75% of output max Voltage Output Range ..................................................... ± 10 V Output coupling......................................
Appendix A Specifications for PCMCIA Bus Stability Offset temperature coefficient ................±50 µV/°C Gain temperature coefficient ..................±25 ppm/°C Digital I/O Number of channels................................8 input/output Compatibility ..........................................TTL/CMOS DIO<0..7> Digital logic levels Level Min Max Input low voltage 0V 0.
Appendix A Specifications for PCMCIA Bus Base clocks available Counter/timers ................................ 20 MHz, 100 kHz Frequency scalers............................ 10 MHz, 100 kHz Base clock accuracy ............................... ±0.01% Max source frequency ............................ 20 MHz Min source pulse duration...................... 10 ns in edge-detect mode Min gate pulse duration.......................... 10 ns in edge-detect mode Data transfers ........................................
Appendix A Specifications for PCMCIA Bus Physical PC card type............................................Type II I/O connector ..........................................68-position VHDCI female connector Environment Operating temperature ............................0 to 40 °C with a maximum internal device temperature of 70 °C as measured by onboard temperature sensor. Storage temperature ................................–20 to 70 °C Relative humidity ...................................
B Custom Cabling and Optional Connectors This appendix describes the various cabling and connector options for the DAQCard-6024E, PCI-6023E, PCI-6024E, PCI-6025E, and PXI-6025E devices. Custom Cabling National Instruments offers cables and accessories for you to prototype your application or to use if you frequently change device interconnections.
Appendix B Custom Cabling and Optional Connectors ♦ 6025E AMP 100-position IDC male connector AMP backshell, 0.50 max O.D. cable AMP backshell, 0.55 max O.D. cable Mating connectors and a backshell kit for making custom 68-pin cables are available from National Instruments. Optional Connectors The following table shows the optional connector and cable assembly combinations you can use for each device.
Appendix B Custom Cabling and Optional Connectors Figure B-1 shows the pin assignments for the 68-Pin E Series connector.
Appendix B Custom Cabling and Optional Connectors Figure B-2 shows the pin assignments for the 68-pin extended digital input connector.
Appendix B Custom Cabling and Optional Connectors Figure B-3 shows the pin assignments for the 50-pin E Series connector.
Appendix B Custom Cabling and Optional Connectors Figure B-4 shows the pin assignments for the 50-pin extended digital input connector. PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 +5 V 1 3 5 2 4 6 GND GND 7 9 11 13 15 17 8 10 12 14 16 18 GND GND 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Figure B-4.
C Common Questions This appendix contains a list of commonly asked questions and their answers relating to usage and special features of your device. General Information What is the DAQ-STC? The DAQ-STC is the system timing control application-specific integrated circuit (ASIC) designed by National Instruments and is the backbone of the E Series devices. The DAQ-STC contains seven 24-bit counters and three 16-bit counters.
Appendix C Common Questions Installation and Configuration How do I set the base address for my device? The base address of your device is assigned automatically through the PCI/PXI bus protocol. This assignment is completely transparent to you. What jumpers should I be aware of when configuring my E Series device? The E Series devices are jumperless and switchless.
Appendix C Common Questions deglitching filter to remove some of these glitches, depending on the frequency and nature of your output signal. Can I synchronize a one-channel analog input data acquisition with a one-channel analog output waveform generation on my PCI E Series device? Yes. One way to accomplish this is to use the waveform generation timing pulses to control the analog input data acquisition.
Appendix C Common Questions 24-bit counters (unlike the 16-bit counters on devices without the DAQ-STC). If you are using the NI-DAQ language interface or LabWindows/CVI, the answer is no, the counter/timer applications that you wrote previously will not work with the DAQ-STC. You must use the GPCTR functions; ICTR and CTR functions will not work with the DAQ-STC.
Appendix C Common Questions after power on, and Table 4-3, I/O Signal Summary, shows that there is a 50 kΩ pull-up resistor. This pull-up resistor sets the DIO(0) pin to a logic high when the output is in a high impedance state.
Technical Support Resources D Web Support National Instruments Web support is your first stop for help in solving installation, configuration, and application problems and questions. Online problem-solving and diagnostic resources include frequently asked questions, knowledge bases, product-specific troubleshooting wizards, manuals, drivers, software updates, and more. Web support is available through the Technical Support section of ni.com NI Developer Zone The NI Developer Zone at ni.
Appendix D Technical Support Resources Worldwide Support National Instruments has offices located around the world to help address your support needs. You can access our branch office Web sites from the Worldwide Offices section of ni.com. Branch office web sites provide up-to-date contact information, support phone numbers, e-mail addresses, and current events.
Glossary Prefix Meanings Value p- pico- 10 –12 n- nano- 10 –9 µ- micro- 10 – 6 m- milli- 10 –3 k- kilo- 10 3 M- mega- 10 6 G- giga- 10 9 t- tera- 10 12 Numbers/Symbols ° degree > greater than < less than – negative of, or minus Ω ohm / per % percent ± plus or minus + positive of, or plus square root of +5 V +5 VDC source signal © National Instruments Corporation G-1 6023E/6024E/6025E User Manual
Glossary A A amperes AC alternating current ACH analog input channel signal A/D analog-to-digital ADC analog-to-digital converter—an electronic device, often an integrated circuit, that converts an analog voltage to a digital number ADC resolution the resolution of the ADC, which is measured in bits. An ADC with 16 bits has a higher resolution, and thus a higher degree of accuracy, than a 12-bit ADC.
Glossary bus the group of conductors that interconnect individual circuitry in a computer. Typically, a bus is the expansion interface to which I/O or other devices are connected. Examples of PC buses are the ISA bus and PCI bus. bus master a type of a plug-in board or controller with the ability to read and write devices on the computer bus C C Celsius CH channel channel pin or wire lead to which you apply, or from which you read, an analog or digital signal.
Glossary DAQ data acquisition—(1) collecting and measuring electrical signals from sensors, transducers, and test probes or fixtures and processing the measurement data using a computer; (2) collecting and measuring the same kinds of electrical signals with A/D and/or DIO boards plugged into a computer, and possibly generating control signals with D/A and/or DIO boards in the same computer dB decibel—the unit for expressing a logarithmic measure of the ratio of two signal levels: dB=20log10 V1/V2, for s
Glossary electrostatically coupled propagating a signal by means of a varying electric field EXTSTROBE external strobe signal F FIFO first-in first-out memory buffer floating signal sources signal sources with voltage signals that are not connected to an absolute reference or system ground. Also called nonreferenced signal sources. Some common example of floating signal sources are batteries, transformers, or thermocouples.
Glossary GPCTR1_UP_DOWN general purpose counter 1 up down GPIB General Purpose Interface bus, synonymous with HP-IB. The standard bus used for controlling electronic instruments with a computer. Also called IEEE 488 bus because it is defined by ANSI/IEEE Standards 488-1978, 488.1-1987, and 488.2-1987. grounded measurement system See RSE.
Glossary IOL current, output low IRQ interrupt request K k kilo—the standard metric prefix for 1,000, or 103, used with units of measure such as volts, hertz, and meters K kilo—the prefix for 1,024, or 210, used with B in quantifying data or computer memory kS 1,000 samples L LabVIEW laboratory virtual instrument engineering workbench LED light-emitting diode library a file containing compiled object modules, each comprised of one of more functions, that can be linked to other object modules
Glossary N NI-DAQ National Instruments driver software for DAQ hardware noise an undesirable electrical signal—Noise comes from external sources such as the AC power line, motors, generators, transformers, fluorescent lights, soldering irons, CRT displays, computers, electrical storms, welders, radio transmitters, and internal sources such as semiconductors, resistors, and capacitors. Noise corrupts signals you are trying to send or receive.
Glossary PFI7/STARTSCAN PFI7/start of scan PFI8/GPCTR0_ SOURCE PFI8/general purpose counter 0 source PFI9/GPCTR0_GATE PFI9/general purpose counter 0 gate PGIA programmable gain instrumentation amplifier port (1) a digital port consisting of multiple I/O lines on a DAQ device (2) a serial or parallel interface connector on a PC PPI programmable peripheral interface ppm parts per million pu pullup pulse trains multiple pulses Q quantization error the inherent uncertainty in digitizing an a
Glossary RSE referenced single-ended mode—all measurements are made with respect to a common reference measurement system or a ground. Also called a grounded measurement system.
Glossary SISOURCE SI counter clock signal software trigger a programmed event that triggers an event such as data acquisition software triggering a method of triggering in which you simulate an analog trigger using software. Also called conditional retrieval.
Glossary update the output equivalent of a scan. One or more analog or digital output samples. Typically, the number of output samples in an update is equal to the number of channels in the output group. For example, one pulse from the update clock produces one update which sends one new sample to every analog output channel in the group.
Glossary W waveform multiple voltage readings taken at a specific sampling rate WFTRIG waveform generation trigger signal working voltage the highest voltage that should be applied to a product in normal use, normally well under the breakdown voltage for safety margin. See also breakdown voltage.
Index Numbers AISENSE signal description (table), 4-4 NRSE mode, 4-10 signal summary (table), 4-7 analog input available input configurations (table), 3-3 common questions, C-2 to C-3 dithering, 3-4 to 3-5 input modes, 3-2 to 3-3 input range, 3-3 multichannel scanning considerations, 3-5 to 3-6 analog input signal connections, 4-8 to 4-19 common-mode signal rejection considerations, 4-19 differential connections, 4-13 to 4-16 ground-referenced signal sources, 4-14 nonreferenced or floating signal sources,
Index B dynamic characteristics, A-4 input characteristics, A-1 to A-2 stability, A-4 transfer characteristics, A-3 PCMCIA bus, A-11 to A-14 accuracy information, A-12 amplifier characteristics, A-13 dynamic characteristics, A-13 input characteristics, A-11 stability, A-13 to A-14 transfer characteristics, A-12 analog output analog output glitch, 3-6 common questions, C-2 to C-3 overview, 3-6 signal connections, 4-19 to 4-20 analog output specifications PCI and PXI buses, A-4 to A-6 accuracy information,
Index D differential connections, 4-13 to 4-16 ground-referenced signal sources, 4-14 nonreferenced or floating signal sources, 4-15 to 4-16 when to use, 4-13 digital I/O. See also PPI (Programmable Peripheral Interface). common questions, C-3 to C-5 overview, 3-7 signal connections, 4-20 to 4-22 block diagram of digital I/O connections (figure), 4-22 digital I/O connections (figure), 4-21 digital I/O specifications PCI and PXI buses, A-7 to A-8 DIO<0..7>, A-7 PA<0..7>, PB<0..7>, PC<0..
Index GPCTR0_OUT signal description (table), 4-6 general-purpose timing signal connections, 4-45 signal summary (table), 4-8 GPCTR0_SOURCE signal, 4-43 to 4-44 GPCTR0_UP_DOWN signal, 4-45 GPCTR1_GATE signal, 4-46 to 4-47 GPCTR1_OUT signal description (table), 4-5 general-purpose timing signal connections, 4-47 signal summary (table), 4-8 GPCTR1_SOURCE signal, 4-46 GPCTR1_UP_DOWN signal, 4-47 to 4-49 ground-referenced signal sources description, 4-9 differential connections, 4-14 single-ended connections (N
Index I L IBF signal description (table), 4-25 mode 1 input timing (figure), 4-27 mode 2 bidirectional timing (figure), 4-29 input modes, 3-2 to 3-3. See also analog input.
Index P PFI7/STARTSCAN signal description (table), 4-6 signal summary (table), 4-8 PFI8/GPCTR0_SOURCE signal description (table), 4-6 signal summary (table), 4-8 PFI9/GPCTR0_GATE signal description (table), 4-6 signal summary (table), 4-8 PFIs (programmable function inputs) common questions, C-4 to C-5 signal routing, 3-8 to 3-9 timing connections, 4-31 to 4-32 PGIA (programmable gain instrumentation amplifier) analog input modes, 4-9 to 4-11 differential connections ground-referenced signal sources (figu
Index referenced single-ended input (RSE). See RSE (referenced single-ended) mode.
Index programmable function input connections, 4-31 to 4-32 waveform generation timing connections, 4-40 to 4-43 signal sources, 4-8 to 4-9 floating signal sources, 4-9 ground-referenced signal sources, 4-9 single-ended connections, 4-17 to 4-19 floating signal sources (RSE configuration), 4-18 grounded signal sources (NRSE configuration), 4-18 to 4-19 when to use, 4-17 SISOURCE signal, 4-40 software installation, 2-1 software programming choices, 1-3 to 1-5 LabVIEW and LabWindows/CVI, 1-3 to 1-4 Measureme
Index GPCTR1_OUT signal, 4-47 GPCTR1_SOURCE signal, 4-46 GPCTR1_UP_DOWN signal, 4-47 to 4-49 overview, 4-30 programmable function input connections, 4-31 to 4-32 timing I/O connections (figure), 4-31 waveform generation timing connections, 4-40 to 4-43 UISOURCE signal, 4-42 to 4-43 UPDATE* signal, 4-41 to 4-42 WFTRIG signal, 4-40 to 4-41 timing I/O common questions, C-3 to C-5 specifications PCI and PXI buses, A-8 PCMCIA bus, A-16 to A-17 timing signal routing, 3-7 to 3-11 CONVERT* signal routing (figure),
Index U waveform generation timing connections, 4-40 to 4-43 UISOURCE signal, 4-42 to 4-43 UPDATE* signal, 4-41 to 4-42 WFTRIG signal, 4-40 to 4-41 Web support from National Instruments, D-1 WFTRIG signal, 4-40 to 4-41 Worldwide technical support, D-2 WR* signal description (table), 4-26 mode 1 output timing (figure), 4-28 mode 2 bidirectional timing (figure), 4-29 UISOURCE signal, 4-42 to 4-43 unpacking 6023E/6024E/6025E, 2-1 UPDATE* signal, 4-41 to 4-42 V VCC signal (table), 4-7 VirtualBench software,
