DAQ 6023E/6024E/6025E Multifunction I/O Devices User Manual
Table Of Contents
- 6023E/6024E/6025E User Manual
- Support
- Important Information
- Contents
- About This Manual
- Chapter 1 Introduction
- Chapter 2 Installation and Configuration
- Chapter 3 Hardware Overview
- Chapter 4 Signal Connections
- I/O Connector
- Analog Input Signal Overview
- Analog Input Signal Connections
- Analog Output Signal Connections
- Digital I/O Signal Connections
- Programmable Peripheral Interface (PPI)
- Power Connections
- Timing Connections
- Field Wiring Considerations
- Chapter 5 Calibration
- Appendix A Specifications
- Appendix B Custom Cabling and Optional Connectors
- Appendix C Common Questions
- Appendix D Technical Support Resources
- Glossary
- Index
- Figures
- Figure 1-1. The Relationship Between the Programming Environment, NI-DAQ, and Your Hardware
- Figure 3-1. PCI-6023E, PCI-6024E, PCI-6025E, and PXI-6025E Block Diagram
- Figure 3-2. DAQCard-6024E Block Diagram
- Figure 3-3. Dithering
- Figure 3-4. CONVERT* Signal Routing
- Figure 3-5. PCI RTSI Bus Signal Connection
- Figure 3-6. PXI RTSI Bus Signal Connection
- Figure 4-1. I/O Connector Pin Assignment for the 6023E/6024E
- Figure 4-2. I/O Connector Pin Assignment for the 6025E
- Figure 4-3. Programmable Gain Instrumentation Amplifier (PGIA)
- Figure 4-4. Summary of Analog Input Connections
- Figure 4-5. Differential Input Connections for Ground Referenced Signals
- Figure 4-6. Differential Input Connections for Nonreferenced Signals
- Figure 4-7. Single Ended Input Connections for Nonreferenced or Floating Signals
- Figure 4-8. Single Ended Input Connections for Ground Referenced Signals
- Figure 4-9. Analog Output Connections
- Figure 4-10. Digital I/O Connections
- Figure 4-11. Digital I/O Connections Block Diagram
- Figure 4-12. DIO Channel Configured for High DIO Power-up State with External Load
- Figure 4-13. Timing Specifications for Mode 1 Input Transfer
- Figure 4-14. Timing Specifications for Mode 1 Output Transfer
- Figure 4-15. Timing Specifications for Mode 2 Bidirectional Transfer
- Figure 4-16. Timing I/O Connections
- Figure 4-17. Typical Posttriggered Acquisition
- Figure 4-18. Typical Pretriggered Acquisition
- Figure 4-19. SCANCLK Signal Timing
- Figure 4-20. EXTSTROBE* Signal Timing
- Figure 4-21. TRIG1 Input Signal Timing
- Figure 4-22. TRIG1 Output Signal Timing
- Figure 4-23. TRIG2 Input Signal Timing
- Figure 4-24. TRIG2 Output Signal Timing
- Figure 4-25. STARTSCAN Input Signal Timing
- Figure 4-26. STARTSCAN Output Signal Timing
- Figure 4-27. CONVERT* Input Signal Timing
- Figure 4-28. CONVERT* Output Signal Timing
- Figure 4-29. SISOURCE Signal Timing
- Figure 4-30. WFTRIG Input Signal Timing
- Figure 4-31. WFTRIG Output Signal Timing
- Figure 4-32. UPDATE* Input Signal Timing
- Figure 4-33. UPDATE* Output Signal Timing
- Figure 4-34. UISOURCE Signal Timing
- Figure 4-35. GPCTR0_SOURCE Signal Timing
- Figure 4-36. GPCTR0_GATE Signal Timing in Edge Detection Mode
- Figure 4-37. GPCTR0_OUT Signal Timing
- Figure 4-38. GPCTR1_SOURCE Signal Timing
- Figure 4-39. GPCTR1_GATE Signal Timing in Edge Detection Mode
- Figure 4-40. GPCTR1_OUT Signal Timing
- Figure 4-41. GPCTR Timing Summary
- Figure B-1. 68 Pin E Series Connector Pin Assignments
- Figure B-2. 68 Pin Extended Digital Input Connector Pin Assignments
- Figure B-3. 50 Pin E Series Connector Pin Assignments
- Figure B-4. 50-Pin Extended Digital Input Connector Pin Assignments
- Tables
- Table 3-1. Available Input Configurations
- Table 3-2. Measurement Precision
- Table 3-3. Pins Used by PXI E Series Device
- Table 4-1. I/O Connector Details
- Table 4-2. I/O Connector Signal Descriptions
- Table 4-3. I/O Signal Summary
- Table 4-4. Port C Signal Assignments
- Table 4-5. Signal Names Used in Timing Diagrams
Index
6023E/6024E/6025E User Manual I-2 ni.com
dynamic characteristics, A-4
input characteristics, A-1 to A-2
stability, A-4
transfer characteristics, A-3
PCMCIA bus, A-11 to A-14
accuracy information, A-12
amplifier characteristics, A-13
dynamic characteristics, A-13
input characteristics, A-11
stability, A-13 to A-14
transfer characteristics, A-12
analog output
analog output glitch, 3-6
common questions, C-2 to C-3
overview, 3-6
signal connections, 4-19 to 4-20
analog output specifications
PCI and PXI buses, A-4 to A-6
accuracy information, A-5
dynamic characteristics, A-6
output characteristics, A-4 to A-5
stability, A-6
transfer characteristics, A-5
voltage output, A-6
PCMCIA bus, A-14 to A-16
accuracy information, A-14
dynamic characteristics, A-15
output characteristics, A-14
stability, A-16
transfer characteristics, A-14 to A-15
voltage output, A-15
AOGND signal
analog output signal connections,
4-19 to 4-20
description (table), 4-4
signal summary (table), 4-7
B
bipolar input, 3-3
block diagrams
6023E/6024E/6025E devices, 3-1
DAQCard-6024E, 3-2
C
cables. See also I/O connectors.
custom cabling, B-1 to B-2
field wiring considerations, 4-49
optional equipment, 1-5
calibration, 5-1 to 5-3
adjusting gain error, 5-3
external calibration, 5-2
loading calibration constants, 5-1 to 5-2
self-calibration, 5-2
specifications
PCI and PXI buses, A-9
PCMCIA bus, A-17
charge injection, 3-6
clocks, device and RTSI, 3-9
commonly asked questions. See questions and
answers.
common-mode signal rejection
considerations, 4-19
CompactPCI products, using with PXI, 1-2
configuration
common questions, C-2
hardware configuration, 2-3
connectors. See I/O connectors.
conventions used in manual, xi-xii
CONVERT* signal
DAQ timing connections, 4-38 to 4-39
signal routing (figure), 3-8
custom cabling, B-1 to B-2
customer education, D-1