User manual

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Expected Results
In theory, you should have expected a 10%-90% rise time of 0 s on the input signal from the FGEN (channel 1). You
should have also read a 10%-90% rise time that is approximately 2.2 ms as measured across the capacitor (channel 2).
Observed Results
In reality, you got something close to the expected value for 10%-90% rise time as measured across the capacitor
(channel 2). Of course, your observed value was not exactly 2.2 ms, but this was because of nonzero tolerances in the 1
kΩ resistor and 1 µF capacitor as well as your use of an equation for rise time that is an approximation based on the RC
time constant.
3.3 Interface Theory
Comparing your observed results with your simulated results for both application circuits, you can see that you were
fairly close to achieving your expected results with the physical circuits and VirtualBench. As noted previously, the small
differences from observed to simulated and expected results are because of the nonideal nature in real-world devices.
With this in mind, instructors, students, engineers, and scientists should feel comfortable moving forward with first
selecting components to realize an application circuit, then simulating the circuit, and finally interfacing with it using the
various functions of the VirtualBench device, such as the FGEN, MSO, and DC power supply.
Now you can begin to design and test more complicated circuits that use operational amplifiers, capacitors, resistors,
inductors, or active components such as diodes and transistors.