DAQ M Series NI 6236 User Manual Isolated Current Input/Voltage Output Devices NI 6236 User Manual May 2006 371948A-01
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Important Information Warranty The NI 6236 is warranted against defects in materials and workmanship for a period of three years from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
Contents About This Manual Conventions ...................................................................................................................xiii Related Documentation..................................................................................................xiv NI-DAQ...........................................................................................................xiv NI-DAQmx for Linux......................................................................................
Contents Chapter 4 Analog Input Analog Input Circuitry .................................................................................................. 4-1 Analog Input Range....................................................................................................... 4-2 Connecting Analog Current Input Signals .................................................................... 4-3 Method 1 .........................................................................................................
Contents AI Pause Trigger Signal ..................................................................................4-23 Using a Digital Source ......................................................................4-23 Routing AI Pause Trigger Signal to an Output Terminal .................4-24 Getting Started with AI Applications in Software.........................................................4-24 Chapter 5 Analog Output Analog Output Circuitry ..........................................................
Contents Chapter 7 Counters Counter Input Applications ........................................................................................... 7-2 Counting Edges ............................................................................................... 7-2 Single Point (On-Demand) Edge Counting ...................................... 7-2 Buffered (Sample Clock) Edge Counting......................................... 7-3 Non-Cumulative Buffered Edge Counting .......................................
Contents Counter Timing Signals .................................................................................................7-25 Counter n Source Signal..................................................................................7-25 Routing a Signal to Counter n Source...............................................7-26 Routing Counter n Source to an Output Terminal ............................7-26 Counter n Gate Signal .............................................................................
Contents Chapter 8 PFI Using PFI Terminals as Timing Input Signals .............................................................. 8-2 Exporting Timing Output Signals Using PFI Terminals............................................... 8-3 Using PFI Terminals as Static Digital Inputs and Outputs............................................ 8-3 Connecting PFI Input Signals........................................................................................ 8-3 PFI Filters ....................................
Contents Chapter 11 Bus Interface DMA Controllers ...........................................................................................................11-1 PXI Considerations ........................................................................................................11-2 PXI Clock and Trigger Signals........................................................................11-2 PXI and PXI Express.......................................................................................
About This Manual The NI 6236 User Manual contains information about using the NI 6236 M Series data acquisition (DAQ) devices with NI-DAQ 8.1 and later. National Instruments 6236 devices feature four analog current input (AI) channels, four analog voltage output (AO) channels, two counters, six lines of digital input (DI), and four lines of digital output (DO).
About This Manual Related Documentation Each application software package and driver includes information about writing applications for taking measurements and controlling measurement devices. The following references to documents assume you have NI-DAQ 8.1 or later, and where applicable, version 7.0 or later of the NI application software.
About This Manual NI-DAQmx Base The NI-DAQmx Base Getting Started Guide describes how to install your NI-DAQmx Base software, your NI-DAQmx Base-supported DAQ device, and how to confirm that your device is operating properly. Select Start»All Programs»National Instruments»NI-DAQmx Base»Documentation» Getting Started Guide. The NI-DAQmx Base Readme lists which devices are supported by this version of NI-DAQmx Base. Select Start»All Programs»National Instruments»NI-DAQmx Base»Documentation»Readme.
About This Manual • Taking Measurements—Contains the conceptual and how-to information you need to acquire and analyze measurement data in LabVIEW, including common measurements, measurement fundamentals, NI-DAQmx key concepts, and device considerations. LabWindows™/CVI™ The Data Acquisition book of the LabWindows/CVI Help contains measurement concepts for NI-DAQmx.
About This Manual Device Documentation and Specifications The NI 6236 Specifications contains all specifications for NI 6236 M Series devices. NI-DAQ 7.0 and later includes the Device Document Browser, which contains online documentation for supported DAQ, SCXI, and switch devices, such as help files describing device pinouts, features, and operation, and PDF files of the printed device documents.
1 Getting Started M Series NI 6236 devices feature four analog current input (AI) channels, four analog voltage output (AO) channels, two counters, six lines of digital input (DI), and four lines of digital output (DO). If you have not already installed your device, refer to the DAQ Getting Started Guide. For NI 6236 device specifications, refer to the NI 6236 Specifications on ni.com/manuals. Before installing your DAQ device, you must install the software you plan to use with the device.
Chapter 1 Getting Started Device Specifications Refer to the NI 6236 Specifications, available on the NI-DAQ Device Document Browser or ni.com/manuals, for more detailed information about NI 6236 devices. Device Accessories and Cables NI offers a variety of accessories and cables to use with your DAQ device. Refer to Appendix A, NI 6236 Device Information, or ni.com for more information. NI 6236 User Manual 1-2 ni.
2 DAQ System Overview Figure 2-1 shows a typical DAQ system, which includes sensors, transducers, cables that connect the various devices to the accessories, the M Series device, programming software, and PC. The following sections cover the components of a typical DAQ system. Sensors and Transducers Cables and Accessories DAQ Hardware DAQ Software Personal Computer Figure 2-1.
Chapter 2 DAQ System Overview Isolation Barrier Analog Input I/O Connector Analog Output Digital Routing and Clock Generation Digital Isolators Counters Bus Interface Bus PFI/Static DI RTSI PFI/Static DO Figure 2-2. General NI 6236 Block Diagram DAQ-STC2 The DAQ-STC2 implements a high-performance digital engine for NI 6236 data acquisition hardware.
Chapter 2 DAQ System Overview Calibration Circuitry The M Series analog inputs and outputs can self-calibrate to correct gain and offset errors. You can calibrate the device to minimize AI and AO errors caused by time and temperature drift at run time. No external circuitry is necessary; an internal reference ensures high accuracy and stability over time and temperature changes. Factory-calibration constants are permanently stored in an onboard EEPROM and cannot be modified.
Chapter 2 DAQ System Overview Cables and Accessories NI offers a variety of products to use with NI 6236 devices, including cables, connector blocks, and other accessories, as follows: • Cables and cable assemblies – Shielded – Unshielded ribbon • Screw terminal connector blocks, shielded and unshielded • RTSI bus cables For more specific information about these products, refer to ni.com.
Chapter 2 DAQ System Overview Programming Devices in Software National Instruments measurement devices are packaged with NI-DAQ driver software, an extensive library of functions and VIs you can call from your application software, such as LabVIEW or LabWindows/CVI, to program all the features of your NI measurement devices. Driver software has an application programming interface (API), which is a library of VIs, functions, classes, attributes, and properties for creating applications for your device.
3 Connector Information The I/O Connector Signal Descriptions and RTSI Connector Pinout sections contain information about M Series connectors. Refer to Appendix A, NI 6236 Device Information, for device I/O connector pinouts. I/O Connector Signal Descriptions Table 3-1 describes the signals found on the I/O connectors. Not all signals are available on all devices. Table 3-1.
Chapter 3 Connector Information Table 3-1. I/O Connector Signals (Continued) Signal Name AO GND Reference Direction Description — — Analog Output Ground—AO GND is the reference for AO <0..3>. All three ground references—AI GND, AO GND, and D GND—are connected on the device. Note: AI GND, AO GND, and D GND are isolated from earth ground and chassis ground. D GND — — Digital Ground—D GND supplies the reference for input PFI <0..5>/P0.<0..5> and output PFI <6..9>/P1.<0..3>.
4 Analog Input Figure 4-1 shows the analog input circuitry of NI 6236 devices. Isolation Barrier I/O Connector AI <0..3>+ Mux NI-PGIA ADC Digital Isolators AI FIFO AI Data AI <0..3>– Input Range Selection AI GND Figure 4-1. NI 6236 Analog Input Circuitry Analog Input Circuitry I/O Connector You can connect analog input signals to the M Series device through the I/O connector.
Chapter 4 Analog Input M Series devices use the NI-PGIA to deliver high accuracy even when sampling multiple channels with small input ranges at fast rates. M Series devices can sample channels in any order at the maximum conversion rate, and you can individually program each channel in a sample with a different input range. A/D Converter The analog-to-digital converter (ADC) digitizes the AI signal by converting the analog voltage into a digital number.
Chapter 4 Analog Input M Series devices use a calibration method that requires some codes (typically about 5% of the codes) to lie outside of the specified range. This calibration method improves absolute accuracy, but it increases the nominal resolution of input ranges by about 5% over what the previous formulas would indicate. Table 4-1 shows the input range and resolution supported by the NI 6236 devices. Table 4-1.
Chapter 4 Analog Input Isolation Barrier AI + + AI – – Vcm AI GND AI GND Figure 4-2. Analog Current Input Connection Method 1 Method 2 Method 2, shown in Figure 4-3, ties the AI – input to AI GND. When measuring current up to 20 mA, this type of connection ensures that the voltage level on both the positive and negative side are within the common-mode input range for NI 6236 devices. Isolation Barrier AI + + AI – – AI GND Figure 4-3.
Chapter 4 Analog Input Note that AI GND must always be connected to the ground-reference point of the circuit being measured. AI GND is the ground-reference point that NI 6236 devices use to reference their isolated front end. The NI 6236 is an isolated device with isolation ratings up to 60 VDC/30 Vrms. This allows for current measurement at high voltage levels provided that the common-mode input range requirement is satisfied.
Chapter 4 Analog Input Instrumentation Amplifier Iin+ Current Sense Resistor Iin– + PGIA Vm Measured Voltage AI GND – Vm = Iin • R × Gain Figure 4-5. NI 6236 PGIA Analog input ground-reference setting refers to the reference that the PGIA measures against.
Chapter 4 Analog Input Caution The maximum input voltage and current ratings of AI signals with respect to AI GND (and for differential signals with respect to each other) and earth/chassis ground are listed in the Maximum Working Voltage section of the NI 6236 Specifications. Exceeding the maximum input voltage or maximum working voltage of AI signals distorts the measurement results. Exceeding the maximum input voltage or maximum working voltage rating also can damage the device and the computer.
Chapter 4 Analog Input Multichannel Scanning Considerations M Series devices can scan multiple channels at high rates and digitize the signals accurately. However, you should consider several issues when designing your measurement system to ensure the high accuracy of your measurements. In multichannel scanning applications, accuracy is affected by settling time.
Chapter 4 Analog Input For example, suppose all channels in a system use a –20 to 20 mA input range. The signals on channels 0 and 2 vary between 18 and 19 mA. The signals on channels 1 and 3 vary between –18 and 0 mA. Scanning channels in the order 0, 2, 1, 3 will produce more accurate results than scanning channels in the order 0, 1, 2, 3. Avoid Scanning Faster Than Necessary Designing your system to scan at slower speeds gives the PGIA more time to settle to a more accurate level.
Chapter 4 Analog Input Analog Input Data Acquisition Methods When performing analog input measurements, you either can perform software-timed or hardware-timed acquisitions. Hardware-timed acquisitions can be buffered or non-buffered. Software-Timed Acquisitions With a software-timed acquisition, software controls the rate of the acquisition. Software sends a separate command to the hardware to initiate each ADC conversion.
Chapter 4 Analog Input samples has been written out, the generation stops. If you use a reference trigger, you must use finite sample mode. Continuous acquisition refers to the acquisition of an unspecified number of samples. Instead of acquiring a set number of data samples and stopping, a continuous acquisition continues until you stop the operation. Continuous acquisition is also referred to as double-buffered or circular-buffered acquisition.
Chapter 4 Analog Input mainly to AI signal routing to the device, although they also apply to signal routing in general. Minimize noise pickup and maximize measurement accuracy by using individually shielded, twisted-pair wires to connect AI signals to the device. With this type of wire, the signals attached to the positive and negative input channels are twisted together and then covered with a shield. You then connect this shield only at one point to the signal source ground.
Chapter 4 Analog Input M Series devices use ai/SampleClock and ai/ConvertClock to perform interval sampling. As Figure 4-8 shows, ai/SampleClock controls the sample period, which is determined by the following equation: 1/Sample Period = Sample Rate Channel 0 Channel 1 Convert Period Sample Period Figure 4-8.
Chapter 4 Analog Input ai/StartTrigger ai/SampleClock ai/ConvertClock Sample Counter 4 3 2 1 0 Figure 4-9. Posttriggered Data Acquisition Example Pretriggered data acquisition allows you to view data that is acquired before the trigger of interest, in addition to data acquired after the trigger. Figure 4-10 shows a typical pretriggered DAQ sequence. ai/StartTrigger can be either a hardware or software signal.
Chapter 4 Analog Input NI 6236 devices feature the following analog input timing signals. • AI Sample Clock Signal • AI Sample Clock Timebase Signal • AI Convert Clock Signal • AI Convert Clock Timebase Signal • AI Hold Complete Event Signal • AI Start Trigger Signal • AI Reference Trigger Signal • AI Pause Trigger Signal AI Sample Clock Signal Use the AI Sample Clock (ai/SampleClock) signal to initiate a set of measurements.
Chapter 4 Analog Input Note Refer to the NI 6236 Specifications for the minimum allowable pulse width and the propagation delay of PFI <0..5>. Routing AI Sample Clock Signal to an Output Terminal You can route ai/SampleClock out to any output PFI <6..9> or RTSI <0..7> terminal. This pulse is always active high. You can specify the output to have one of two behaviors. With the pulse behavior, your DAQ device briefly pulses the PFI terminal once for every occurrence of ai/SampleClock.
Chapter 4 Analog Input Figure 4-11 shows the relationship of ai/SampleClock to ai/StartTrigger. ai/SampleClockTimebase ai/StartTrigger ai/SampleClock Delay From Start Trigger Figure 4-11. ai/SampleClock and ai/StartTrigger AI Sample Clock Timebase Signal You can route any of the following signals to be the AI Sample Clock Timebase (ai/SampleClockTimebase) signal: • 20 MHz Timebase • 100 kHz Timebase • PXI_CLK10 • RTSI <0..7> • Input PFI <0..
Chapter 4 Analog Input With NI-DAQmx, the driver will choose the fastest conversion rate possible based on the speed of the A/D converter and add 10 µs of padding between each channel to allow for adequate settling time. This scheme enables the channels to approximate simultaneous sampling and still allow for adequate settling time.
Chapter 4 Analog Input PFI <0..5> terminals are fixed inputs. PFI <6..9> terminals are fixed outputs. Using a Delay from Sample Clock to Convert Clock When using an internally generated ai/ConvertClock, you also can specify a configurable delay from ai/SampleClock to the first ai/ConvertClock pulse within the sample. By default, this delay is three ticks of ai/ConvertClockTimebase. Figure 4-12 shows the relationship of ai/SampleClock to ai/ConvertClock.
Chapter 4 Analog Input It is also possible to use a single external signal to drive both ai/SampleClock and ai/ConvertClock at the same time. In this mode, each tick of the external clock will cause a conversion on the ADC. Figure 4-13 shows this timing relationship. ai/SampleClock ai/ConvertClock Channel Measured 0 1 2 3 0 1 2 3 0 1 … Sample #1 Sample #2 Sample #3 • One External Signal Driving Both Clocks Figure 4-13.
Chapter 4 Analog Input AI Start Trigger Signal Use the AI Start Trigger (ai/StartTrigger) signal to begin a measurement acquisition. A measurement acquisition consists of one or more samples. If you do not use triggers, begin a measurement with a software command.
Chapter 4 Analog Input complete description of the use of ai/StartTrigger and ai/ReferenceTrigger in a pretriggered DAQ operation. AI Reference Trigger Signal Use a reference trigger (ai/ReferenceTrigger) signal to stop a measurement acquisition. To use a reference trigger, specify a buffer of finite size and a number of pretrigger samples (samples that occur before the reference trigger).
Chapter 4 Analog Input Using a Digital Source To use ai/ReferenceTrigger with a digital source, specify a source and an edge. The source can be any of the following signals: • Input PFI <0..5> • RTSI <0..7> • PXI_STAR The source also can be one of several internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information.
Chapter 4 Analog Input Routing AI Pause Trigger Signal to an Output Terminal You can route ai/PauseTrigger out to RTSI <0..7>. Note Pause triggers are only sensitive to the level of the source, not the edge. Getting Started with AI Applications in Software You can use the M Series device in the following analog input applications.
5 Analog Output NI 6236 devices have four AO channels that are controlled by a single clock and are capable of waveform generation. Figure 5-1 shows the analog output circuitry of NI 6236 devices. AO 0 DAC0 AO 1 DAC1 Isolation Barrier Digital Isolators AO 2 DAC2 AO 3 DAC3 AO FIFO AO Data AO Sample Clock Figure 5-1. NI 6236 Analog Output Circuitry Analog Output Circuitry DACs Digital-to-analog converters (DACs) convert digital codes to analog voltages.
Chapter 5 Analog Output AO FIFO The AO FIFO enables analog output waveform generation. It is a first-in-first-out (FIFO) memory buffer between the computer and the DACs. It allows you to download the points of a waveform to your M Series device without host computer interaction. AO Sample Clock The AO Sample Clock signal reads a sample from the DAC FIFO and generates the AO voltage.
Chapter 5 Analog Output Hardware-Timed Generations With a hardware-timed generation, a digital hardware signal controls the rate of the generation. This signal can be generated internally on your device or provided externally. Hardware-timed generations have several advantages over software-timed acquisitions: • The time between samples can be much shorter. • The timing between samples can be deterministic. • Hardware-timed acquisitions can use hardware triggering.
Chapter 5 Analog Output Regeneration is the repetition of the data that is already in the buffer. Standard regeneration is when data from the PC buffer is continually downloaded to the FIFO to be written out. New data can be written to the PC buffer at any time without disrupting the output. With FIFO regeneration, the entire buffer is downloaded to the FIFO and regenerated from there. After the data is downloaded, new data cannot be written to the FIFO.
Chapter 5 AO 0 + Load Analog Output Channel 0 V OUT – Digital Isolators – V OUT + Load AO 1 + AO 2 Channel 1 Isolation Barrier I/O Connector Load Channel 2 V OUT – – Load V OUT + AO 3 Channel 3 AO GND Figure 5-2. Analog Output Connections Analog Output Timing Signals Figure 5-3 summarizes all of the timing options provided by the analog output timing engine.
Chapter 5 Analog Output PFI, RTSI PXI_STAR PFI, RTSI Ctr n Internal Output ao/Sample Clock Timebase PXI_STAR ao/Sample Clock Programmable Clock Divider 20 MHz Timebase 100 kHz Timebase PXI_CLK10 Figure 5-3. Analog Output Timing Options NI 6236 devices feature the following AO (waveform generation) timing signals.
Chapter 5 Analog Output The source also can be one of several internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information. You also can specify whether the waveform generation begins on the rising edge or falling edge of ao/StartTrigger. Routing AO Start Trigger Signal to an Output Terminal You can route ao/StartTrigger out to any output PFI <6..9> or RTSI <0..7> terminal. The output is an active high pulse. PFI <0..
Chapter 5 Analog Output deasserted and another edge of the sample clock is received, as shown in Figure 5-5. Pause Trigger Sample Clock Figure 5-5. ao/PauseTrigger with Other Signal Source Using a Digital Source To use ao/PauseTrigger, specify a source and a polarity. The source can be one of the following signals: • Input PFI <0..5> • RTSI <0..7> • PXI_STAR The source also can be one of several other internal signals on your DAQ device.
Chapter 5 Analog Output Using an Internal Source One of the following internal signals can drive ao/SampleClock. • AO Sample Clock Timebase (divided down) • Counter n Internal Output A programmable internal counter divides down the AO Sample Clock Timebase signal. Using an External Source Use one of the following external signals as the source of ao/SampleClock: • Input PFI <0..5> • RTSI <0..
Chapter 5 Analog Output Figure 5-6 shows the relationship of ao/SampleClock to ao/StartTrigger. ao/SampleClockTimebase ao/StartTrigger ao/SampleClock Delay From Start Trigger Figure 5-6. ao/SampleClock and ao/StartTrigger AO Sample Clock Timebase Signal The AO Sample Clock Timebase (ao/SampleClockTimebase) signal is divided down to provide a source for ao/SampleClock.
Chapter 5 Analog Output Getting Started with AO Applications in Software You can use an M Series device in the following analog output applications. • Single-point (on-demand) generation • Finite generation • Continuous generation • Waveform generation You can perform these generations through programmed I/O, interrupt, or DMA data transfer mechanisms. Some of the applications also use start triggers and pause triggers.
Digital Input and Output 6 NI 6236 devices have six static digital input lines, P0.<0..5>. These lines also can be used as PFI inputs. NI 6236 devices have four static digital output lines, P1.<0..3>. These lines also can be used as PFI output. By default the digital output lines are disabled (high impedance) on power up. Software can enable or disable the entire port (software cannot enable individual lines).
Chapter 6 Digital Input and Output Programmable Power-Up States By default, the digital output lines (P1.<0..3>/PFI <6..9>) are disabled (high impedance) at power up. Software can configure the board to power up with the entire port enabled or disabled; you cannot enable individual lines. If the port powers up enabled, you also can configure each line individually to power up as 1 or 0. Refer to the NI-DAQmx Help or the LabVIEW 8.
Chapter 6 Digital Input and Output +5 V Isolation Barrier LED P1.<0..3> Digital Isolators TTL Signal P0.<0..5> +5 V Switch I/O Connector D GND M Series Isolated Device Note: All voltages referenced to D GND Figure 6-1. Digital I/O Connections Caution Exceeding the maximum input voltage or maximum working voltage ratings, which are listed in the NI 6236 Specifications, can damage the DAQ device and the computer. NI is not liable for any damage resulting from such signal connections.
7 Counters NI 6236 devices have two general-purpose 32-bit counter/timers and one frequency generator, as shown in Figure 7-1. The general-purpose counter/timers can be used for many measurement and pulse generation applications.
Chapter 7 Counters The counters have seven input signals, although in most applications only a few inputs are used. For information about connecting counter signals, refer to the Default Counter Terminals section. Counter Input Applications Counting Edges In edge counting applications, the counter counts edges on its Source after the counter is armed. You can configure the counter to count rising or falling edges on its Source input. You also can control the direction of counting (up or down).
Chapter 7 Counters Counter Armed Pause Trigger (Pause When Low) SOURCE Counter Value 0 0 1 2 3 4 5 Figure 7-3. Single Point (On-Demand) Edge Counting with Pause Trigger Buffered (Sample Clock) Edge Counting With buffered edge counting (edge counting using a sample clock), the counter counts the number of edges on the Source input after the counter is armed. The value of the counter is sampled on each active edge of a sample clock. A DMA controller transfers the sampled values to host memory.
Chapter 7 Counters Non-Cumulative Buffered Edge Counting Non-cumulative edge counting is similar to buffered (sample clock) edge counting. However, the counter resets after each active edge of the Sample Clock. You can route the Sample Clock to the Gate input of the counter. Figure 7-5 shows an example of non-cumulative buffered edge counting. Counter Armed Sample Clock (Sample on Rising Edge) SOURCE Counter Value 0 1 2 1 2 3 2 Buffer 1 2 2 3 3 1 2 3 3 Figure 7-5.
Chapter 7 Counters Pulse-Width Measurement In pulse-width measurements, the counter measures the width of a pulse on its Gate input signal. You can configure the counter to measure the width of high pulses or low pulses on the Gate signal. You can route an internal or external periodic clock signal (with a known period) to the Source input of the counter. The counter counts the number of rising (or falling) edges on the Source signal while the pulse on the Gate signal is active.
Chapter 7 Counters The counter counts the number of edges on the Source input while the Gate input remains active. On each trailing edge of the Gate signal, the counter stores the count in a hardware save register. A DMA controller transfers the stored values to host memory. Figure 7-7 shows an example of a buffered pulse-width measurement. GATE SOURCE 0 Counter Value 1 2 3 1 2 3 Buffer 3 3 2 2 Figure 7-7.
Chapter 7 Counters Single Period Measurement With single period measurement, the counter counts the number of rising (or falling) edges on the Source input occurring between two active edges of the Gate input. On the second active edge of the Gate input, the counter stores the count in a hardware save register and ignores other edges on the Gate and Source inputs. Software then can read the stored count. Figure 7-8 shows an example of a single period measurement.
Chapter 7 Counters Counter Armed GATE SOURCE Counter Value 1 2 1 2 2 2 (Discard) 3 1 2 3 2 (Discard) 3 1 3 2 (Discard) 3 Buffer 3 3 Figure 7-9. Buffered Period Measurement Note that if you are using an external signal as the Source, at least one Source pulse should occur between each active edge of the Gate signal. This condition ensures that correct values are returned by the counter. If this condition is not met, consider using duplicate count prevention.
Chapter 7 Counters Buffered Semi-Period Measurement In buffered semi-period measurement, on each edge of the Gate signal, the counter stores the count in a hardware save register. A DMA controller transfers the stored values to host memory. The counter begins counting when it is armed. The arm usually occurs between edges on the Gate input. So the first value stored in the hardware save register does not reflect a full semi-period of the Gate input.
Chapter 7 Counters You can route the signal to measure (F1) to the Gate of a counter. You can route a known timebase (Ft) to the Source of the counter. The known timebase can be 80MHzTimebase. For signals that might be slower than 0.02 Hz, use a slower known timebase. You can configure the counter to measure one period of the gate signal. The frequency of F1 is the inverse of the period. Figure 7-11 illustrates this method.
Chapter 7 T1 F1 Gate Ft Source Counters Intervals Measured T2 … TK F1 1 2 ...N11... ...N2 … 1... ...NK Ft Buffered Period Measurement Average Period of F1 = Frequency of F1 = N1 + N2 + …NK K × 1 Ft K × Ft N1 + N2 + …NK Figure 7-12. Method 1b Method 2—Measure High Frequency with Two Counters In this method, you measure one pulse of a known width using your signal and derive the frequency of your signal from the result. This method is good for high frequency signals.
Chapter 7 Counters Width of Pulse (T) Pulse Pulse Gate 1 F1 Source 2 N … F1 Width of T = Pulse Pulse-Width Measurement N F1 Frequency of F1 = N T Figure 7-13. Method 2 Method 3—Measure Large Range of Frequencies Using Two Counters By using two counters, you can accurately measure a signal that might be high or low frequency. This technique is called reciprocal frequency measurement. In this method, you generate a long pulse using the signal to measure.
Chapter 7 Signal to Measure (F1) SOURCE Counters OUT COUNTER 0 Signal of Known Frequency (F2) SOURCE OUT COUNTER 1 GATE CTR_0_SOURCE (Signal to Measure) CTR_0_OUT (CTR_1_GATE) 0 1 2 3 … N Interval to Measure CTR_1_SOURCE Figure 7-14. Method 3 Then route the Counter 0 Internal Output signal to the Gate input of Counter 1. You can route a signal of known frequency (F2) to the Counter 1 Source input. F2 can be 80MHzTimebase. For signals that might be slower than 0.
Chapter 7 Counters 80 MHz Timebase. Your measurement may return 1600 ± 1 cycles depending on the phase of the signal with respect to the timebase. As your frequency becomes larger, this error of ±1 cycle becomes more significant; Table 7-1 illustrates this point. Table 7-1.
Chapter 7 Counters Table 7-2 summarizes some of the differences in methods of measuring frequency. Table 7-2. Frequency Measurement Method Comparison Method Number of Counters Used Number of Measurement s Returned Measures High Frequency Signals Accurately Measures Low Frequency Signals Accurately 1 1 1 Poor Good 1b 1 Many Fair Good 2 1 or 2 1 Good Poor 3 2 1 Good Good For information about connecting counter signals, refer to the Default Counter Terminals section.
Chapter 7 Counters increment occurs on the rising edge of channel A. When channel B leads channel A, the decrement occurs on the falling edge of channel A. Ch A Ch B Counter Value 5 6 7 7 5 6 Figure 7-15. X1 Encoding X2 Encoding The same behavior holds for X2 encoding except the counter increments or decrements on each edge of channel A, depending on which channel leads the other. Each cycle results in two increments or decrements, as shown in Figure 7-16.
Chapter 7 Counters quadrature cycle. You can program this reload to occur in any one of the four phases in a quadrature cycle. Channel Z behavior—when it goes high and how long it stays high—differs with quadrature encoder designs. You must refer to the documentation for your quadrature encoder to obtain timing of channel Z with respect to channels A and B. You must then ensure that channel Z is high during at least a portion of the phase you specify for reload.
Chapter 7 Counters Ch A Ch B Counter Value 2 3 4 5 4 3 4 Figure 7-19. Measurements Using Two Pulse Encoders For information about connecting counter signals, refer to the Default Counter Terminals section. Two-Signal Edge-Separation Measurement Two-signal edge-separation measurement is similar to pulse-width measurement, except that there are two measurement signals—Aux and Gate. An active edge on the Aux input starts the counting and an active edge on the Gate input stops the counting.
Chapter 7 Counters Counter Armed Measured Interval AUX GATE SOURCE Counter Value 0 0 0 0 1 2 3 4 5 6 7 8 8 8 8 HW Save Register Figure 7-20. Single Two-Signal Edge-Separation Measurement Buffered Two-Signal Edge-Separation Measurement Buffered and single two-signal edge-separation measurements are similar, but buffered measurement measures multiple intervals.
Chapter 7 Counters Counter Output Applications Simple Pulse Generation Single Pulse Generation The counter can output a single pulse. The pulse appears on the Counter n Internal Output signal of the counter. You can specify a delay from when the counter is armed to the beginning of the pulse. The delay is measured in terms of a number of active edges of the Source input. You can specify a pulse width. The pulse width is also measured in terms of a number of active edges of the Source input.
Chapter 7 Counters GATE (Start Trigger) SOURCE OUT Figure 7-23. Single Pulse Generation with Start Trigger Retriggerable Single Pulse Generation The counter can output a single pulse in response to each pulse on a hardware Start Trigger signal. The pulses appear on the Counter n Internal Output signal of the counter. You can route the Start Trigger signal to the Gate input of the counter. You can specify a delay from the Start Trigger to the beginning of each pulse. You also can specify the pulse width.
Chapter 7 Counters Pulse Train Generation Continuous Pulse Train Generation This function generates a train of pulses with programmable frequency and duty cycle. The pulses appear on the Counter n Internal Output signal of the counter. You can specify a delay from when the counter is armed to the beginning of the pulse train. The delay is measured in terms of a number of active edges of the Source input. You specify the high and low pulse widths of the output signal.
Chapter 7 Counters Frequency Generation You can generate a frequency by using a counter in pulse train generation mode or by using the frequency generator circuit. Using the Frequency Generator The frequency generator can output a square wave at many different frequencies. The frequency generator is independent of the two general-purpose 32-bit counter/timer modules on M Series devices. Figure 7-26 shows a block diagram of the frequency generator.
Chapter 7 Counters Frequency Output can be routed out to any output PFI <6..9> or RTSI <0..7> terminal. All PFI terminals are set to high-impedance at startup. In software, program the frequency generator as you would program one of the counters for pulse train generation. For information about connecting counter signals, refer to the Default Counter Terminals section. Frequency Division The counters can generate a signal with a frequency that is a fraction of an input signal.
Chapter 7 Counters frequency of the system. Figure 7-28 shows an example of pulse generation for ETS; the delay from the trigger to the pulse increases after each subsequent Gate active edge. GATE OUT D2 = D1 + ∆D D1 D3 = D1 + 2∆D Figure 7-28. Pulse Generation for ETS For information about connecting counter signals, refer to the Default Counter Terminals section. Counter Timing Signals M Series devices feature the following counter timing signals.
Chapter 7 Counters performing. Table 7-3 lists how this terminal is used in various applications. Table 7-3.
Chapter 7 Counters Counter n Gate Signal The Counter n Gate signal can perform many different operations depending on the application including starting and stopping the counter, and saving the counter contents. Routing a Signal to Counter n Gate Each counter has independent input selectors for the Counter n Gate signal. Any of the following signals can be routed to the Counter n Gate input. • RTSI <0..7> • Input PFI <0..
Chapter 7 Counters • ai/StartTrigger • PXI_STAR In addition, Counter 1 Internal Output, Counter 1 Gate, Counter 1 Source, or Counter 0 Gate can be routed to Counter 0 Aux. Counter 0 Internal Output, Counter 0 Gate, Counter 0 Source, or Counter 1 Gate can be routed to Counter 1 Aux. Some of these options may not be available in some driver software. Counter n A, Counter n B, and Counter n Z Signals Counter n B can control the direction of counting in edge counting applications.
Chapter 7 Counters waiting for the Gate signal when it is armed. Counter output operations can use the arm signal in addition to a start trigger. Software can arm a counter or configure counters to be armed on a hardware signal. Software calls this hardware signal the Arm Start Trigger. Internally, software routes the Arm Start Trigger to the Counter n HW Arm input of the counter. Routing Signals to Counter n HW Arm Input Any of the following signals can be routed to the Counter n HW Arm input.
Chapter 7 Counters Default Counter Terminals By default, NI-DAQmx routes the counter/timer inputs and outputs to the PFI pins, shown in Table 7-4. Table 7-4. NI 6236 Device Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Pin Number (Name) Port CTR 0 SRC 13 (PFI 0) P0.0 CTR 0 GATE 32 (PFI 1) P0.1 CTR 0 AUX 33 (PFI 2) P0.2 CTR 0 OUT 17 (PFI 6) P1.0 CTR 0 A 13 (PFI 0) P0.0 CTR 0 Z 32 (PFI 1) P0.1 CTR 0 B 33 (PFI 2) P0.2 CTR 1 SRC 15 (PFI 3) P0.
Chapter 7 Counters Counter Triggering Counters support three different triggering actions—arm start, start, and pause. Arm Start Trigger To begin any counter input or output function, you must first enable, or arm, the counter. Software can arm a counter or configure counters to be armed on a hardware signal. Software calls this hardware signal the Arm Start Trigger. Internally, software routes the Arm Start Trigger to the Counter n HW Arm input of the counter.
Chapter 7 Counters Other Counter Features Cascading Counters You can internally route the Counter n Internal Output and Counter n TC signal of each counter to the Gate inputs of the other counter. By cascading two counters together, you can effectively create a 64-bit counter. By cascading counters, you also can enable other applications.
Chapter 7 Counters The filter setting for each input can be configured independently. On power up, the filters are disabled. Figure 7-29 shows an example of a low to high transition on an input that has its filter set to 125 ns (N = 5). RTSI, PFI, or PXI_STAR Terminal Filter Clock (40 MHz) 1 1 2 3 4 1 2 3 4 5 Filtered input goes high when terminal is sampled high on five consecutive filter clocks. Filtered Input Figure 7-29.
Chapter 7 Counters Prescaling is intended to be used for frequency measurement where the measurement is made on a continuous, repetitive signal. The prescaling counter cannot be read; therefore, you cannot determine how many edges have occurred since the previous rollover. Prescaling can be used for event counting provided it is acceptable to have an error of up to seven (or one). Prescaling can be used when the counter Source is an external signal.
Chapter 7 Counters The counter synchronizes or samples the Gate signal with the Source signal, so the counter does not detect a rising edge in the Gate until the next Source pulse. In this example, the counter stores the values in the buffer on the first rising Source edge after the rising edge of Gate. The details of when exactly the counter synchronizes the Gate signal vary depending on the synchronization mode. Synchronization modes are described in the Synchronization Modes section.
Chapter 7 Counters Counter detects rising Gate edge. Counter value increments only one time for each Source pulse. Gate Source 80 MHz Timebase Counter Value 6 7 0 1 7 Buffer 0 7 Figure 7-33. Duplicate Count Prevention Example Even if the Source pulses are long, the counter increments only once for each Source pulse. Normally, the counter value and Counter n Internal Output signals change synchronously to the Source signal.
Chapter 7 Counters Enabling Duplicate Count Prevention in NI-DAQmx You can enable duplicate count prevention in NI-DAQmx by setting the Enable Duplicate Count Prevention attribute/property. For specific information about finding the Enable Duplicate Count Prevention attribute/property, refer to the help file for the API you are using. Synchronization Modes The 32-bit counter counts up or down synchronously with the Source signal.
Chapter 7 Counters 80 MHz Source Mode In 80 MHz source mode, the device synchronizes signals on the rising edge of the source, and counts on the following rising edge of the source, as shown in Figure 7-34. Source Synchronize Count Figure 7-34. 80 MHz Source Mode Other Internal Source Mode In other internal source mode, the device synchronizes signals on the falling edge of the source, and counts on the following rising edge of the source, as shown in Figure 7-35.
8 PFI NI 6236 devices have 10 Programmable Function Interface (PFI) signals—six input signals and four output signals. Each PFI <0..5>/P0.<0..5> can be configured as a timing input signal for AI or counter/timer functions or a static digital input. Each PFI input also has a programmable debouncing filter. Figure 8-1 shows the circuitry of one PFI input line. Each PFI line is similar. Isolation Barrier Static DI PFI <0..5>/P0.<0..
Chapter 8 PFI Isolation Barrier Timing Signals Digital Isolators Static DO Buffer I/O Protection Output Enable PFI <6..9>/P1.<0..3> Note: One output enable is shared by all digital output signals. Figure 8-2. NI 6236 PFI Output Circuitry When a terminal is used as a timing input or output signal, it is called PFI x (where x is an integer from 0 to 9). When a terminal is used as a static digital input or output, it is called P0.x or P1.x.
Chapter 8 PFI Exporting Timing Output Signals Using PFI Terminals You can route any of the following timing signals to any PFI <6..9> terminal. • AI Convert Clock* • AI Hold Complete Event • AI Reference Trigger • AI Sample Clock • AI Start Trigger • AO Sample Clock* • AO Start Trigger • Counter n Source • Counter n Gate • Counter n Internal Output • Frequency Output • PXI_STAR • RTSI <0..7> Note Signals with a * are inverted before being driven to a terminal.
Chapter 8 PFI I/O Connector PFI 0 PFI 2 PFI 0 Source PFI 2 Source D GND M Series Device Figure 8-3. PFI Input Signals Connections PFI Filters You can enable a programmable debouncing filter on each PFI, RTSI, or PXI_STAR signal. When the filters are enabled, your device samples the input on each rising edge of a filter clock. M Series devices use an onboard oscillator to generate the filter clock with a 40 MHz frequency. Note NI-DAQmx only supports filters on counter inputs.
Chapter 8 PFI Table 8-1. Filters Filter Setting N (Filter Clocks Needed to Pass Signal) Pulse Width Guaranteed to Pass Filter Pulse Width Guaranteed to Not Pass Filter 125 ns 5 125 ns 100 ns 6.425 µs 257 6.425 µs 6.400 µs 2.55 ms ~101,800 2.55 ms 2.54 ms Disabled — — — The filter setting for each input can be configured independently. On power up, the filters are disabled. Figure 8-4 shows an example of a low to high transition on an input that has its filter set to 125 ns (N = 5).
Chapter 8 PFI I/O Protection Each DI, DO, and PFI signal is protected against overvoltage, undervoltage, and overcurrent conditions as well as ESD events. However, you should avoid these fault conditions by following these guidelines. • Do not connect any digital output line to any external signal source, ground signal, or power supply. • Understand the current requirements of the load connected to the digital output lines. Do not exceed the specified current output limits of the digital outputs.
9 Isolation and Digital Isolators NI 6236 devices are isolated data acquisition devices. As shown in Figure 9-1, the analog input, analog output, PFI/static DI, and PFI/static DO are isolated from earth/chassis ground, , and are all referenced to the isolated ground, . The bus interface circuitry, RTSI, digital routing, and clock generation are all referenced to a non-isolated ground, .
Chapter 9 Isolation and Digital Isolators Connecting Digital I/O Signals section of Chapter 6, Digital Input and Output, and the Connecting PFI Input Signals section of Chapter 8, PFI, for more information. Digital Isolation The NI 6236 uses digital isolators. Unlike analog isolators, digital isolators do not introduce any analog error in the measurements taken by the device. The A/D converter, used for analog input, is on the isolated side of the device.
Chapter 9 Isolation and Digital Isolators These parasitic currents interact with parasitic and non-parasitic resistances causing voltage spikes. These voltage spikes are called common-mode noise, a noise source that travels in the ground and is therefore common to both the ground and any signal referenced to the ground, such as AI, AO, and digital signals. Common-mode noise appears at the harmonics of the switching power supply frequency and can corrupt measurements depending on the system setup.
10 Digital Routing and Clock Generation The digital routing circuitry has the following three main functions. • Manages the flow of data between the bus interface and the acquisition/generation sub-systems (analog input, analog output, digital I/O, and the counters). The digital routing circuitry uses FIFOs (if present) in each sub-system to ensure efficient data movement. • Routes timing and control signals.
Chapter 10 Digital Routing and Clock Generation 80 MHz Timebase The 80 MHz Timebase can be used as the Source input to the 32-bit general-purpose counter/timers. The 80 MHz Timebase can be generated from either of the following. • Onboard oscillator • External signal (by using the external reference clock) 20 MHz Timebase The 20 MHz Timebase normally generates many of the AI and AO timing signals. The 20 MHz Timebase also can be used as the Source input to the 32-bit general-purpose counter/timers.
Chapter 10 Digital Routing and Clock Generation 10 MHz Reference Clock The 10 MHz reference clock can be used to synchronize other devices to your M Series device. The 10 MHz reference clock can be routed to the RTSI <0..7> terminals. Other devices connected to the RTSI bus can use this signal as a clock input. The 10 MHz reference clock is generated by dividing down the onboard oscillator.
Chapter 10 Digital Routing and Clock Generation Many National Instruments DAQ, motion, vision, and CAN devices support RTSI. In a PCI system, the RTSI bus consists of the RTSI bus interface and a ribbon cable. The bus can route timing and trigger signals between several functions on as many as five DAQ, vision, motion, or CAN devices in the computer. In a PXI system, the RTSI bus consists of the RTSI bus interface and the PXI trigger signals on the PXI backplane.
Chapter 10 Digital Routing and Clock Generation Table 10-1. RTSI Signal Descriptions RTSI Bus Signal Terminal RTSI 7 34 RTSI 6 32 RTSI 5 30 RTSI 4 28 RTSI 3 26 RTSI 2 24 RTSI 1 22 RTSI 0 20 Not Connected. Do not connect signals to these terminals. 1–18 GND 19, 21, 23, 25, 27, 29, 31, 33 Note: RTSI <0..7> and GND are earth/chassis ground-referenced. They are not isolated. Using RTSI as Outputs RTSI <0..7> are bidirectional terminals.
Chapter 10 Digital Routing and Clock Generation Using RTSI Terminals as Timing Input Signals You can use RTSI terminals to route external timing signals to many different M Series functions. Each RTSI terminal can be routed to any of the following signals.
Chapter 10 Digital Routing and Clock Generation Table 10-2. Filters Filter Setting N (Filter Clocks Needed to Pass Signal) Pulse Width Guaranteed to Pass Filter Pulse Width Guaranteed to Not Pass Filter 125 ns 5 125 ns 100 ns 6.425 µs 257 6.425 µs 6.400 µs 2.55 ms ~101,800 2.55 ms 2.54 ms Disabled — — — The filter setting for each input can be configured independently. On power up, the filters are disabled.
Chapter 10 Digital Routing and Clock Generation PXI Clock and Trigger Signals Note PXI clock and trigger signals are only available on PXI devices. Other devices use RTSI. PXI_CLK10 PXI_CLK10 is a common low-skew 10 MHz clock reference clock for synchronization of multiple modules in a PXI measurement or control system. The PXI backplane is responsible for generating PXI_CLK10 independently to each peripheral slot in a PXI chassis.
Chapter 10 Digital Routing and Clock Generation An M Series device is not a Star Trigger controller. An M Series device may be used in the first peripheral slot of a PXI system, but the system will not be able to use the Star Trigger feature. PXI_STAR Filters You can enable a programmable debouncing filter on each PFI, RTSI, or PXI_STAR signal. When the filters are enabled, your device samples the input on each rising edge of a filter clock.
Chapter 10 Digital Routing and Clock Generation The filter setting for each input can be configured independently. On power up, the filters are disabled. Figure 10-4 shows an example of a low to high transition on an input that has its filter set to 125 ns (N = 5). RTSI, PFI, or PXI_STAR Terminal Filter Clock (40 MHz) 1 1 2 3 4 1 2 3 4 5 Filtered input goes high when terminal is sampled high on five consecutive filter clocks. Filtered Input Figure 10-4.
11 Bus Interface The bus interface circuitry of NI 6236 devices efficiently moves data between host memory and the measurement and acquisition circuits. NI 6236 devices are available for the following platforms. • PCI • PXI NI 6236 devices are jumperless for complete plug-and-play operation. The operating system automatically assigns the base address, interrupt levels, and other resources. NI 6236 devices incorporate PCI-MITE technology to implement a high-performance PCI interface.
Chapter 11 Bus Interface Each DMA controller supports packing and unpacking of data through the FIFOs to connect different size devices and optimize PCI bus utilization and automatically handles unaligned memory buffers. PXI Considerations Note PXI clock and trigger signals are only available on PXI devices. Other devices use RTSI.
Chapter 11 Bus Interface Using PXI with CompactPCI Using PXI-compatible products with standard CompactPCI products is an important feature provided by PXI Hardware Specification Revision 2.1. If you use a PXI-compatible plug-in module in a standard CompactPCI chassis, you cannot use PXI-specific functions, but you can still use the basic plug-in device functions. For example, the RTSI bus on a PXI M Series device is available in a PXI chassis, but not in a CompactPCI chassis.
Chapter 11 Bus Interface Interrupt Request (IRQ) IRQ transfers rely on the CPU to service data transfer requests. The device notifies the CPU when it is ready to transfer data. The data transfer speed is tightly coupled to the rate at which the CPU can service the interrupt requests. If you are using interrupts to transfer data at a rate faster than the rate the CPU can service the interrupts, your systems may start to freeze.
12 Triggering A trigger is a signal that causes an action, such as starting or stopping the acquisition of data. When you configure a trigger, you must decide how you want to produce the trigger and the action you want the trigger to cause. NI 6236 devices support internal software triggering, as well as external digital triggering.
Chapter 12 Triggering You also can program your DAQ device to perform an action in response to a trigger from a digital source. The action can affect the following. NI 6236 User Manual • Analog input acquisition • Analog output generation • Counter behavior 12-2 ni.
A NI 6236 Device Information This appendix contains device pinouts, specifications, cable and accessory choices, and other information for the NI 6236 M Series devices. To obtain documentation for devices not listed here, refer to ni.com/manuals. NI 6236 Pinout Figure A-1 shows the pinout of the NI 6236. For a detailed description of each signal, refer to the I/O Connector Signal Descriptions section of Chapter 3, Connector Information.
Appendix A NI 6236 Device Information AI 0+/CAL+ AI 1– AI GND AI 2+ AI 3– AI GND AO 0 AO GND NC AO 2 AO GND NC PFI 1/P0.1 (Input) PFI 2/P0.2 (Input) PFI 4/P0.4 (Input) PFI 5/P0.5 (Input) PFI 7/P1.1 (Output) PFI 8/P1.2 (Output) 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 AI 0– AI GND AI 1+ AI 2– AI GND AI 3+ AO GND CAL– AO 1 AO GND NC AO 3 PFI 0/P0.0 (Input) D GND PFI 3/P0.3 (Input) D GND PFI 6/P1.0 (Output) D GND PFI 9/P1.
Appendix A NI 6236 Device Information Table A-1. NI 6236 Device Default NI-DAQmx Counter/Timer Pins (Continued) Counter/Timer Signal Default Pin Number (Name) Port CTR 1 OUT 36 (PFI 7) P1.1 CTR 1 A 15 (PFI 3) P0.3 CTR 1 Z 34 (PFI 4) P0.4 CTR 1 B 35 (PFI 5) P0.5 FREQ OUT 37 (PFI 8) P1.2 Note For more information about default NI-DAQmx counter inputs, refer to Connecting Counter Signals in the NI-DAQmx Help or the LabVIEW 8.x Help.
Appendix A NI 6236 Device Information RTSI Use RTSI bus cables to connect timing and synchronization signals among PCI devices, such as M Series, E Series, CAN, and other measurement, vision, and motion devices. Since PXI devices use PXI backplane signals for timing and synchronization, no cables are required.
B Troubleshooting This section contains some common questions about M Series devices. If your questions are not answered here, refer to the National Instruments KnowledgeBase at ni.com/kb. It contains thousands of documents that answer frequently asked questions about NI products. Analog Input I am seeing crosstalk or ghost current when sampling multiple channels.
Appendix B Troubleshooting reference the signal to the same ground level as the device reference. There are various methods of achieving this reference while maintaining a high common-mode rejection ratio (CMRR). These methods are outlined in the Connecting Analog Current Input Signals section of Chapter 4, Analog Input.
Appendix B Troubleshooting changes. You can build a lowpass deglitching filter to remove some of these glitches, depending on the frequency and nature of the output signal. Visit ni.com/support for more information about minimizing glitches. Counters When multiple sample clocks on my buffered counter measurement occur before consecutive edges on my source, I see weird behavior.
Technical Support and Professional Services C Visit the following sections of the National Instruments Web site at ni.com for technical support and professional services: • Support—Online technical support resources at ni.
Appendix C Technical Support and Professional Services • Calibration Certificate—If your product supports calibration, you can obtain the calibration certificate for your product at ni.com/calibration. If you searched ni.com and could not find the answers you need, contact your local office or NI corporate headquarters. Phone numbers for our worldwide offices are listed at the front of this manual. You also can visit the Worldwide Offices section of ni.
Glossary Symbols % Percent. + Positive of, or plus. – Negative of, or minus. ± Plus or minus. < Less than. > Greater than. ≤ Less than or equal to. ≥ Greater than or equal to. / Per. º Degree. Ω Ohm. A A Amperes—the unit of electric current. A/D Analog-to-Digital. Most often used as A/D converter. AC Alternating current. accuracy A measure of the capability of an instrument or sensor to faithfully indicate the value of the measured signal.
Glossary AI 1. Analog input. 2. Analog input channel signal. AI GND Analog input ground signal. AI SENSE Analog input sense signal. analog A signal whose amplitude can have a continuous range of values. analog input signal An input signal that varies smoothly over a continuous range of values, rather than in discrete steps. analog output signal An output signal that varies smoothly over a continuous range of values, rather than in discrete steps.
Glossary ASIC Application-specific integrated circuit—A proprietary semiconductor component designed and manufactured to perform a set of specific functions for a specific customer. asynchronous 1. Hardware—A property of an event that occurs at an arbitrary time, without synchronization to a reference clock. 2. Software—A property of a function that begins an operation and returns prior to the completion or termination of the operation. B b Bit—One binary digit, either 0 or 1.
Glossary calibrator A precise, traceable signal source used to calibrate instruments. cascading Process of extending the counting range of a counter chip by connecting to the next higher counter. CE European emissions control standard. channel Pin or wire lead to which you apply or from which you read the analog or digital signal. For digital signals, you group channels to form ports. Ports usually consist of either four or eight digital channels.
Glossary counter 1. Software. A memory location used to store a count of certain occurrences. 2. Hardware. A circuit that counts events. When it refers to an instrument, it refers to a frequency counter. counter/timer A circuit that counts external pulses or clock pulses (timing). D D GND Digital ground signal. D-SUB connector A serial connector.
Glossary data transfer A technique for moving digital data from one system to another. Options for data transfer are DMA, interrupt, and programmed I/O. For programmed I/O transfers, the CPU in the PC reads data from the DAQ device whenever the CPU receives a software signal to acquire a single data point. Interrupt-based data transfers occur when the DAQ device sends an interrupt to the CPU, telling the CPU to read the acquired data from the DAQ device.
Glossary digital isolator Provides voltage isolation between its input and output. digital signal A representation of information by a set of discrete values according to a prescribed law. These values are represented by numbers. digital trigger A TTL level signal having two discrete levels—a high and a low level. DIO Digital input/output.
Glossary F FIFO First-In-First-Out memory buffer—A data buffering technique that functions like a shift register where the oldest values (first in) come out first. Many DAQ products and instruments use FIFOs to buffer digital data from an A/D converter, or to buffer the data before or after bus transmission. The first data stored is the first data sent to the acceptor. FIFOs are often used on DAQ devices to temporarily store incoming or outgoing data until that data can be retrieved or output.
Glossary function 1. A built-in execution element, comparable to an operator, function, or statement in a conventional language. 2. A set of software instructions executed by a single line of code that may have input and/or output parameters and returns a value when executed. G glitch An unwanted signal excursion of short duration that is usually unavoidable. GND See ground. ground 1. A pin. 2. An electrically neutral wire that has the same potential as the surrounding earth.
Glossary in. Inch or inches. instrument driver A set of high-level software functions that controls a specific GPIB, VXI, or RS232 programmable instrument or a specific plug-in DAQ device. Instrument drivers are available in several forms, ranging from a function callable language to a virtual instrument (VI) in LabVIEW. instrumentation amplifier A circuit whose output voltage with respect to ground is proportional to the difference between the voltages at its two inputs.
Glossary K kHz Kilohertz—A unit of frequency; 1 kHz = 103 = 1,000 Hz. kS 1,000 samples. L LabVIEW A graphical programming language. LED Light-Emitting Diode—A semiconductor light source. lowpass filter A filter that passes signals below a cutoff frequency while blocking signals above that frequency. LSB Least Significant Bit. M m Meter. M Series An architecture for instrumentation-class, multichannel data acquisition devices based on the earlier E Series architecture with added new features.
Glossary MITE MXI Interface To Everything—A custom ASIC designed by National Instruments that implements the PCI bus interface. The MITE supports bus mastering for high-speed data transfers over the PCI bus. module A board assembly and its associated mechanical parts, front panel, optional shields, and so on. A module contains everything required to occupy one or more slots in a mainframe. SCXI and PXI devices are modules.
Glossary NI-PGIA See instrumentation amplifier. non-referenced signal sources Signal sources with voltage signals that are not connected to an absolute reference or system ground. Also called floating signal sources. Some common example of non-referenced signal sources are batteries, transformers, or thermocouples.
Glossary power source An instrument that provides one or more sources of AC or DC power. Also known as power supply. ppm Parts per million. pretriggering The technique used on a DAQ device to keep a continuous buffer filled with data, so that when the trigger conditions are met, the sample includes the data leading up to the trigger condition. pulse A signal whose amplitude deviates from zero for a short period of time.
Glossary real time 1. Displays as it comes in; no delays. 2. A property of an event or system in which data is processed and acted upon as it is acquired instead of being accumulated and processed at a later time. 3. Pertaining to the performance of a computation during the actual time that the related physical process transpires so results of the computation can be used in guiding the physical process.
Glossary SCXI Signal Conditioning eXtensions for Instrumentation—The National Instruments product line for conditioning low-level signals within an external chassis near sensors so that only high-level signals are sent to DAQ devices in the noisy PC environment. sensor A device that responds to a physical stimulus (heat, light, sound, pressure, motion, flow, and so on), and produces a corresponding electrical signal. Primary characteristics of sensors are sensitivity, frequency range, and linearity.
Glossary software triggering A method of triggering in which you simulate an analog trigger using software. Also called conditional retrieval. source impedance A parameter of signal sources that reflects current-driving ability of voltage sources (lower is better) and the voltage-driving ability of current sources (higher is better). synchronous 1. Hardware—A property of an event that is synchronized to a reference clock. 2.
Glossary trigger 1. Any event that causes or starts some form of data capture. 2. An external stimulus that initiates one or more instrument functions. Trigger stimuli include a front panel button, an external input voltage pulse, or a bus trigger command. The trigger may also be derived from attributes of the actual signal to be acquired, such as the level and slope of the signal. tsc Source clock period. tsp Source pulse width.
Glossary Vout Volts out. Vs Signal source voltage. virtual channel See channel. W waveform 1. The plot of the instantaneous amplitude of a signal as a function of time. 2. Multiple voltage readings taken at a specific sampling rate.
Index Symbols ai/ReferenceTrigger, 4-22 ai/SampleClock, 4-15 ai/SampleClockTimebase, 4-17 ai/StartTrigger, 4-21 analog input analog-to-digital converter, 4-2 channels, sampling with AI Sample Clock and AI Convert Clock, B-2 charge injection, B-1 circuitry, 4-1 crosstalk when sampling multiple channels, B-1 data acquisition methods, 4-10 FIFO, 4-2 getting started with applications in software, 4-24 ghost current when sampling multiple channels, B-1 ground-reference settings, 4-5 I/O connector, 4-1 instrumen
Index C timing signals, 5-5 trigger signals, 5-4 triggering, 5-4 troubleshooting, B-2 ANSI C documentation, xvi AO FIFO, 5-2 AO Pause Trigger signal, 5-7 AO Sample Clock signal, 5-8 AO Sample Clock Timebase signal, 5-10 AO Start Trigger signal, 5-6 ao/PauseTrigger, 5-7 ao/SampleClock, 5-8 ao/SampleClockTimebase, 5-10 ao/StartTrigger, 5-6 applications counter input, 7-2 counter output, 7-20 edge counting, 7-2 arm start trigger, 7-31 avoiding scanning faster than necessary, 4-9 cables, 2-4, A-3 choosing fo
Index single pulse generation, 7-20 single pulse generation with start trigger, 7-20 synchronization modes, 7-37 timing signals, 7-25 triggering, 7-31 troubleshooting, B-3 counting edges, 7-2 creating an AC return path, 9-3 crosstalk when sampling multiple channels, B-1 current, connecting analog input signals, 4-3 custom cabling, 2-4 controlling counting direction, 7-2 conventions used in the manual, xiii Counter n A signal, 7-28 Counter n Aux signal, 7-27 Counter n B signal, 7-28 Counter n Gate signal,
Index encoding X1, 7-15 X2, 7-16 X4, 7-16 equivalent time sampling, 7-24 examples (NI resources), C-1 exporting timing output signals using PFI terminals, 8-3 external reference clock, 10-2 source mode, 7-38 isolators, 9-1 routing, 10-1 signals, connecting, 6-2 source, triggering, 12-1 digital I/O circuitry, 6-1 connecting signals, 6-2 getting started with applications in software, 6-3 I/O protection, 6-1 programmable power-up states, 6-2 triggering, 12-1 digital isolators, 4-2, 5-2 DMA as a transfer meth
Index IRQ pulse train, 7-22 retriggerable single pulse, 7-21 simple pulse, 7-20 single pulse, 7-20 single pulse with start trigger, 7-20 software-timed, 5-2 getting started, 1-1 AI applications in software, 4-24 AO applications in software, 5-11 DIO applications in software, 6-3 ghost voltages when sampling multiple channels, B-1 ground-reference connections, checking, B-1 settings, analog input, 4-5 as a transfer method, 11-4 changing data transfer methods, 11-4 isolated DAQ devices, 9-1 benefits, 9-2 c
Index output signals glitches (troubleshooting), B-2 minimizing glitches, 5-2 outputs, using RTSI as, 10-5 overview, 2-1 measuring high frequency with two counters, 7-11 large range of frequencies using two counters, 7-12 low frequency with one counter, 7-9 averaged, 7-10 methods, data transfer, 11-3 minimizing glitches on the output signal, 5-2 output signal glitches (troubleshooting), B-2 multichannel scanning considerations, 4-8 multiple device synchronization, 10-3 P pause trigger, 7-31 period measur
Index using terminals as timing input signals, 10-6 train generation, 7-22 continuous, 7-22 pulse-width measurement, 7-5 buffered, 7-5 single, 7-5 PXI and PXI Express, 11-2 clock, 11-2 clock and trigger signals, 10-8 considerations, 11-2 trigger signals, 11-2 triggers, 10-8 using with CompactPCI, 11-3 PXI Express chassis compatibility, 11-2 PXI_CLK10, 10-8 PXI_STAR filters, 10-9 trigger, 10-8 S sample clock edge counting, 7-3 scanning speed, 4-9 semi-period measurement, 7-8 buffered, 7-9 single, 7-8 sens
Index synchronization modes, 7-37 80 MHz source, 7-38 external source, 7-38 other internal source, 7-38 synchronizing multiple devices, 10-3 synchronous counting mode, 7-34 Counter n Internal Output, 7-29 Counter n Source, 7-25 Counter n TC, 7-29 Counter n Up_Down, 7-28 Counter n Z, 7-28 counter timing, 7-25 counters, 7-25 exporting timing output using PFI terminals, 8-3 FREQ OUT, 7-29 Frequency Output, 7-29 minimizing output glitches, B-2 output, minimizing glitches on, 5-2 simple pulse generation, 7-20
Index V two-signal edge-separation measurement, 7-18 buffered, 7-19 single, 7-18 voltage, connecting analog voltage, 5-4 W waveform generation signals, 5-5 Web resources, C-1 wiring, field, 4-11 U using PFI terminals as static digital I/Os, 8-3 as timing input, 8-2 to export timing output signals, 8-3 using RTSI as outputs, 10-5 terminals as timing input signals, 10-6 using short high-quality cabling, 4-8 © National Instruments Corporation X X1 encoding, 7-15 X2 encoding, 7-16 X4 encoding, 7-16 I-9
