User’s Manual 78K/0 Series Instructions Common to 78K/0 Series Document No.
[MEMO] 2 User's Manual U12326EJ4V0UM
NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity.
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Major Revisions in This Edition Page Throughout Description Deletion of all information except for information common to the 78K/0 Series (for individual product information, refer to the user’s manual of each product). The mark 6 shows major revised points.
INTRODUCTION Target Readers This manual is intended for users who wish to understand the functions of 78K/0 Series products and to design and develop its application systems and programs. Purpose This manual is intended to give users an understanding of the various kinds of instruction functions of 78K/0 Series products. Organization This manual is broadly divided into the following sections.
Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. • Documents Common to 78K/0 Series Document Name User’s Manual Instructions Application Note Note Document No. This manual Basic I U12704E Basic II U10121E Basic III U10182E Note Some subseries may not be covered. Caution The related documents listed above are subject to change without notice.
CONTENTS CHAPTER 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 MEMORY SPACE ............................................................................................................... 12 Memory Spaces ................................................................................................................12 Internal Program Memory (Internal ROM) Space .......................................................... 12 Vector Table Area .........................................................................
CHAPTER 5 EXPLANATION OF INSTRUCTIONS ................................................................................. 46 5.1 8-Bit Data Transfer Instructions ...................................................................................... 48 5.2 16-Bit Data Transfer Instructions .................................................................................... 51 5.3 8-Bit Operation Instructions ............................................................................................ 54 5.
LIST OF FIGURES Figure No. Title Page 2-1 Program Counter Configuration .............................................................................................................. 14 2-2 Program Status Word Configuration ....................................................................................................... 14 2-3 Stack Pointer Configuration ....................................................................................................................
CHAPTER 1 MEMORY SPACE 1.1 Memory Spaces The 78K/0 Series product program memory map varies depending on the internal memory capacity. For details of memory-mapped address area, refer to the user’s manual of each product. 1.2 Internal Program Memory (Internal ROM) Space Each 78K/0 Series product has internal ROM in the address space. Program and table data, etc. are stored in the ROM. Normally, this memory space is addressed by the program counter (PC).
CHAPTER 1 MEMORY SPACE (3) RAM for VFD display There are some products in the 78K/0 Series to which RAM for VFD display is allocated. This RAM can also be used as an ordinary RAM area. (4) Internal expansion RAM There are some products in the 78K/0 Series to which internal expansion RAM is allocated. (5) RAM for LCD display There are some products in the 78K/0 Series to which RAM for LCD display is allocated. This RAM can also be used as an ordinary RAM area. 1.
CHAPTER 2 REGISTERS 2.1 Control Registers The control registers control the program sequence, statuses and stack memory. A program counter, a program status word and a stack pointer are the control registers. 2.1.1 Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched.
CHAPTER 2 REGISTERS (1) Interrupt enable flag (IE) This flag controls the interrupt request acknowledgement operations of the CPU. When IE = 0, the IE flag is set to interrupt disable (DI), and interrupts other than non-maskable interrupts are all disabled. When IE = 1, the IE flag is set to interrupt enable (EI), and interrupt request acknowledgement is controlled by an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority specification flag.
CHAPTER 2 REGISTERS 2.1.3 Stack pointer (SP) This is a 16-bit register that holds the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 2-3. Stack Pointer Configuration 15 0 SP The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. Each stack operation saves/resets data as shown in Figures 2-4 and 2-5.
CHAPTER 2 REGISTERS 2.2 General-Purpose Registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. These registers consist of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L and H). In addition that each register can be used as an 8-bit register, two 8-bit registers in pairs can be used as a 16bit register (AX, BC, DE and HL).
CHAPTER 2 REGISTERS Figure 2-6.
CHAPTER 2 REGISTERS 2.3 Special Function Registers (SFRs) Unlike a general-purpose register, each special-function register has a special function. Special function registers are allocated in the 256-byte area FF00H to FFFFH. Special function registers can be manipulated, like general-purpose registers, by operation, transfer and bit manipulation instructions. The manipulatable bit units (1, 8, and 16) differ depending on the special function register type.
CHAPTER 3 ADDRESSING 3.1 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
CHAPTER 3 ADDRESSING 3.1.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the “CALL !addr16” or “BR !addr16” or “CALLF !addr11” instruction is executed. The CALL !addr16 and BR !addr16 instructions can be branched to all memory spaces. The CALLF !addr11 instruction is branched to the area of 0800H to 0FFFH. [Illustration] CALL !addr16, BR !addr16 instruction 7 0 CALL or BR Low Addr.
CHAPTER 3 ADDRESSING 3.1.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by the lower-5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched. When the “CALLT [addr5]” instruction is executed, table indirect addressing is performed.
CHAPTER 3 ADDRESSING 3.1.4 Register addressing [Function] The register pair (AX) contents to be specified by an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the “BR AX” instruction is executed.
CHAPTER 3 ADDRESSING 3.2 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.2.1 Implied addressing [Function] This addressing automatically specifies the address of the registers that function as an accumulator (A and AX) in the general-purpose register area. Of the 78K/0 Series instruction words, the following instructions employ implied addressing.
CHAPTER 3 ADDRESSING 3.2.2 Register addressing [Function] Register addressing accesses a general-purpose register as an operand. The general-purpose register to be accessed is specified by the register bank selection flags (RBS0 and RBS1) and the register specification codes (Rn and RPn) in the instruction codes. Register addressing is carried out when an instruction with the following operand format is executed.
CHAPTER 3 ADDRESSING 3.2.3 Direct addressing [Function] Direct addressing directly addresses the memory indicated by the immediate data in the instruction word.
CHAPTER 3 ADDRESSING 3.2.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte fixed space FE20H to FF1FH. An internal high-speed RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the entire SFR area.
CHAPTER 3 ADDRESSING 3.2.5 Special-function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing.
CHAPTER 3 ADDRESSING 3.2.6 Register indirect addressing [Function] Register indirect addressing addresses memory with register pair contents specified as an operand. The register pair to be accessed is specified by the register bank selection flags (RBS0 and RBS1) and the register pair specification in instruction codes.
CHAPTER 3 ADDRESSING 3.2.7 Based addressing [Function] 8-bit immediate data is added to the contents of the HL register pair as a base register and the sum is used to address the memory. The HL register pair to be accessed is in the register bank specified by the register bank select flag (RBS0 and RBS1). Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
CHAPTER 3 ADDRESSING 3.2.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and RETURN instructions are executed or the register is saved/reset upon generation of an interrupt request. Stack addressing enables addressing of the internal high-speed RAM area only.
CHAPTER 4 INSTRUCTION SET This chapter lists the instructions in the 78K/0 Series instruction set. The instructions are common to all 78K/0 Series products. 4.1 Operation For the operation list for each product, refer to the user’s manual of each product. 4.1.1 Operand identifiers and description methods Operands are described in the “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details).
CHAPTER 4 INSTRUCTION SET 4.1.
CHAPTER 4 INSTRUCTION SET 4.1.4 Description of number of clocks 1 instruction clock cycle is 1 CPU clock cycle (fCPU) selected by the processor clock control register (PCC). 4.1.
CHAPTER 4 INSTRUCTION SET 2nd Operand #byte A rNote sfr saddr !addr16 PSW [DE] [HL] r 1 None [HL+B] [HL+C] 1st Operand A [HL+byte] $addr16 ADD MOV MOV MOV MOV ADDC SUB XCH ADD XCH XCH ADD XCH ADD SUBC AND ADDC SUB ADDC SUB OR XOR SUBC AND CMP MOV MOV MOV MOV MOV ROR XCH XCH ADD XCH ADD ROL RORC ADDC SUB ADDC SUB ADDC SUB ROLC SUBC AND SUBC AND SUBC AND SUBC AND OR XOR OR XOR OR XOR OR XOR OR XOR CMP CMP CMP CMP CMP MOV ADD INC DEC ADDC SUB SUBC
CHAPTER 4 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand #word AX rpNote sfrp saddrp !addr16 SP None 1st Operand AX ADDW SUBW MOVW XCHW MOVW MOVW MOVW MOVW CMPW rp MOVW MOVWNote INCW DECW PUSH POP sfrp MOVW MOVW saddrp MOVW MOVW !addr16 MOVW SP Note MOVW MOVW Only when rp = BC, DE or HL. (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR 2nd Operand A.bit sfr.bit saddr.
CHAPTER 4 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ 2nd Operand AX !addr16 !addr11 [addr5] $addr16 1st Operand Basic Instructions BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound Instructions BT BF BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP User's Manual U12326EJ4V0UM 37
CHAPTER 4 INSTRUCTION SET 4.2 Instruction Codes 4.2.
CHAPTER 4 INSTRUCTION SET 4.2.
CHAPTER 4 INSTRUCTION SET Instruction Mnemonic Operands Operation Code Group B1 B2 B3 B4 16-Bit Data MOVW rp,#word 0 0 0 1 0 P1 P0 0 Low byte High byte Transfer saddrp,#word 1 1 1 0 1 1 1 0 Saddr-offset Low byte High byte sfrp,#word 1 1 1 1 1 1 1 0 Sfr-offset Low byte High byte AX,saddrp 1 0 0 0 1 0 0 1 Saddr-offset saddrp,AX 1 0 0 1 1 0 0 1 Saddr-offset AX,sfrp 1 0 1 0 1 0 0 1 Sfr-offset sfrp,AX 1 0 1 1 1 0 0 1 Sfr-offset 8-Bit AX,rp Note 1 1 1 0 0 0 P1 P0 0 rp,AX
CHAPTER 4 INSTRUCTION SET Instruction Mnemonic Operands Operation Code Group 8-Bit SUB Operation B1 B2 A,#byte 0 0 0 1 1 1 0 1 Data saddr,#byte 1 0 0 1 1 0 0 0 Saddr-offset A,r SUBC Note 0 1 1 0 0 0 0 1 0 0 0 1 0 R2 R1 R0 A,saddr 0 0 0 1 1 1 1 0 Saddr-offset A,!addr16 0 0 0 1 1 0 0 0 Low addr A,[HL] 0 0 0 1 1 1 1 1 A,[HL+byte] 0 0 0 1 1 0 0 1 A,[HL+B] 0 0 1 1 0 0 0 1 0 0 0 1 1 0 1 1 A,[HL+C] 0 0 1 1 0 0 0 1 0 0 0 1 1 0 1 0 A,#byte 0 0 1 1 1 1 0 1 Data 1 0 1 1 1 0 0 0 Sa
CHAPTER 4 INSTRUCTION SET Instruction Mnemonic Operands Operation Code Group 8-Bit OR Operation B1 B2 A,#byte 0 1 1 0 1 1 0 1 Data saddr,#byte 1 1 1 0 1 0 0 0 Saddr-offset A,r XOR Note 0 1 1 0 0 0 0 1 0 1 1 0 0 R2 R1 R0 A,saddr 0 1 1 0 1 1 1 0 Saddr-offset A,!addr16 0 1 1 0 1 0 0 0 Low addr A,[HL] 0 1 1 0 1 1 1 1 A,[HL+byte] 0 1 1 0 1 0 0 1 A,[HL+B] 0 0 1 1 0 0 0 1 0 1 1 0 1 0 1 1 A,[HL+C] 0 0 1 1 0 0 0 1 0 1 1 0 1 0 1 0 A,#byte 0 1 1 1 1 1 0 1 Data 1 1 1 1 1 0 0 0 Sadd
CHAPTER 4 INSTRUCTION SET Instruction Mnemonic Operands Group Operation Code B1 B2 B3 16-Bit ADDW AX,#word 1 1 0 0 1 0 1 0 Low byte High byte Operation SUBW AX,#word 1 1 0 1 1 0 1 0 Low byte High byte CMPW AX,#word 1 1 1 0 1 0 1 0 Low byte High byte Multiply/ MULU X 0 0 1 1 0 0 0 1 1 0 0 0 1 0 0 0 divide DIVUW C 0 0 1 1 0 0 0 1 1 0 0 0 0 0 1 0 Increment/ INC r 0 1 0 0 0 R2 R1 R0 saddr 1 0 0 0 0 0 0 1 r 0 1 0 1 0 R2 R1 R0 saddr 1 0 0 1 0 0 0 1 INCW rp 1 0 0 0 0 P1
CHAPTER 4 INSTRUCTION SET Instruction Mnemonic Operands Operation Code Group Bit B1 OR1 0 1 1 1 0 0 0 1 0 B2 B1 B0 0 1 1 0 Saddr-offset CY,sfr.bit 0 1 1 1 0 0 0 1 0 B2 B1 B0 1 1 1 0 Sfr-offset CY,A.bit 0 1 1 0 0 0 0 1 1 B2 B1 B0 1 1 1 0 CY,PSW.bit 0 1 1 1 0 0 0 1 0 B2 B1 B0 0 1 1 0 0 0 0 1 1 1 1 0 CY,[HL].bit 0 1 1 1 0 0 0 1 1 B2 B1 B0 0 1 1 0 CY,saddr.bit 0 1 1 1 0 0 0 1 0 B2 B1 B0 0 1 1 1 Saddr-offset CY,sfr.bit 0 1 1 1 0 0 0 1 0 B2 B1 B0 1 1 1 1 Sfr-offset CY,A.
CHAPTER 4 INSTRUCTION SET Instruction Mnemonic Operands Group Operation Code B1 B2 B3 !addr16 1 0 0 1 1 0 1 1 Low addr High addr $addr16 1 1 1 1 1 0 1 0 jdisp AX 0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 Conditional BC $addr16 1 0 0 0 1 1 0 1 jdisp Branch BNC $addr16 1 0 0 1 1 1 0 1 jdisp BZ $addr16 1 0 1 0 1 1 0 1 jdisp BNZ $addr16 1 0 1 1 1 1 0 1 jdisp BT saddr.bit,$addr16 1 B2 B1 B0 1 1 0 0 Unconditional BR Branch BF BTCLR DBNZ Saddr-offset jdisp sfr.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS This chapter explains the instructions of 78K/0 Series products. Each instruction is described with a mnemonic, including description of multiple operands. The basic configuration of instruction description is shown on the next page. For the number of instruction bytes and the instruction codes, refer to the user’s manual of each product and CHAPTER 4 INSTRUCTION SET, respectively. All the instructions are common to 78K/0 Series products.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS DESCRIPTION EXAMPLE Mnemonic Full name Move MOV Byte Data Transfer Meaning of instruction [Instruction format] MOV dst, src: Indicates the basic description format of the instruction. [Operation] dst ← src: Indicates instruction operation using symbols. [Operand] Indicates operands that can be specified by this instruction. Refer to 4.1 Operation for the description of each operand symbol.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.1 8-Bit Data Transfer Instructions The following instructions are 8-bit data transfer instructions. MOV ... 49 XCH ...
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Move MOV Byte Data Transfer [Instruction format] MOV dst, src [Operation] dst ← src [Operand] Mnemonic Operand(dst,src) MOV Mnemonic r, #byte MOV saddr, #byte Operand(dst,src) A, PSW PSW, A sfr, #byte A, [DE] A, r Note [DE], A r, A Note A, [HL] A, saddr [HL], A saddr, A A, [HL+byte] A, sfr [HL+byte], A sfr, A A, [HL+B] A, !addr16 [HL+B], A !addr16, A A, [HL+C] PSW, #byte [HL+C], A Note Except r = A [Flag] PSW, #byte and PSW, All o
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Exchange XCH Byte Data Exchange [Instruction format] XCH dst, src [Operation] dst ↔ src [Operand] Mnemonic XCH Operand(dst,src) Mnemonic Note A, r XCH Operand(dst,src) A, [HL] A, saddr A, [HL+byte] A, sfr A, [HL+B] A, !addr16 A, [HL+C] A, [DE] Note Except r = A [Flag] Z AC CY [Description] • The 1st and 2nd operand contents are exchanged. [Description example] XCH A, FEBCH; The A register contents and address FEBCH contents are exchanged.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.2 16-Bit Data Transfer Instructions The following instructions are 16-bit data transfer instructions. MOVW ... 52 XCHW ...
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Move Word MOVW Word Data Transfer [Instruction format] MOVW dst, src [Operation] dst ← src [Operand] Mnemonic MOVW Operand(dst,src) Mnemonic rp, #word MOVW Operand(dst,src) sfrp, AX saddrp, #word AX, rp Note sfrp, #word rp, AX Note AX, saddrp AX, !addr16 saddrp, AX !addr16, AX AX, sfrp Note Only when rp = BC, DE or HL [Flag] Z AC CY [Description] • The contents of the source operand (src) specified by the 2nd operand are transferred to the de
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Exchange Word XCHW Word Data Exchange [Instruction format] XCHW dst, src [Operation] dst ↔ src [Operand] Mnemonic XCHW Operand(dst,src) AX, rp Note Note Only when rp = BC, DE or HL [Flag] Z AC CY [Description] • The 1st and 2nd operand contents are exchanged. [Description example] XCHW AX, BC; The memory contents of the AX register are exchanged with those of the BC register.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.3 8-Bit Operation Instructions The following are 8-bit operation instructions. ADD ... 55 ADDC ... 56 SUB ... 57 SUBC ... 58 AND ... 59 OR ... 60 XOR ... 61 CMP ...
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Add ADD Byte Data Addition [Instruction format] ADD dst, src [Operation] dst, CY ← dst + src [Operand] Mnemonic Operand(dst,src) ADD Mnemonic A, #byte ADD saddr, #byte A, !addr16 A, [HL] Note A, r Operand(dst,src) A, [HL+byte] r, A A, [HL+B] A, saddr A, [HL+C] Note Except r = A [Flag] Z AC CY × × × [Description] • The destination operand (dst) specified by the 1st operand is added to the source operand (src) specified by the 2nd operand an
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Add with Carry ADDC Addition of Byte Data with Carry [Instruction format] ADDC dst, src [Operation] dst, CY ← dst + src + CY [Operand] Mnemonic Operand(dst,src) ADDC Mnemonic A, #byte ADDC saddr, #byte A, !addr16 A, [HL] Note A, r Operand(dst,src) A, [HL+byte] r, A A, [HL+B] A, saddr A, [HL+C] Note Except r = A [Flag] Z AC CY × × × [Description] • The destination operand (dst) specified by the 1st operand, the source operand (src) specifie
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Subtract SUB Byte Data Subtraction [Instruction format] SUB dst, src [Operation] dst, CY ← dst – src [Operand] Mnemonic Operand(dst,src) SUB Mnemonic A, #byte SUB saddr, #byte A, !addr16 A, [HL] Note A, r Operand(dst,src) A, [HL+byte] r, A A, [HL+B] A, saddr A, [HL+C] Note Except r = A [Flag] Z AC CY × × × [Description] • The source operand (src) specified by the 2nd operand is subtracted from the destination operand (dst) specified by the
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Subtract with Carry SUBC Subtraction of Byte Data with Carry [Instruction format] SUBC dst, src [Operation] dst, CY ← dst – src – CY [Operand] Mnemonic Operand(dst,src) SUBC Mnemonic A, #byte SUBC saddr, #byte A, !addr16 A, [HL] Note A, r Operand(dst,src) A, [HL+byte] r, A A, [HL+B] A, saddr A, [HL+C] Note Except r = A [Flag] Z AC CY × × × [Description] • The source operand (src) specified by the 2nd operand and the CY flag are subtracted
CHAPTER 5 EXPLANATION OF INSTRUCTIONS And AND Logical Product of Byte Data [Instruction format] AND dst, src [Operation] dst ← dst ∧ src [Operand] Mnemonic AND Operand(dst,src) Mnemonic A, #byte AND saddr, #byte A, !addr16 A, [HL] Note A, r Operand(dst,src) A, [HL+byte] r, A A, [HL+B] A, saddr A, [HL+C] Note Except r = A [Flag] Z AC CY × [Description] • Bit-wise logical product is obtained from the destination operand (dst) specified by the 1st operand and the source operand (src
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Or OR Logical Sum of Byte Data [Instruction format] OR dst, src [Operation] dst ← dst ∨ src [Operand] Mnemonic OR Operand(dst,src) Mnemonic A, #byte OR saddr, #byte A, !addr16 A, [HL] Note A, r Operand(dst,src) A, [HL+byte] r, A A, [HL+B] A, saddr A, [HL+C] Note Except r = A [Flag] Z AC CY × [Description] • The bit-wise logical sum is obtained from the destination operand (dst) specified by the 1st operand and the source operand (src) specifi
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Exclusive Or XOR Exclusive Logical Sum of Byte Data [Instruction format] XOR dst, src [Operation] dst ← dst ∨ src [Operand] Mnemonic XOR Operand(dst,src) Mnemonic A, #byte XOR saddr, #byte A, !addr16 A, [HL] Note A, r Operand(dst,src) A, [HL+byte] r, A A, [HL+B] A, saddr A, [HL+C] Note Except r = A [Flag] Z AC CY × [Description] • The bit-wise exclusive logical sum is obtained from the destination operand (dst) specified by the 1st operand an
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Compare CMP Byte Data Comparison [Instruction format] CMP dst, src [Operation] dst – src [Operand] Mnemonic Operand(dst,src) CMP Mnemonic A, #byte CMP saddr, #byte A, !addr16 A, [HL] Note A, r Operand(dst,src) A, [HL+byte] r, A A, [HL+B] A, saddr A, [HL+C] Note Except r = A [Flag] Z AC CY × × × [Description] • The source operand (src) specified by the 2nd operand is subtracted from the destination operand (dst) specified by the 1st operand
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.4 16-Bit Operation Instructions The following are 16-bit operation instructions. ADDW ... 64 SUBW ... 65 CMPW ...
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Add Word ADDW Word Data Addition [Instruction format] ADDW dst, src [Operation] dst, CY ← dst + src [Operand] Mnemonic Operand(dst,src) ADDW AX, #word [Flag] Z AC CY × × × [Description] • The destination operand (dst) specified by the 1st operand is added to the source operand (src) specified by the 2nd operand and the result is stored in the destination operand (dst). • If the addition result shows that dst is 0, the Z flag is set (1).
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Subtract Word SUBW Word Data Subtraction [Instruction format] SUBW dst, src [Operation] dst, CY ← dst – src [Operand] Mnemonic Operand(dst,src) SUBW AX, #word [Flag] Z AC CY × × × [Description] • The source operand (src) specified by the 2nd operand is subtracted from the destination operand (dst) specified by the 1st operand and the result is stored in the destination operand (dst) and the CY flag.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Compare Word CMPW Word Data Comparison [Instruction format] CMPW dst, src [Operation] dst – src [Operand] Mnemonic Operand(dst,src) CMPW AX, #word [Flag] Z AC CY × × × [Description] • The source operand (src) specified by the 2nd operand is subtracted from the destination operand (dst) specified by the 1st operand. The subtraction result is not stored anywhere and only the Z, AC and CY flags are changed.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.5 Multiply/Divide Instructions The following are multiply/divide instructions. MULU ... 68 DIVUW ...
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Multiply Unsigned MULU Unsigned Multiplication of Data [Instruction format] MULU src [Operation] AX ← A × src [Operand] Mnemonic MULU Operand(src) X [Flag] Z AC CY [Description] • The A register contents and the source operand (src) data are multiplied as unsigned data and the result is stored in the AX register. [Description example] MULU X; The A register contents and the X register contents are multiplied and the result is stored in the AX register.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Divide Unsigned Word DIVUW Unsigned Division of Word Data [Instruction format] DIVUW dst [Operation] AX (quotient), dst (remainder) ← AX ÷ dst [Operand] Mnemonic DIVUW Operand(dst) C [Flag] Z AC CY [Description] • The AX register contents are divided by the destination operand (dst) contents and the quotient and the remainder are stored in the AX register and the destination operand (dst), respectively.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.6 Increment/Decrement Instructions The following are increment/decrement instructions. INC ... 71 DEC ... 72 INCW ... 73 DECW ...
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Increment INC Byte Data Increment [Instruction format] INC dst [Operation] dst ← dst + 1 [Operand] Mnemonic Operand(dst) INC r saddr [Flag] Z AC × × CY [Description] • The destination operand (dst) contents are incremented by only one. • If the increment result is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0). • If the increment generates a carry for bit 4 out of bit 3, the AC flag is set (1).
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Decrement DEC Byte Data Decrement [Instruction format] DEC dst [Operation] dst ← dst – 1 [Operand] Mnemonic Operand(dst) DEC r saddr [Flag] Z AC × × CY [Description] • The destination operand (dst) contents are decremented by only one. • If the decrement result is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0). • If the decrement generates a carry for bit 3 out of bit 4, the AC flag is set (1).
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Increment Word INCW Word Data Increment [Instruction format] INCW dst [Operation] dst ← dst + 1 [Operand] Mnemonic INCW Operand(dst) rp [Flag] Z AC CY [Description] • The destination operand (dst) contents are incremented by only one. • Because this instruction is frequently used for increment of a register (pointer) used for addressing, the Z, AC and CY flag contents are not changed. [Description example] INCW HL; The HL register is incremented.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Decrement Word DECW Word Data Decrement [Instruction format] DECW dst [Operation] dst ← dst – 1 [Operand] Mnemonic DECW Operand (dst) rp [Flag] Z AC CY [Description] • The destination operand (dst) contents are decremented by only one. • Because this instruction is frequently used for decrement of a register (pointer) used for addressing, the Z, AC and CY flag contents are not changed. [Description example] DECW DE; The DE register is decremented.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.7 Rotate Instructions The following are rotate instructions. ROR ... 76 ROL ... 77 RORC ... 78 ROLC ... 79 ROR4 ... 80 ROL4 ...
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Rotate Right ROR Byte Data Rotation to the Right [Instruction format] ROR dst, cnt [Operation] (CY, dst7 ← dst 0, dst m–1 ← dstm) × one time [Operand] Mnemonic ROR Operand(dst,cnt) A, 1 [Flag] Z AC CY × [Description] • The destination operand (dst) contents specified by the 1st operand are rotated to the right just once. • The LSB (bit 0) contents are simultaneously rotated to MSB (bit 7) and transferred to the CY flag.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Rotate Left ROL Byte Data Rotation to the Left [Instruction format] ROL dst, cnt [Operation] (CY, dst0 ← dst 7, dstm+1 ← dstm) × one time [Operand] Mnemonic ROL Operand(dst,cnt) A, 1 [Flag] Z AC CY × [Description] • The destination operand (dst) contents specified by the 1st operand are rotated to the left just once. • The MSB (bit 7) contents are simultaneously rotated to LSB (bit 0) and transferred to the CY flag.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Rotate Right with Carry RORC Byte Data Rotation to the Right with Carry [Instruction format] RORC dst, cnt [Operation] (CY ← dst 0, dst 7 ← CY, dstm–1 ← dst m) × one time [Operand] Mnemonic RORC Operand(dst,cnt) A, 1 [Flag] Z AC CY × [Description] • The destination operand (dst) contents specified by the 1st operand are rotated just once to the right with carry.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Rotate Left with Carry ROLC Byte Data Rotation to the Left with Carry [Instruction format] ROLC dst, cnt [Operation] (CY ← dst 7, dst 0 ← CY, dstm+1 ← dstm ) × one time [Operand] Mnemonic ROLC Operand(dst,cnt) A, 1 [Flag] Z AC CY × [Description] • The destination operand (dst) contents specified by the 1st operand are rotated just once to the left with carry.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Rotate Right Digit ROR4 Digit Rotation to the Right [Instruction format] ROR4 dst [Operation] A3-0 ← (dst) 3-0, (dst)7-4 ← A 3-0, (dst)3-0 ← (dst) 7-4 [Operand] Mnemonic ROR4 Operand(dst) Note [HL] Note Specify an area other than the SFR area as operand [HL]. [Flag] Z AC CY [Description] • The lower 4 bits of the A register and the 2-digit data (4-bit data) of the destination operand (dst) are rotated to the right.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Rotate Left Digit ROL4 Digit Rotation to the Left [Instruction format] ROL4 dst [Operation] A3-0 ← (dst)7-4, (dst)3-0 ← A3-0, (dst) 7-4 ← (dst)3-0 [Operand] Mnemonic ROL4 Operand(dst) Note [HL] Note Specify an area other than the SFR area as operand [HL]. [Flag] Z AC CY [Description] • The lower 4 bits of the A register and the 2-digit data (4-bit data) of the destination operand (dst) are rotated to the left.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.8 BCD Adjust Instructions The following are BCD adjust instructions. ADJBA ... 83 ADJBS ...
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Decimal Adjust Register for Addition ADJBA Decimal Adjustment of Addition Result [Instruction format] ADJBA [Operation] Decimal Adjust Accumulator for Addition [Operand] None [Flag] Z AC CY × × × [Description] • The A register, CY flag and AC flag are decimally adjusted from their contents.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Decimal Adjust Register for Subtraction ADJBS Decimal Adjustment of Subtraction Result [Instruction format] ADJBS [Operation] Decimal Adjust Accumulator for Subtraction [Operand] None [Flag] Z AC CY × × × [Description] • The A register, CY flag and AC flag are decimally adjusted from their contents.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.9 Bit Manipulation Instructions The following are bit manipulation instructions. MOV1 ... 86 AND1 ... 87 OR1 ... 88 XOR1 ... 89 SET1 ... 90 CLR1 ... 91 NOT1 ...
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Move Single Bit MOV1 1 Bit Data Transfer [Instruction format] MOV1 dst, src [Operation] dst ← src [Operand] Mnemonic MOV1 Operand(dst,src) Mnemonic CY, saddr.bit MOV1 Operand(dst,src) saddr.bit, CY CY, sfr.bit sfr.bit, CY CY, A.bit A.bit, CY CY, PSW.bit PSW.bit, CY CY, [HL].bit [HL].bit, CY [Flag] dst = CY Z PSW.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS And Single Bit AND1 1 Bit Data Logical Product [Instruction format] AND1 dst, src [Operation] dst ← dst ∧ src [Operand] Mnemonic AND1 Operand(dst,src) CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Or Single Bit OR1 1 Bit Data Logical Sum [Instruction format] OR1 dst, src [Operation] dst ← dst ∨ src [Operand] Mnemonic OR1 Operand(dst,src) CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit [Flag] Z AC CY × [Description] • The logical sum of bit data of the destination operand (dst) specified by the 1st operand and the source operand (src) specified by the 2nd operand is obtained and the result is stored in the destination operand (dst).
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Exclusive Or Single Bit XOR1 1 Bit Data Exclusive Logical Sum [Instruction format] XOR1 dst, src [Operation] dst ← dst ∨ src [Operand] Mnemonic XOR1 Operand(dst,src) CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Set Single Bit (Carry Flag) SET1 1 Bit Data Set [Instruction format] SET1 dst [Operation] dst ←1 [Operand] Mnemonic Operand(dst) SET1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit CY [Flag] dst = PSW.bit dst = CY Z AC CY × × × Z In all other cases AC CY Z AC CY 1 [Description] • The destination operand (dst) is set (1). • When the destination operand (dst) is CY or PSW.bit, only the corresponding flag is set (1). [Description example] SET1 FE55H.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Clear Single Bit (Carry Flag) CLR1 1 Bit Data Clear [Instruction format] CLR1 dst [Operation] dst ← 0 [Operand] Mnemonic Operand(dst) CLR1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit CY [Flag] dst = PSW.bit dst = CY Z AC CY × × × Z In all other cases AC CY Z AC CY 0 [Description] • The destination operand (dst) is cleared (0). • When the destination operand (dst) is CY or PSW.bit, only the corresponding flag is cleared (0).
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Not Single Bit (Carry Flag) NOT1 1 Bit Data Logical Negation [Instruction format] NOT1 dst [Operation] dst ← dst [Operand] Mnemonic NOT1 Operand(dst) CY [Flag] Z AC CY × [Description] • The CY flag is inverted. [Description example] NOT1 CY; The CY flag is inverted.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.10 Call Return Instructions The following are call return instructions. CALL ... 94 CALLF ... 95 CALLT ... 96 BRK ... 97 RET ... 98 RETI ... 99 RETB ...
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Call CALL Subroutine Call (16 Bit Direct) [Instruction format] CALL target [Operation] (SP–1) ← (PC+3)H, (SP–2) ← (PC+3)L, SP ← SP–2, PC ← target [Operand] Mnemonic CALL Operand(target) !addr16 [Flag] Z AC CY [Description] • This is a subroutine call with a 16-bit absolute address or a register indirect address.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Call Flag CALLF Subroutine Call (11 Bit Direct Specification) [Instruction format] CALLF Target [Operation] (SP–1) ← (PC+2)H, (SP–2) ← (PC+2)L, SP ← SP–2, PC ← target [Operand] Mnemonic Operand(target) CALLF !addr11 [Flag] Z AC CY [Description] • This is a subroutine call which can only be branched to addresses 0800H to 0FFFH.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Call Table CALLT Subroutine Call (Refer to the Call Table) [Instruction format] CALLT [addr5] [Operation] (SP–1) ← (PC+1)H, (SP–2) ← (PC+1)L, SP ← SP–2, PCH ← (00000000, addr5+1) PCL ← (00000000, addr5) [Operand] Mnemonic CALLT Operand([addr5]) [addr5] [Flag] Z AC CY [Description] • This is a subroutine call for call table reference.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Break BRK Software Vectored Interrupt [Instruction format] BRK [Operation] (SP–1) ← PSW, (SP–2) ← (PC+1)H, (SP–3) ← (PC+1)L, IE ← 0, SP ← SP–3, PCH ← (3FH), PCL ← (3EH) [Operand] None [Flag] Z AC CY [Description] • This is a software interrupt instruction. • PSW and the next instruction address (PC+1) are saved to the stack.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Return RET Return from Subroutine [Instruction format] RET [Operation] PCL ← (SP), PCH ← (SP+1), SP ← SP+2 [Operand] None [Flag] Z AC CY [Description] • This is a return instruction from the subroutine call made with the CALL, CALLF and CALLT instructions. • The word data saved to the stack returns to the PC, and the program returns from the subroutine.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Return from Interrupt RETI Return from Hardware Vectored Interrupt [Instruction format] RETI [Operation] PCL ← (SP), PCH ← (SP+1), PSW ← (SP+2), SP ← SP+3, NMIS ← 0 [Operand] None [Flag] Z AC CY R R R [Description] • This is a return instruction from the vectored interrupt. • The data saved to the stack returns to the PC and the PSW, and the program returns from the interrupt service routine.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Return from Break RETB Return from Software Vectored Interrupt [Instruction format] RETB [Operation] PCL ← (SP), PCH ← (SP+1), PSW ← (SP+2), SP ← SP+3 [Operand] None [Flag] Z AC CY R R R [Description] • This is a return instruction from the software interrupt generated with the BRK instruction. • The data saved in the stack returns to the PC and the PSW, and the program returns from the interrupt service routine.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.11 Stack Manipulation Instructions The following are stack manipulation instructions. PUSH ... 102 POP ... 103 MOVW SP, src ... 104 MOVW AX, SP ...
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Push PUSH Push [Instruction format] PUSH src [Operation] When src = rp When src = PSW (SP–1) ← srcH, (SP–1) ← src (SP–2) ← src L, SP SP ← SP–1 ← SP–2 [Operand] Mnemonic PUSH Operand(src) PSW rp [Flag] Z AC CY [Description] • The data of the register specified by the source operand (src) is saved to the stack. [Description example] PUSH AX; AX register contents are saved to the stack.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Pop POP Pop [Instruction format] POP dst [Operation] When dst = rp When dst = PSW dst L ← (SP), dst ← (SP) dstH ← (SP+1), SP ← SP+1 SP ← SP+2 [Operand] Mnemonic POP Operand(dst) PSW rp [Flag] dst =rp Z PSW AC CY Z AC CY R R R [Description] • Data is returned from the stack to the register specified by the destination operand (dst). • When the operand is PSW, each flag is replaced with stack data.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS MOVW SP, src MOVW AX, SP [Instruction format] MOVW dst, src [Operation] dst ← src Move Word Word Data Transfer with Stack Pointer [Operand] Mnemonic MOVW Operand(dst,src) SP, #word SP, AX AX, SP [Flag] Z AC CY [Description] • This is an instruction to manipulate the stack pointer contents. • The source operand (src) specified by the 2nd operand is stored in the destination operand (dst) specified by the 1st operand.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.12 Unconditional Branch Instruction The unconditional branch instruction is shown below. BR ...
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch BR Unconditional Branch [Instruction format] BR target [Operation] PC ← target [Operand] Mnemonic BR Operand(target) !addr16 AX $addr16 [Flag] Z AC CY [Description] • This is an instruction to branch unconditionally. • The word data of the target address operand (target) is transferred to PC and branched. [Description example] BR AX; The AX register contents are branched as the address.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.13 Conditional Branch Instructions Conditional branch instructions are shown below. BC ... 108 BNC ... 109 BZ ... 110 BNZ ... 111 BT ... 112 BF ... 113 BTCLR ... 114 DBNZ ...
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch if Carry BC Conditional Branch with Carry Flag (CY = 1) [Instruction format] BC $addr16 [Operation] PC ← PC+2+jdisp8 if CY = 1 [Operand] Mnemonic BC Operand($addr16) $addr16 [Flag] Z AC CY [Description] • When CY = 1, data is branched to the address specified by the operand. When CY = 0, no processing is carried out and the subsequent instruction is executed.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch if Not Carry BNC Conditional Branch with Carry Flag (CY = 0) [Instruction format] BNC $addr16 [Operation] PC ← PC+2+jdisp8 if CY = 0 [Operand] Mnemonic BNC Operand($addr16) $addr16 [Flag] Z AC CY [Description] • When CY = 0, data is branched to the address specified by the operand. When CY = 1, no processing is carried out and the subsequent instruction is executed.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch if Zero BZ Conditional Branch with Zero Flag (Z = 1) [Instruction format] BZ $addr16 [Operation] PC ← PC+2+jdisp8 if Z = 1 [Operand] Mnemonic BZ Operand($addr16) $addr16 [Flag] Z AC CY [Description] • When Z = 1, data is branched to the address specified by the operand. When Z = 0, no processing is carried out and the subsequent instruction is executed.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch if Not Zero BNZ Conditional Branch with Zero Flag (Z = 0) [Instruction format] BNZ $addr16 [Operation] PC ← PC+2+jdisp8 if Z = 0 [Operand] Mnemonic BNZ Operand($addr16) $addr16 [Flag] Z AC CY [Description] • When Z = 0, data is branched to the address specified by the operand. When Z = 1, no processing is carried out and the subsequent instruction is executed.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch if True BT Conditional Branch by Bit Test (Byte Data Bit = 1) [Instruction format] BT bit, $addr16 [Operation] PC ← PC+b+jdisp8 if bit = 1 [Operand] Mnemonic BT Operand(bit,$addr16) b(Number of bytes) saddr.bit, $addr16 3 sfr.bit, $addr16 4 A.bit, $addr16 3 PSW.bit, $addr16 3 [HL].
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch if False BF Conditional Branch by Bit Test (Byte Data Bit = 0) [Instruction format] BF bit, $addr16 [Operation] PC ← PC+b+jdisp8 if bit = 0 [Operand] Mnemonic BF Operand(bit,$addr16) b(Number of bytes) saddr.bit, $addr16 4 sfr.bit, $addr16 4 A.bit, $addr16 3 PSW.bit, $addr16 4 [HL].
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch if True and Clear BTCLR Conditional Branch and Clear by Bit Test (Byte Data Bit = 1) [Instruction format] BTCLR bit, $addr16 [Operation] PC ← PC+b+jdisp8 if bit = 1, then bit ← 0 [Operand] Mnemonic Operand(bit,$addr16) BTCLR b(Number of bytes) saddr.bit, $addr16 4 sfr.bit, $addr16 4 A.bit, $addr16 3 PSW.bit, $addr16 4 [HL].bit, $addr16 3 [Flag] bit =PSW.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Decrement and Branch if Not Zero DBNZ Conditional Loop (R1 ≠ 0) [Instruction format] DBNZ dst, $addr16 dst ← dst–1, [Operation] then PC ← PC+b+jdisp16 if dst R1 ≠ 0 [Operand] Mnemonic DBNZ Operand(dst,$addr16) b(Number of bytes) B, $addr16 2 C, $addr16 2 saddr, $addr16 3 [Flag] Z AC CY [Description] • One is subtracted from the destination operand (dst) contents specified by the 1st operand and the subtraction result is stored in the destination opera
CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.14 CPU Control Instructions The following are CPU control instructions. SEL RBn ... 117 NOP ... 118 EI ... 119 DI ... 120 HALT ... 121 STOP ...
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Select Register Bank SEL RBn Register Bank Selection [Instruction format] SEL RBn [Operation] RBS0, RBS1 ← n; (n = 0-3) [Operand] Mnemonic SEL Operand(RBn) RBn [Flag] Z AC CY [Description] • The register bank specified by the operand (RBn) is made a register bank for use by the next and subsequent instructions. • RBn ranges from RB0 to RB3. [Description example] SEL RB2; Register bank 2 is selected as the one for use by the next and subsequent instructions.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS No Operation NOP No Operation [Instruction format] NOP [Operation] no operation [Operand] None [Flag] Z AC CY [Description] • Only the time is consumed without processing.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Enable Interrupt EI Interrupt Enabled [Instruction format] EI [Operation] IE ← 1 [Operand] None [Flag] Z AC CY [Description] • The maskable interrupt acknowledgeable status is set (by setting the interrupt enable flag (IE) to (1)). • No interrupts are acknowledged between this instruction and the next instruction. • If this instruction is executed, vectored interrupt acknowledgment from another source can be disabled.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Disable Interrupt DI Interrupt Disabled [Instruction format] DI [Operation] IE ← 0 [Operand] None [Flag] Z AC CY [Description] • Maskable interrupt acknowledgment by vectored interrupt is disabled (with the interrupt enable flag (IE) cleared (0)). • No interrupts are acknowledged between this instruction and the next instruction. • For details of interrupt servicing, refer to “Interrupt Functions” in the user’s manual of each product.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Halt HALT HALT Mode Set [Instruction format] HALT [Operation] Set HALT Mode [Operand] None [Flag] Z AC CY [Description] • This instruction is used to set the HALT mode to stop the CPU operation clock. The total power consumption of the system can be decreased with intermittent operation by combining this mode with the normal operation mode.
CHAPTER 5 EXPLANATION OF INSTRUCTIONS Stop STOP Stop Mode Set [Instruction format] STOP [Operation] Set STOP Mode [Operand] None [Flag] Z AC CY [Description] • This instruction is used to set the STOP mode to stop the main system clock oscillator and to stop the whole system. Power consumption can be minimized to only leakage current.
APPENDIX A REVISION HISTORY The following table shows the revision history of the previous editions. The “Applied to:” column indicates the chapters of each edition in which the revision was applied. Edition 2nd Major Revision from Previous Edition Addition of the following versions: Applied to: Throughout µPD78055 and 78P058, and µPD78018F, 78044A, 78054Y, 78078, 78083, 78098, and 780208 Subseries Addition of the English documentation No.
APPENDIX B INSTRUCTION INDEX (MNEMONIC: BY FUNCTION) [8-bit data transfer instructions] [Rotate instructions] MOV ... 49 ROR ... 76 XCH ... 50 ROL ... 77 RORC ... 78 [16-bit data transfer instructions] ROLC ... 79 ROR4 ... 80 MOVW ... 52 ROL4 ... 81 XCHW ... 53 [BCD adjust instructions] [8-bit operation instructions] ADJBA ... 83 ADD ... 55 ADJBS ... 84 ADDC ... 56 SUB ... 57 [Bit manipulation instructions] SUBC ... 58 AND ... 59 MOV1 ... 86 OR ... 60 AND1 ... 87 XOR ... 61 OR1 ...
APPENDIX B INSTRUCTION INDEX (MNEMONIC: BY FUNCTION) [Unconditional branch instruction] BR ... 106 [Conditional branch instructions] BC ... 108 BNC ... 109 BZ ... 110 BNZ ... 111 BT ... 112 BF ... 113 BTCLR ...114 DBNZ ... 115 [CPU control instructions] SEL RBn ... 117 NOP ... 118 EI ... 119 DI ... 120 HALT ... 121 STOP ...
APPENDIX C INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER) [A] [H] ADD ... 55 HALT ... 121 ADDC ... 56 ADDW ... 64 [I] ADJBA ... 83 ADJBS ... 84 INC ... 71 AND ... 59 INCW ... 73 AND1 ... 87 [M] [B] MOV ... 49 BC ... 108 MOVW ... 52 BF ... 113 MOVW AX, SP ... 104 BNC ... 109 MOVW SP, src ... 104 BNZ ... 111 MOV1 ... 86 BR ... 106 MULU ... 68 BRK ... 97 BT ... 112 [N] BTCLR ... 114 BZ ... 110 NOP ... 118 NOT1 ... 92 [C] [O] CALL ... 94 CALLF ... 95 OR ... 60 CALLT ...
APPENDIX C INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER) [S] SEL RBn ... 117 SET1 ... 90 STOP ... 122 SUB ... 57 SUBC ... 58 SUBW ... 65 [X] XCH ... 50 XCHW ... 53 XOR ... 61 XOR1 ...
[MEMO] 128 User's Manual U12326EJ4V0UM
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