USER'S MANUAL µPD750008 4 BIT SINGLE-CHIP MICROCOMPUTER µPD750004 µPD750006 µPD750008 µPD75P0016 © 1995 Document No. U10740EJ2V0UM00 (2nd edition) (Previous No.
GENERAL 1 PIN FUNCTIONS 2 FEATURES OF THE ARCHITECTURE AND MEMORY MAP 3 INTERNAL CPU FUNCTIONS 4 PERIPHERAL HARDWARE FUNCTIONS 5 INTERRUPT AND TEST FUNCTIONS 6 STANDBY FUNCTION 7 RESET FUNCTION 8 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) 9 MASK OPTION 10 INSTRUCTION SET 11 FUNCTIONS OF THE µPD75008, µPD750008, AND µPD75P0016 A DEVELOPMENT TOOLS B MASK ROM ORDERING PROCEDURE C INSTRUCTION INDEX D HARDWARE INDEX E RIVISION HISTORY F
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. The information in this document is subject to change without notice.
Major Changes Page All Description The 44-pin plastic QFP package has been changed from µPD750008GB-xxx-3B4 to µPD750008GB-xxx-3BS-MTX. The µPD75P0016 under development has been changed to the already-developed µPD75P0016. The input withstand voltage at ports 4 and 5 during open drain has been changed from 12 V to 13 V. Preface English-version document numbers have been added to "Related documents." p.4 The format of the table in Section 1.3 has been changed. p.
PREFACE Readers This manual is intended for engineers who want to learn the capabilities of the µPD750004, µPD750006, µPD750008, and µPD75P0016 to develop application systems based on them. Purpose The purpose of this manual is to help users understand the hardware capabilities (shown below) of the µPD750004, µPD750006, µPD750008, and µPD75P0016.
Notation Data bit significance : Higher-order bits on the left side Lower-order bits on the right side Active low Memory map address : xxx (Pin and signal names are overscored.) : Low-order address on the upper side Note High-order address on the lower side : Explanation of an indicated part of text Caution Remark : Information requesting the user's special attention : Supplementary information Important and emphasized matter : Described in bold face Numeric value : Binary ..................
Related documents Some documents are preliminary editions, but they are not so specified in the tables below.
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CONTENTS CHAPTER 1 CHAPTER 2 GENERAL ......................................................................................................................... 1 1.1 FUNCTION OVERVIEW ......................................................................................... 2 1.2 ORDERING INFORMATION................................................................................... 3 1.3 DIFFERENCES AMONG SUBSERIES PRODUCTS ............................................. 4 1.4 BLOCK DIAGRAM .....
CHAPTER 3 CHAPTER 4 CHAPTER 5 FEATURES OF THE ARCHITECTURE AND MEMORY MAP ....................................... 21 3.1 DATA MEMORY BANK STRUCTURE AND ADDRESSING MODES .................. 21 3.1.1 Data Memory Bank Structure .................................................................... 21 3.1.2 Data Memory Addressing Modes .............................................................. 23 3.2 GENERAL REGISTER BANK CONFIGURATION ................................................. 34 3.
5.4 5.5 5.6 5.7 5.3.5 Operation of the Watchdog Timer ............................................................. 102 5.3.6 Other Functions ......................................................................................... 103 CLOCK TIMER ........................................................................................................ 105 5.4.1 Configuration of the Clock Timer .............................................................. 106 5.4.2 Clock Mode Register ............
CHAPTER 8 RESET FUNCTION ........................................................................................................... 225 CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) ................................... 229 9.1 OPERATING MODES WHEN WRITING TO AND VERIFYING THE PROGRAM MEMORY .................................................................................... 230 * * CHAPTER 10 9.2 WRITING TO THE PROGRAM MEMORY .............................................................
APPENDIX A FUNCTIONS OF THE µPD75008, µPD750008, AND µPD75P0016 ............................ 299 APPENDIX B DEVELOPMENT TOOLS ................................................................................................ 301 APPENDIX C MASKED ROM ORDERING PROCEDURE ................................................................... 309 APPENDIX D INSTRUCTION INDEX .................................................................................................... 311 D.
LIST OF FIGURES (1/4) Figure No. Title Page 2-1 Pin Input/Output Circuits .................................................................................................. 18 3-1 Use of MBE = 0 Mode and MBE = 1 Mode ..................................................................... 22 3-2 Data Memory Organization and Addressing Range of Each Addressing Mode ............ 24 3-3 Updating Static RAM Addresses .....................................................................................
LIST OF FIGURES (2/4) Figure No. Title Page 5-9 I/O Timing Chart of Digital I/O Ports ................................................................................ 82 5-10 ON Timing Chart of Built-in Pull-Up Resistor Connected by Software .......................... 83 5-11 Block Diagram of the Clock Generator ............................................................................ 84 5-12 Format of the Processor Clock Control Register .....................................................
LIST OF FIGURES (3/4) Figure No. Title Page 5-45 Operations of RELT and CMDT ....................................................................................... 141 5-46 Transfer Bit Switching Circuit ........................................................................................... 141 5-47 Example of Two-Wire Serial I/O System Configuration .................................................. 144 5-48 Timing of Two-Wire Serial I/O Mode..................................................
LIST OF FIGURES (4/4) Figure No. Title Page 5-81 Format of the Bit Sequential Buffer ................................................................................. 181 6-1 Block Diagram of Interrupt Control Circuit ....................................................................... 184 6-2 Interrupt Vector Table ....................................................................................................... 185 6-3 Interrupt Priority Specification Register ...........................
LIST OF TABLES (1/2) Table No. Title Page 1-1 Features of the Products .................................................................................................. 1 2-1 Digital I/O Port Pins .......................................................................................................... 9 2-2 Non-Port Pin Functions .................................................................................................... 11 2-3 Connection of Unused Pins ...............................
LIST OF TABLES (2/2) Table No. Title Page 7-1 Operation Statuses in the Standby Mode ........................................................................ 216 7-2 Selection of a Wait Time with BTM .................................................................................. 219 8-1 Status of the Hardware after a Reset .............................................................................. 226 10-1 Selecting Mask Option of Pin .........................................................
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CHAPTER 1 GENERAL CHAPTER 1 GENERAL The µPD750004, µPD750006, µPD750008, and µPD75P0016 are 75XL series 4-bit single-chip microcomputers. The 75XL series is a successor of the 75X series consisting of many products. These µPD750004, µPD750006, µPD750008, and µPD75P0016 are collectively called the µPD750008 subseries. The 75XL series takes over the CPUs of the 75X series, realizing a wide range of operating voltages and high-speed operation.
µPD750008 USER'S MANUAL 1.1 FUNCTION OVERVIEW Item Function Instruction execution time • 0.95, 1.91, 3.81, 15.3 µs (when the main system clock operates at 4.19 MHz) • 0.67, 1.33, 2.67, 10.7 µs (when the main system clock operates at 6.0 MHz) • 122 µs (when the subsystem clock operates at 32.
CHAPTER 1 GENERAL 1.
µPD750008 USER'S MANUAL 1.3 DIFFERENCES AMONG SUBSERIES PRODUCTS Item µPD750004 µPD750006 µPD750008 µPD75P0016 Program counter 12 bits 13 bits Program memory (byte) Masked ROM 4096 Masked ROM 6144 Data memory (x 4 bits) 512 Mask option Pull-up resistors at ports 4 and 5 Incorporated (Whether to incorporate pull-up resistors can be specified.) None (Cannot be incorporated.) Wait time during RESET Available (Can be selected from 217 /fX or 215 /fX.) Note Not available (Fixed to 215 /fX.
CHAPTER 1 GENERAL 1.
µPD750008 USER'S MANUAL 1.
CHAPTER 1 GENERAL (2) 44-pin plastic QFP (10 x 10 mm) µPD750004GB-XXX-3BS-MTX µPD750006GB-XXX-3BS-MTX NC P12/INT2 P11/INT1 P10/INT0 VDD IC (VPP)Note P23/BUZ P22/PCL P21/PTO1 P20/PTO0 P73/KR7 µPD750008GB-XXX-3BS-MTX µPD75P0016GB-3BS-MTX 4 30 P02/SO/SB0 P62/KR2 5 29 P03/SI/SB1 P61/KR1 6 28 P80 P60/KR0 7 27 P81 P53 8 26 P30 (/MD0) P52 9 25 P31 (/MD1) P51 10 24 P32 (/MD2) P50 11 23 12 13 14 15 16 17 18 19 20 21 22 P33 (/MD3) P13/TI0 X2 X1 P01/SCK P63/KR3 XT2 31
µPD750008 USER'S MANUAL Pin name P00-P03 : Port 0 P10-P13 : Port 1 RESET TI0 : Reset input : Timer input 0 P20-P23 : Port 2 P30-P33 : Port 3 PTO0, 1 BUZ : Programmable timer output 0, 1 : Buzzer clock P40-P43 : Port 4 P50-P53 : Port 5 PCL : Programmable clock INT0, 1, 4 : External vectored interrupt 0, 1, 4 P60-P63 : Port 6 P70-P73 : Port 7 INT2 X1, 2 : External test input 2 : Main system clock oscillation 1, 2 P80-P81 : Port 8 KR0-KR7 : Key return XT1, 2 NC : Subsystem clock oscillation 1, 2
CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS 2.1 PIN FUNCTIONS OF THE µPD750008 2 Table 2-1. Digital I/O Port Pins (1/2) Also used as Input/ output Pin Function 8 bit I/O Input INT4 4-bit input port (PORT0). P01 I/O SCK For P01 to P03, built-in pull-up resistors P02 I/O SO/SB0 can be connected by software in units of F -B P03 I/O SI/SB1 3 bits. M -C P10 Input INT0 4-bit input port (PORT1).
µPD750008 USER'S MANUAL Table 2-1. Digital I/O Port Pins (2/2) Input output Pin * Also used as 8 bit I/O Upon reset I/O circuit type Note 1 P40P43 Note 2, 4 I/O — N-ch open-drain 4-bit I/O port (PORT4). Withstand voltage is 13 V in open-drain mode. A pull-up resistor can be provided bit by bit (mask option)Note 5. Data input/output pins for writing/ verifying (lower 4 bits of program memory (PROM).
CHAPTER 2 PIN FUNCTIONS Table 2-2.
µPD750008 USER'S MANUAL 2.2 2.2.1 PIN FUNCTIONS P00-P03 (PORT0) : Input Pins Used Also for INT4, SCK, SO/SB0 and SI/SB1 P10-P13 (PORT1) : Input Pins Used Also for INT0-INT2, and TI0 These are the input pins of the 4-bit input ports: Ports 0 and 1. Ports 0 and 1 function as input ports, and also have the functions described below.
CHAPTER 2 PIN FUNCTIONS 2.2.2 P20-P23 (PORT2) : I/O Pins Used Also for PTO0, PTO1, PCL, and BUZ P30-P33 (PORT3) : I/O Pins Used Also for MD0-MD3Note P40-P43 (PORT4), P50-P53 (PORT5) : N-ch Open-Drain Intermediate Withstand Voltage (13 V) Large-Current * Output P60-P63 (PORT6), P70-P73 (PORT7) : Tristate I/O These pins are the I/O pins of the 4-bit I/O ports with output latches: Ports 2 to 7.
µPD750008 USER'S MANUAL 2.2.6 PCL: Output Pin Used Also for Port 2 This is the programmable clock output pin. It is used to supply the clock pulse to a peripheral LSI circuit such as a slave microcomputer or A/D converter. A RESET signal clears the clock mode register (CLOM) to 0, disabling clock output, then the pin is placed in the normal mode to function as a normal port. 2.2.7 BUZ: Output Pin Used Also for Port 2 An arbitrary frequency (2.048, 4.096, or 32.
CHAPTER 2 PIN FUNCTIONS INT0 has a noise eliminator. Two different sampling clocks for noise elimination can be switched. The acceptable width of a signal depends on the CPU clock. INT1 is an asynchronous input, and can accept a signal with some high level width regardless of what the CPU clock is. A RESET input clears IM0 and IM1 to 0, selecting rising edge active. The INT1 pin can also be used to release the STOP and HALT modes, but the INT0 pin cannot.
µPD750008 USER'S MANUAL 2.2.14 XT1, XT2 These pins are used for connection to a crystal for subsystem clock oscillation. An external clock can also be applied. (a) Crystal oscillation (b) External clock µPD750008 VSS XT1 XT2 Crystal 2.2.15 µPD750008 External clock XT1 XT2 (Standard frequency: 32.768 kHz) RESET This is the pin for active-low reset input. The RESET input is asynchronous.
CHAPTER 2 PIN FUNCTIONS 2.2.18 IC (for the µPD750004, µPD750006, and µPD750008 only) The internally connected (IC) pin is used to set the µPD750008 to test mode for inspection prior to shipping. In normal operation, connect the IC pin to the VDD pin, keeping the writing as short as possible. When the wiring between the IC pin and the VDD pin is too long, or noise is generated on the IC pin, a potential difference may occur between the IC pin and the VDD pin. This may cause your program to malfunction.
µPD750008 USER'S MANUAL 2.3 PIN INPUT/OUTPUT CIRCUITS Figure 2-1 shows schematic diagrams of the I/O circuitry of the µPD750008. Figure 2-1. Pin Input/Output Circuits (1/2) Type B-C Type A VDD VDD P.U.R. P-ch P.U.R. enable P-ch IN N-ch IN CMOS input buffer P.U.R.
CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin Input/Output Circuits (2/2) Type M-C VDD Type E-B VDD P.U.R. P.U.R. enable P.U.R. P.U.R. enable P-ch Data P-ch IN/OUT IN/OUT Type D Data Output disable N-ch Output disable Type A P.U.R.: Pull-Up Resistor Type F-A P.U.R.: Pull-Up Resistor Type M-D* VDD P.U.R. P.U.R. enable VDD Input instruction P.U.R. (Mask option) P-ch Data IN/OUT Type D P-ch VDD Data N-ch (Withstand voltage:13 V) Output disable Output disable P.U.
µPD750008 USER'S MANUAL 2.4 CONNECTION OF UNUSED PINS Table 2-3.
CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP The 75XL series architecture of the µPD750008 has the following features: • Internal RAM of up to 4K words x 4 bits (12-bit address) • Peripheral hardware expansibility 3 To provide these features, the following are used: (1) Data memory bank structure (2) General register bank structure (3) Memory-mapped I/O This chapter explains these topics. 3.1 3.1.
µPD750008 USER'S MANUAL Applicable program processing MBE = 0 mode MBE = 1 mode Effect • Interrupt processing MBS save/restoration becomes unnecessary. • Processing that repeats internal hardware and static RAM operations MBS modification becomes unnecessary. • Subroutine processing MBS save/restoration becomes • Usual program processing Figure 3-1.
CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP 3.1.2 Data Memory Addressing Modes With the architecture of the µPD750008, seven addressing modes summarized in Figures 3-2 and 3-3, and Table 3-1 are available to address data memory space efficiently for each bit length of data to be processed. These addressing modes enable more efficient programming. (1) 1-bit direct addressing (mem.
µPD750008 USER'S MANUAL Figure 3-2. Data Memory Organization and Addressing Range of Each Addressing Mode Addressing mode Memory bank enable flag 000H 01FH 020H 07FH mem mem.bit MBE =0 MBE =1 @HL @H+mem.bit MBE =0 MBE =1 @DE @DL — Stack address- fmem.bit pmem.
CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Table 3-1. Addressing Modes Addressing mode 1-bit direct addressing Representation format mem.bit Specified address Bit specified by bit at the address specified by MB and mem. • When MBE = 0 and mem = 00H-7FH, MB = 0 mem = 80H-FFH, MB = 15 • When MBE = 1, 4-bit direct addressing mem Address specified by MB and mem.
µPD750008 USER'S MANUAL (2) 4-bit direct addressing (mem) In this addressing mode, the operand of an instruction directly specifies any area in the data memory space in units of four bits. As with the 1-bit direct addressing mode, in the MBE = 0 mode, a fixed space consisting of the static RAM area ranging from 000H to 07FH and the peripheral hardware area ranging from F80H to FFFH can be addressed. In the MBE = 1 mode, MB = MBS, and specifiable data memory space can be expanded to the entire space.
CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Example 2. Eight-bit data is latched into the serial interface shift register (SIO), and the transfer data is set at the same time. SEL XCH MB15 XA,SIO ; MBS <– 15 ; XA <—> (SIO) (4) 4-bit register indirect addressing (@rpa) In this addressing mode, the pointer (general register pair) specified in the operand of an instruction indirectly specifies a data memory space in units of four bits. There are three types of data pointers.
µPD750008 USER'S MANUAL Example 2. The data memory of 00H to FFH is cleared to 0. CLR1 RBE LOOP: CLR1 MOV MBE XA,#00H MOV MOV HL,#04H @HL,A INCS BR HL LOOP ; (HL) <– A ; HL <– HL + 1 Figure 3-3.
CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP (5) 8-bit register indirect addressing (@HL) In this addressing mode, the data pointer (HL register pair) indirectly specifies any area in the data memory space in units of eight bits. The 4-bit data at the address determined with bit 0 of the data pointer (bit 0 of the L register) set to 0 and the 4-bit data at the address incremented by 1 are processed as a pair on an 8-bit basis with the 8-bit accumulator (XA register pair).
µPD750008 USER'S MANUAL (a) Specific address bit direct addressing (fmem.bit) In this addressing mode, peripheral equipment that frequently performs bit manipulations involving, for example, I/O ports and interrupt flags, can be processed at all times regardless of memory bank setting. Accordingly, the data memory addresses that allow this addressing mode to be used are FF0H to FFFH where I/O ports are mapped, and FB0H to FBFH where interrupt-related hardware is mapped.
CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP (b) Specific address bit register indirect addressing (pmem.@L) In this addressing mode, the bits of peripheral hardware I/O ports are indirectly specified using a register to allow continuous manipulations. This addressing mode can be applied to data memory addresses FC0H to FFFH.
µPD750008 USER'S MANUAL (c) Specific 1-bit direct addressing (@H+mem.bit) This addressing mode enables any bit in the data memory space to be manipulated. In this addressing mode, the high-order four bits of the data memory address in the memory bank specified by MB = MBE·MBS are indirectly specified using the H register, and the low-order four bits and bit address are directly specified in the operand.
CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP (7) Stack addressing This addressing mode is used for save/restoration operation in interrupt processing or subroutine processing. In this addressing mode, the address indicated by the stack pointer (8 bits) of data memory bank 0 is specified. This addressing mode can be used for register save/restoration operation using the PUSH or POP instruction as well as save/restoration operation in interrupt and subroutine processing. Examples 1.
µPD750008 USER'S MANUAL 3.2 GENERAL REGISTER BANK CONFIGURATION The µPD750008 contains four register banks, each consisting of eight general registers: X, A, B, C, D, E, H, and L. These registers are mapped to addresses 00H to 1FH in memory bank 0 of the data memory (see Figure 3-5). To specify a general register bank, a register bank enable flag (RBE) and a register bank select register (RBS) are contained.
CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Figure 3-4.
µPD750008 USER'S MANUAL (2) When used as an 8-bit register When the general register area is used on an 8-bit basis, the register pairs in the register bank specified by RBE·RBS can be specified as XA, BC, DE, and HL as shown in Figure 3-6, and the register pairs in the register bank that has the inverted value of bit 0 of the register bank (RB) can be specified as XA’, BC’, DE’, and HL’, thus providing up to eight 8-bit registers.
CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Figure 3-5.
µPD750008 USER'S MANUAL Figure 3-6.
CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP 3.3 MEMORY-MAPPED I/O The µPD750008 employs memory-mapped I/O, which maps peripheral hardware such as timers and I/O ports to addresses F80H to FFFH in data memory space as shown in Figure 3-2. This means that there is no particular instruction to control peripheral hardware, but all peripheral hardware is controlled using memory manipulation instructions. (Some mnemonics for hardware control are available to make programs readable.
µPD750008 USER'S MANUAL Figure 3-7. µPD750008 I/O Map (1/5) Hardware name (symbol) Address R/ W b3 b2 b1 b0 Number of bits that can be manipulated 1 bit 4 bits 8 bits Bit manipulation addressing F80H Stack pointer (SP) F82H R/ W Register bank selection register (RBS) Bank selection register (BS) – – – Remarks Bit 0 is fixed to 0.
CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Figure 3-7. µPD750008 I/O Map (2/5) Hardware name (symbol) Address R/W b3 b2 b1 b0 Number of bits that can be manipulated 1 bit FA0H Timer/event counter mode register (TM0) (W) 8 bits – R/W Remarks mem.bit Bit write manipulation is enabled only for bit 3. (R/W) – FA2H 4 bits Bit manipulation addressing – – TOE0Note 1 W Timer/event counter count register (T0) R – – – R/W – – – – mem.bit – – mem.
µPD750008 USER'S MANUAL Figure 3-7. µPD750008 I/O Map (3/5) Hardware name (symbol) Address FB0H R/W b3 b2 b1 b0 IST1 IST0 MBE RBE R/W Program status word (PSW) CY SK2 SK1 SK0 Number of bits that can be manipulated 1 bit 4 bits (R/W) (R/W) – – 8 bits Bit manipulation addressing Remarks Manipulation in 8-bit units is enabled only for reading. (R) fmem.
CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Figure 3-7. µPD750008 I/O Map (4/5) Hardware name (symbol) Address R/ W b3 FD0H FDCH FDEH FE0H b2 b1 b0 Number of bits that can be manipulated 1 bit 4 bits 8 bits Bit manipulation addressing – – Clock output mode register (CLOM) R/W – Pull-up resistor specification register group A (POGA) R/W – – – Pull-up resistor specification register group B (POGB) R/W – – – – – – – mem.
µPD750008 USER'S MANUAL Figure 3-7.
CHAPTER 4 INTERNAL CPU FUNCTIONS CHAPTER 4 INTERNAL CPU FUNCTIONS 4.1 Mk I MODE/Mk II MODE SWITCH FUNCTIONS 4.1.1 Differences between Mk I Mode and Mk II Mode The CPU of the µPD750008 subseries has two modes (Mk I mode and Mk II mode) and which mode is used is selectable. Bit 3 of the stack bank selection register (SBS) determines the mode. 4 • Mk I mode: This mode has the upward compatibility with the µPD75008 subseries. It can be used in the 75XL CPUs having a ROM of up to 16KB.
µPD750008 USER'S MANUAL 4.1.2 Setting of the Stack Bank Selection Register (SBS) The Mk I mode and Mk II mode are switched by stack bank selection register. Figure 4-1 shows the register configuration. The stack bank selection register is set with a 4-bit memory operation instruction. To use the CPU in Mk I mode, initialize the register to 10xxBNote at the beginning of the program. To use the CPU in Mk II mode, initialize it to 00xxBNote. Figure 4-1.
CHAPTER 4 INTERNAL CPU FUNCTIONS 4.2 PROGRAM COUNTER (PC): 12 BITS (µPD750004) 13 BITS (µPD750006 AND µPD750008) 14 BITS (µPD75P0016) The program counter is a binary counter which retains the address data of the program memory. The program counter consists of 12 bits in the µPD750004 (see Figure 4-2(a)), 13 bits in the µPD750006 and µPD750008 (see Figure 4-2(b)), and 14 bits in the µPD75P0016 (see Figure 4-2(c)). Figure 4-2.
µPD750008 USER'S MANUAL 4.3 PROGRAM MEMORY (ROM): 4096 WORDS x 8 BITS (µPD750004: MASKED ROM) 6144 WORDS x 8 BITS (µPD750006: MASKED ROM) 8192 WORDS x 8 BITS (µPD750008: MASKED ROM) 16384 WORDS x 8 BITS (µPD75P0016: ONE-TIME PROM) The program memory is used for storing programs, an interrupt vector table, GETI instruction reference table, table data, and so forth.
CHAPTER 4 INTERNAL CPU FUNCTIONS Figure 4-3.
µPD750008 USER'S MANUAL Figure 4-4.
CHAPTER 4 INTERNAL CPU FUNCTIONS Figure 4-5.
µPD750008 USER'S MANUAL Figure 4-6.
CHAPTER 4 INTERNAL CPU FUNCTIONS 4.4 DATA MEMORY (RAM): 512 WORDS x 4 BITS The data memory consists of a data area and peripheral hardware area as shown in Figure 4-7. The data memory consists of the following memory banks with each bank made of 256 words x 4 bits. • Memory banks 0 and 1 (data area) • Memory bank 15 (peripheral hardware area) 4.4.
µPD750008 USER'S MANUAL 4.4.2 Specification of a Data Memory Bank If the memory bank enable flag (MBE) enables bank specification (MBE = 1), a memory bank is specified with the 4-bit memory bank select register (MBS = 0, 1, 15). If the MBE disables bank specification (MBE = 0), memory bank 0 or 15 is automatically selected according to the addressing mode. Locations in a bank is addressed by 8-bit immediate data or a register pair.
CHAPTER 4 INTERNAL CPU FUNCTIONS Data memory is undefined when it is reset. For this reason, it is to be initialized to zero (RAM clear) usually at the start of a program. Remember to perform this initialization. Otherwise, unexpected bugs may occur. Example The following program clears data at addresses 000H to 1FFH in RAM.
µPD750008 USER'S MANUAL 4.5 GENERAL REGISTER: 8 x 4 BITS x 4 BANKS The general registers are mapped to particular addresses in data memory. Four banks of registers are provided, with each bank consisting of eight 4-bit registers (B, C, D, E, H, L, X, and A). The register bank (RB) to be enabled at the time of instruction execution is determined by: RB = RBE·RBS: (RBS = 0 to 3) Each general register allows 4-bit manipulation. In addition, BC, DE, HL, or XA serves as a register pair for 8-bit manipulation.
CHAPTER 4 INTERNAL CPU FUNCTIONS Figure 4-9. Register Pair Format 3 0 3 0 B 3 C 0 3 0 D 3 E 0 3 0 H 3 L 0 3 0 X 4.6 One bank A ACCUMULATOR In the µPD750008, the A register and XA register pair function as accumulators. The A register is mainly used for 4-bit data processing instructions, and the XA register pair is mainly used for 8-bit data processing instructions. For a bit manipulation instruction, the carry flag (CY) functions as a bit accumulator. Figure 4-10.
µPD750008 USER'S MANUAL 4.7 STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS) The µPD750008 uses static RAM as stack memory (LIFO scheme), and the 8-bit register holding the start address of the stack area is the stack pointer (SP). The stack area is located at addresses 000H to 1FFH in memory banks 0 and 1. One memory bank is selected according to the value of the 2-bit SBS. (See Table 4-2.) Table 4-2.
CHAPTER 4 INTERNAL CPU FUNCTIONS Figure 4-11. Format of Stack Pointer and Stack Bank Select Register Address Symbol SP7 F80H SP6 SP5 SP4 SP3 Note F84H SBS3 SP2 SP1 0 SP 0 SBS1 SBS0 SBS 000H SBS Memory bank 0 SP Memory bank 1 SP 0FFH 100H 1FFH Note The Mk I mode and Mk II mode can be switched by bit 3 of SBS. The stack bank selection function can be used in both Mk I mode and Mk II mode. (See Section 4.1 for details.
µPD750008 USER'S MANUAL Figure 4-13.
CHAPTER 4 INTERNAL CPU FUNCTIONS Figure 4-15.
µPD750008 USER'S MANUAL 4.8 PROGRAM STATUS WORD (PSW): 8 BITS The program status word (PSW) consists of various flags closely associated with processor operations. The PSW is mapped to addresses FB0H and FB1H in data memory space. Four bits at address FB0H can be manipulated with a memory manipulation instruction. Figure 4-16.
CHAPTER 4 INTERNAL CPU FUNCTIONS Table 4-4. Carry Flag Manipulation Instructions Instruction (mnemonic) Carry flag operation/processing Instruction dedicated to carry flag manipulation SET1 CLR1 NOT1 SKT CY CY CY CY Sets CY to 1. Clears CY to 0. Inverts the state of CY. Skips if CY is 1. Bit transfer instruction MOV1 MOV1 mem*.bit, CY CY, mem*.bit Transfers the state of CY to a specified bit. Transfers the state of a specified bit to CY. Bit Boolean instruction AND1 OR1 XOR1 CY, mem*.
µPD750008 USER'S MANUAL Table 4-5. Information Indicated by the Interrupt Status Flag IST1 IST0 0 0 Status of processing Status 0 Processing and interrupt control being performed Normal program processing is being performed. Any interrupts are acceptable. 0 1 Status 1 A lower- or higher-priority interrupt is being serviced. Higher-priority interrupts are acceptable. 1 0 Status 2 A higher-priority interrupt is being serviced. No interrupts are acceptable.
CHAPTER 4 INTERNAL CPU FUNCTIONS When the RBE is reset to 0, register bank 0 is always selected as general registers, regardless of the setting of the RBS. A RESET signal automatically initializes the RBE by setting the RBE to the state of bit 6 at program memory address 0. When a vectored interrupt occurs, the RBE is automatically set to the state of bit 6 in the vector address table for servicing the interrupt. Usually, the RBE is set to 0 in interrupt processing.
µPD750008 USER'S MANUAL Table 4-6. Register Bank to Be Selected with the RBE and RBS RBS RBE Register bank 3 2 1 0 0 0 0 x x Bank 0 is always selected. 1 0 0 0 0 Bank 0 is selected. 0 1 Bank 1 is selected. 1 0 Bank 2 is selected. 1 1 Bank 3 is selected.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.1 DIGITAL I/O PORTS The µPD750008 employs the memory mapped I/O method. Thus, all input/output ports are mapped on the data memory space. Figure 5-1.
µPD750008 USER'S MANUAL 5.1.1 Types, Features, and Configurations of Digital I/O Ports Table 5-1 lists the types of digital I/O ports. Figures 5-2 to 5-6 show the configurations of the ports. Table 5-1. Types and Features of Digital Ports Port name (symbol) PORT0 Function 4-bit I/O Operation and feature Allows read and test at any timeregard less of the operation modes of another functions assigned to these pins. PORT1 Also used as INT4, SCK, SO/SB0, and SI/SB1. Also used as INT0 to INT2 and TI0.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-2.
µPD750008 USER'S MANUAL Figure 5-3.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-4.
µPD750008 USER'S MANUAL Figure 5-5.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-6.
µPD750008 USER'S MANUAL 5.1.2 I/O Mode Setting The I/O mode of each I/O port is set by the port mode register as shown in Figure 5-7. The I/O modes of ports 3 and 6 can be set bit by bit by port mode register group A (PMGA). The I/O modes of ports 2, 4, 5, and 7 can be set in units of four bits by port mode register group B (PMGB). The I/O mode of port 8 can be set in units of two bits by port mode register group C (PMGC).
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-7.
µPD750008 USER'S MANUAL 5.1.3 Digital I/O Port Manipulation Instructions All I/O ports contained in the µPD750008 are mapped to data memory space, so that all data memory manipulation instructions can be used. Table 5-3 lists the instructions that are particularly useful for I/O pin manipulation and their application ranges. (1) Bit manipulation instructions For digital I/O ports PORT0 to PORT8, specific address bit direct addressing (fmem.bit) and specific address bit register indirect addressing (pmem.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (3) 8-bit manipulation instructions The MOV, XCH, and SKE instructions as well as the IN and OUT instructions can be used for ports 4 and 5 that allow 8-bit manipulation. As with 4-bit manipulation, memory bank 15 must be selected in advance. Example The data contained in the BC register pair is output on the output port specified by 8-bit data applied to ports 4 and 5.
µPD750008 USER'S MANUAL Table 5-2. I/O Pin Manipulation Instructions PORT Instruction PORT 0 IN A, PORTn Note 1 IN XA, PORTn Note 1 — OUT PORTn, A Note 1 — OUT PORTn, XA Note 1 — SET1 PORTn.bit SET1 PORTn.@L CLR1 PORTn.@L SKT PORTn.bit SKT PORTn.@L SKF PORTn.bit SKF PORTn.@L PORT 2 PORT 3 PORT 4 PORT 5 PORT 6 PORT 7 PORT 8 — — — — — Note 2 — CLR1 PORTn.bit * * * * PORT 1 — Note 2 — Note 2 Note 2 MOV1 CY, PORTn.bit MOV1 CY, PORTn.@L Note 2 MOV1 PORTn.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.1.4 Digital I/O Port Operation When a data memory manipulation instruction is executed for a digital I/O port, the operation of the port and pins depends on the I/O mode setting (Table 5-3). This is because data taken in on the internal bus is the data input from the pins in the input mode, or the output latch data in the output mode, as obvious from the configurations of I/O ports.
µPD750008 USER'S MANUAL Table 5-3. Operations by I/O Port Manipulation Instructions Port and pin operation Instruction Input mode SKT SKF * * <1> <1> Output mode Pin data is tested. Output latch data is tested. MOV1 CY, <1> Pin data is transferred to CY. Output latch data is transferred to CY. AND1 CY, OR1 CY, XOR1 CY, <1> <1> <1> An operation is performed on pin data and CY. An operation is performed on output latch data and CY.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.1.5 Specification of Bilt-in Pull-Up Resistors A pull-up resistor can be contained at each port pin of the µPD750008 (except for P00). Whether to use the pull-up resistor can be specified by software (for some pins) or a mask option (for the other pins). Table 5-4 shows how a built-in pull-up resistor is specified for each port pin. The built-in pull-up resistor is connected by software in the format shown in Figure 5-8. Table 5-4.
µPD750008 USER'S MANUAL Figure 5-8.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-9.
µPD750008 USER'S MANUAL 5.2 CLOCK GENERATOR The clock generator supplies various clock signals to the CPU and peripheral hardware to control the CPU operation mode. 5.2.1 Clock Generator Configuration Figure 5-11 shows the configuration of the clock generator. Figure 5-11. Block Diagram of the Clock Generator • • • • • • • XT1 XT2 Subsystem clock generator fXT Main system clock generator fX Clock timer X1 X2 WM.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.2.2 Functions and Operations of the Clock Generator The clock generator generates the following clocks, and controls the CPU operation modes such as the standby mode. • Main system clock fX • Subsystem clock fXT • CPU clock F • Clock to peripheral hardware The operation of the clock generator is determined by the processor clock control register (PCC) and system clock control register (SCC).
µPD750008 USER'S MANUAL (1) Processor clock control register (PCC) The PCC is a 4-bit register for selecting a CPU clock F with the low-order two bits and for controlling the CPU operation mode with the high-order two bits (see Figure 5-12). When bit 3 or bit 2 is set to 1, the standby mode is set. When the standby mode is released by the standby release signal, these bits are automatically cleared to return to the normal operation mode. (See Chapter 7 for details.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-12. Format of the Processor Clock Control Register Address FB3H 3 PCC3 2 1 Symbol 0 PCC2 PCC1 PCC0 PCC CPU clock selection bit (Operation with fX = 6.0 MHz) SCC3, SCC0 = 00 ( ) is actual frequency at fX = 6.0 MHz SCC3, SCC0 = 01 or 11 ( ) is actual frequency at fXT = 32.768 kHz CPU clock frequency 1 machine cycle CPU clock frequency 1 machine cycle Φ = fXT/4 (8.192 kHz) 122 µs 0 0 Φ = fX /64 (93.7 kHz) 10.
µPD750008 USER'S MANUAL (2) System clock control register (SCC) The SCC is a 4-bit register for selecting CPU clock F with the least significant bit and for controlling the termination of main system clock generation with the most significant bit (see Figure 5-13). Bits 0 and 3 of the SCC are located at the same data memory address, but both bits cannot be changed at the same time. Accordingly, bits 0 and 3 of the SCC are set using bit manipulation instructions.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (3) System clock oscillator The main system clock oscillator operates with a crystal resonator or ceramic resonator connected to the X1 and X2 pins. An external clock can also be input. Input the clock signal to the X1 pin and the reversed signal to the X2 pin. Figure 5-14.
µPD750008 USER'S MANUAL Any line carrying a high pulsating current must be kept away as far as possible. • The grounding point of the capacitor of the oscillator must have the same potential as that of VSS. It must not be grounded to a grounding pattern carry ing a high current. • No signal must be taken directly from the resonator. The subsystem clock oscillator has low amplification to minimize current consumption.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-16. Examples of Oscillator Connections Which Should Be Avoided (2/2) (c) A high pulsating current is too close to the signal line. (d) The current flows through the ground line of the oscillator. (The potential at points A, B, and C fluctuates.) VDD µPD750008 µPD750008 VSS X1 Pnm VSS X2 X1 X2 High current A B C High current (e) A signal is taken directly from the resonator.
µPD750008 USER'S MANUAL (4) Frequency divider The frequency divider divides the output (fX) of the main system clock oscillator to generate various clocks. (5) Control functions of subsystem clock oscillator The subsystem clock oscillator of the µPD750008 subseries has two control functions to decrease the supply current.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (6) Sub-oscillator control register (SOS) The SOS register specifies whether to use the built-in feedback register and controls the drive current of the built-in inverter. (See Figure 5-18.) Inputting a RESET signal clears all bits of the SOS register. The functions of each flag in the SOS register are described below. (a) SOS.0 (feedback resistor cut flag) To use the feedback resistor of the subsystem clock, the mask option setup and switching SOS.
µPD750008 USER'S MANUAL 5.2.3 System Clock and CPU Clock Setting (1) Time required to change the system clock and CPU clock The system clock and CPU clock can be changed by using the least significant bit of the SCC and the low-order two bits of the PCC. This switching is not performed immediately after the contents of the registers are rewritten, but the system operates with the previous clock for some machine cycles.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (2) Procedure for changing the system clock and CPU clock The procedure for changing the system clock and CPU clock is explained using Figure 5-19. Figure 5-19. Changing the System Clock and CPU Clock Commercial power line voltage ON OFF VDD pin voltage RESET signal Wait Note 1 System clock CPU clock fX = 6.00 MHz fXT = 32.768 kHz fX fX f XT fX 10.7 µs 0.67 µs 122 µs 0.
µPD750008 USER'S MANUAL 5.2.4 Clock Output Circuit (1) Configuration of the clock output circuit Figure 5-20 shows the configuration of the clock output circuit. (2) Functions of the clock output circuit The clock output circuit outputs a clock pulse signal on the P22/PCL pin to output remote control signals or to supply clock pulses to a peripheral LSI device. The procedure for outputting a clock pulse signal is as follows: (a) Select a clock output frequency, and disable clock output.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (3) Clock output mode register (CLOM) The CLOM is a 4-bit register to control clock output. The CLOM is set by a 4-bit memory manipulation instruction. No read operation is allowed on this register. CPU clock F is output on the PCL/P22 pin. SEL MB15 ; or CLR1 MBE Example MOV MOV A,#1000B CLOM,A A RESET signal clears the CLOM to 0, disabling clock output. Figure 5-21.
µPD750008 USER'S MANUAL (4) Application to remote control output The clock output function of the µPD750008 is applicable to remote control output. The frequency of the carrier for remote control output is selected by the clock frequency select bit of the clock output mode register. Pulse output is enabled or disabled by controlling the clock output enable/disable bit by software. The clock output circuit is designed so that pulses with short widths do not appear in enabling or disabling clock output.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.3 BASIC INTERVAL TIMER/WATCHDOG TIMER The µPD750008 contains an 8-bit basic interval timer/watchdog timer, which has the following functions: (a) Interval timer operation which generates a reference timer interrupt (b) Operation as a watchdog timer for detecting program crashes and resetting the CPU (c) Selection of a wait time for releasing the standby mode, and counting (d) Reading the count value 5.3.
µPD750008 USER'S MANUAL When bit 3 is set to 1, the BT is cleared, and the basic interval ltimer/watchdog timer interrupt request flag (IRQBT) is also cleared (to start the basic interval timer/watchdog timer). A RESET signal clears the interval timer to 0, and the longest interrupt request signal generation interval time is set. Figure 5-24. Format of the Basic Interval Timer Mode Register Address F85H 3 2 1 0 BTM3 BTM2 BTM1 BTM0 Symbol BTM (fX = 6.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.3.3 Watchdog Timer Enable Flag (WDTM) WDTM, when set, is a flag for enabling the generation of the reset signal when the basic interval timer overflows. WDTM is set by a bit manipulation instruction. It cannot be cleared by an instruction. Example Set the watchdog timer function. SEL MB15 ; or CLR1 MBE SET1 SET1 WDTM · · · BTM.3 ; Set bit 3 of BTM to 1 The generation of a RESET signal clears WDTM to 0. Figure 5-25.
µPD750008 USER'S MANUAL 5.3.5 Operation of the Watchdog Timer When WDTM is set to 1, the basic interval timer/watchdog timer functions as a watchdog timer. An internal * reset signal is generated when the basic interval timer (BT) overflows. No reset signal, however, is generated during the oscillation wait time following the STOP instruction has been released (WDTM cannot be cleared without using reset). BT is constantly incremented by the clock supplied from the clock generator.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Module 1: ······ SET1 MBE SEL MB15 SET1 BTM.3 Processing completes within 5.46 ms. Module 2: ······ SET1 MBE SEL MB15 SET1 BTM.3 Processing completes within 5.46 ms. ··· 5.3.
µPD750008 USER'S MANUAL (2) Reading the count The count status of the basic interval timer (BT) can be read by using an 8-bit manipulation instruction. No data can be loaded to the timer. Caution When reading the count value of BT, execute a read instruction twice so that unstable data which has been counted will not be read. If the two read values are reasonable, use the second one as the result. If the two read values are far apart, retry from the beginning. Examples 1. Read the count value of BT.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.4 MOV MOV XA, BC BUFF, XA ; Store data SET1 RETI FLAG ; Set data presence flag CLOCK TIMER The µPD750008 contains one clock timer, which has the following functions. (a) The clock timer sets the test flag (IRQW) every 0.5 seconds. The IRQW can release the standby mode. (b) Either the main system clock or the subsystem clock can be used to produce 0.5-second intervals. Use a main system clock of 4.194304 MHz.
µPD750008 USER'S MANUAL 5.4.1 Configuration of the Clock Timer Figure 5-26 shows the configuration of the clock timer. Figure 5-26. Block Diagram of the Clock Timer fw 27 From the clock generator fX 128 (32.768 kHz) (256 Hz: 3.91 ms) fw fW (32.768 kHz) 214 Selector INTW IRQW set signal Selector Frequency divider fXT (32.768 kHz) 2 Hz 0.5 sec (4 kHz) (2 kHz) fw fw 23 24 Clear signal Selector Output buffer P23/BUZ WM WM7 PORT2.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Example Time is set using the main system clock (4.19 MHz), and buzzer output is enabled: CLR1 MBE MOV MOV XA, #84H WM, XA ; Sets WM Figure 5-27. Clock Mode Register Format Address F98H Symbol 7 6 5 4 3 2 1 0 WM7 0 WM5 WM4 WM3 WM2 WM1 WM0 WM BUZ output enable/disable bit WM7 0 Disables BUZ output 1 Enables BUZ output BUZ output frequency selection bit WM5 WM4 BUZ output frequency 0 0 fW (2.048 kHz) 24 0 1 fW (4.
µPD750008 USER'S MANUAL 5.5 TIMER/EVENT COUNTER The µPD750008 has one timer/event counter channel (channel 0) and one timer counter channel (channel 1). Figures 5-28 and 5-29 show the configuration of these channels. In this section, the timer/event counter and timer counters are referred to as "timer/event counters." When you read this section for description of channel 1, take "timer/event counter" as "timer counter." The timer/event counter has the following functions.
TI0 Input buffer Port input buffer From the clock generator MPX TM0 8 Timer operation start signal TM06 TM05 TM04 TM03 TM02 8 CP T0 Clear signal Count register (8) 8 Comparator (8) 8 Match TMOD0 Modulo register (8) 8 Internal bus Reset TOUT flip-flop TOUT0 TO enable flag TOE0 Figure 5-28.
110 From the clock generator MPX TM1 8 Timer operation start signal TM16 TM15 TM14 TM13 TM12 8 CP Clear signal Count register (8) 8 Comparator (8) 8 T1 TMOD1 Modulo register (8) 8 Internal bus Match Reset TOUT flip-flop TOE1 TO enable flag Figure 5-29. Block Diagram of the Timer Counter (Channel 1) IRQT1 clear signal RESET IRQT1 set signal INTT1 Output buffer P21/PTO1 Bit 2 of PMGB Port 2 input/ output mode PORT2.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (1) Timer/event counter mode register (TM0, TM1) The mode register (TMn) is an 8-bit register which controls the timer/event counter. Its format is shown in Figures 5-30 and 5-31. The timer/event counter mode register is set by an 8-bit memory manipulation instruction. Bit 3 is a timer start bit and can be operated bit-wise. It is automatically reset to 0 when the timer operation starts.
µPD750008 USER'S MANUAL Figure 5-30. Timer/Event Counter Mode Register (Channel 0) Format Address FA0H 7 6 5 TM06 TM05 4 3 TM04 TM03 2 1 0 TM02 Symbol TM0 Count pulse (CP) selection bit When fX = 6.00 MHz TM06 TM05 TM04 0 0 0 TI0 rising edge 0 0 1 TI0 falling edge 1 0 0 fX/210 (5.86 kHz) 1 0 1 fX/28 (23.4 kHz) 1 1 0 fX/26 (93.8 kHz) 1 1 1 fX/24 (375 kHz) Other than above Count pulse (CP) Not to be set When fX = 4.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-31. Timer Counter Mode Register (Channel 1) Format Address FA8H 7 6 5 TM16 TM15 4 3 2 TM14 TM13 1 0 TM12 Symbol TM1 Count pulse (CP) select bit When fX = 6.00 MHz TM16 TM15 Count pulse (CP) TM14 12 1 0 0 fX/2 (1.46 kHz) 1 0 1 fX/210 (5.86 kHz) 1 1 0 fX/28 (23.4 kHz) 1 1 1 fX/26 (93.8 kHz) Other than above Not to be set When fX = 4.19 MHz TM16 TM15 TM14 Count pulse (CP) 12 1 0 0 fX/2 (1.02 kHz) 1 0 1 fX/210 (4.
µPD750008 USER'S MANUAL (2) Timer/event counter output enable flag (TOE0, TOE1) The timer/event counter output enable flag (TOE0, TOE1) controls the output enable/disable to the PTO0 and PTO1 pins in the timer out flip-flop (TOUT flip-flop ) status. The timer out flip-flop is inverted by the match signal sent from the comparator. When bit 3 of the timer/ event counter mode register (TM0, TM1) is set to 1, the timer out flip-flop is cleared to 0.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-33.
µPD750008 USER'S MANUAL Figure 5-33. Timer/Event Counter Mode Register Setup (2/2) (b) In the case of timer counter (channel 1) Address 7 FA8H 6 5 4 3 2 1 TM16 TM15 TM14 TM13 TM12 0 Symbol TM1 Count pulse (CP) selection bit TM16 TM15 TM14 Count pulse (CP) 1 0 0 fX/212 1 0 1 fX/210 1 1 0 fX/28 1 1 1 fX/26 Other than above Not to be set Timer start indication bit TM13 When “1” is written to the bit, the counter and IRQT1 flag are cleared.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (2) Timer/event counter time setting [Timer setup time] (cycle) is found by dividing [modulo register contents + 1] by [count pulse (CP) frequency] selected by setting the mode register. T (sec) = n+1 = (n + 1) · (resolution) fCP T (sec) : Timer setup time (seconds) fCP (Hz) : Count pulse frequency (Hz) n : Modulo register content (n • 0) Once the timer is set, interrupt request signal (IRQTn) is generated at the intervals set in the timer.
µPD750008 USER'S MANUAL (3) Timer/event counter operation The timer/event counter operates as follows. Figure 5-35 shows the configuration of the timer/event counter. <1> The count pulse (CP) is selected by setting the mode register (TMn) and is input to the count register (Tn). <2> The Tn is compared with the modulo register (TMODn), and if they are equal, a match signal is generated and the interrupt request flag (IRQTn) is set. At the same time, the timer out flip-flop (TOUT flip-flop) is inverted.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-36. Count Operation Timing Count pulse(CP) n Modulo register (TMODn) Count register (Tn) 0 1 2 n–1 n 0 1 2 n–1 n Match 0 1 2 3 4 Match Reset TOUT F/F Timer start indication (4) Applications of the timer/event counter (a) Timer/event counter is used as an interval timer that generates interrupts at intervals of 30 ms. • The high-order four bits of the mode register are set to 0100B to select maximum set time 43.7 ms (at fX = 6.00 MHz).
µPD750008 USER'S MANUAL SEL MB15 5.5.3 MOV MOV XA,#100 – 1 TMOD0,XA ; Set the modulo register MOV MOV XA,#00001100B TM0,XA ; Set the mode register EI EI IET0 ; Enable INTT0 Notes on Timer/Event Counter Applications (1) Time error at the start of the timer A maximum error of one count pulse (CP) cycle from a value calculated according to Section 5.5.2 (2) occurs in a time period from the start of the timer (bit 3 of the TM0 is set) to the generation of a match signal.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (3) Error in reading the count register The contents of the count register can be read using an 8-bit data memory manipulation instruction at any time. During operation by such an instruction, all count pulse changes are held not to change the count register. This means that if the count pulse signal source is applied to the TI0 input, as many count pulses as corresponding to the time required to execute the instruction are cut.
µPD750008 USER'S MANUAL Re-set instruction Re-set instruction Clock A specified Clock B specified Clock A specified Clock A Clock B <1> <2> CP (5) Operation after the modulo register is changed The contents of the modulo register are changed when an 8-bit data memory manipulation instruction is executed.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.6 SERIAL INTERFACE 5.6.1 Serial Interface Functions The µPD750008 contains a clock synchronous 8-bit serial interface, which has four modes. The functions of the four modes are outlined below. (1) Operation halt mode This mode is used when serial transfer is not performed. This mode reduces power consumption. (2) Three-wire serial I/O mode In this mode, 8-bit data is transferred through three lines: Serial clock (SCK), serial output (SO), and serial input (SI).
µPD750008 USER'S MANUAL Figure 5-38. Example of the SBI System Configuration VDD Master CPU Serial clock Slave CPU SCK SCK #1 Address 1 #N Address N SB0, SB1 SB0, SB1 Address Command Data Slave IC SCK SB0, SB1 5.6.2 Configuration of Serial Interface Figure 5-39 shows the block diagram of the serial interface.
P01/SCK P02/SO0/SB0 P03/SI0/SB1 P01 output latch Selector Selector CSIM Bit test 8 8 Serial clock control circuit Serial clock counter Bus release/ command/ acknowledge detection circuit Shift register (SIO) Address comparator CMDT D INTCSI control circuit Q SET CLR SO latch RELD CMDD ACKD (8) (8) Match signal RELT Bit manipulation Slave address register (SVA) (8) 8 SBIC Serial clock selector Busy/ acknowledge output circuit ACKT 8/4 ACKE Internal bus BSYE Figure 5-39.
µPD750008 USER'S MANUAL (1) Serial operation mode register 0 (CSIM) CSIM is an 8-bit register which specifies a serial interface operation mode, serial clock, wake-up function, and so forth. (See (1) in Section 5.6.3 for details.) (2) Serial bus interface control register (SBIC) SBIC is an 8-bit register consisting of bits for controlling the serial bus and flags for indicating the states of input data from the serial bus. SBIC is used mainly in the SBI mode. (See (2) in Section 5.6.3 for details.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (9) Serial clock control circuit The serial clock control circuit controls the serial clock to be supplied to the shift register, or controls the clock to be output to the SCK pin when the internal system clock is used. (10) Busy/acknowledge output circuit and bus release/command/acknowledge detection circuit The busy/acknowledge output circuit and bus release/command/acknowledge detection circuit output and detect control signals generated in the SBI mode.
µPD750008 USER'S MANUAL Figure 5-40. Format of Serial Operation Mode Register (CSIM) (2/4) Serial interface operation enable/disable specification bit (W) Shift register operation CSIE Serial clock counter IRQCSI flag SO/SB0 and SI/SB1 pins 0 Shift operation disabled Cleared Held Used only for port 0 1 Shift operation enabled Count operation Can be set.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-40.
µPD750008 USER'S MANUAL Figure 5-40. Format of Serial Operation Mode Register (CSIM) (4/4) Remarks 2. The P01/SCK pin assumes any of the following states according to the state of CSIE, CSIM1, and CSIM0: CSIE CSIM1 CSIM0 P01/SCK pin state 0 0 0 Input port 1 0 0 High impedance 0 0 1 High level output 0 1 0 0 1 1 1 0 1 1 1 0 1 1 1 Serial clock output (High level output) 3.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (2) Serial bus interface control register (SBIC) Figure 5-41 shows the format of the serial bus interface control register (SBIC). SBIC is an 8-bit register consisting of bits for controlling the serial bus and flags for indicating the states of input data from the serial bus. SBIC is used mainly in the SBI mode. SBIC is manipulated using a bit manipulation instruction. SBIC cannot be manipulated using a 4-bit or 8-bit memory manipulation instruction.
µPD750008 USER'S MANUAL Figure 5-41. Format of Serial Bus Interface Control Register (SBIC) (2/3) Busy enable bit (R/W) BSYE 0 <1> The busy signal is automatically disabled. <2> Busy signal output is stopped in phase with the falling edge of SCK immediately after clear instruction execution. 1 The busy signal is output after the acknowledge signal in phase with the falling edge of SCK. Acknowledge detection flag (R) ACKD Condition for being cleared (ACKD = 0) <1> The transfer operation is started.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-41. Format of Serial Bus Interface Control Register (SBIC) (3/3) Bus release detection flag (R) RELD Condition for being cleared (RELD = 0) <1> <2> <3> <4> The transfer start instruction is executed. The RESET signal is generated. CSIE = 0 (Figure 5-40) SVA does not match SIO when an address is received. Condition for being set (RELD = 1) The bus release signal (REL) is detected.
µPD750008 USER'S MANUAL (3) Shift register (SIO) Figure 5-42 shows the configuration of peripheral hardware of shift register. SIO is an 8-bit register which performs parallel-serial conversion and serial transfer (shift) operation in phase with the serial clock. Serial transfer is started by writing data to SIO. In transmission, data written to SIO is output on the serial output (SO) or serial data bus (SB0 or SB1). In receive operation, data is read from the serial input (SI) or SB0 or SB1 into SIO.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (a) Slave address detection [In the SBI mode] SVA is used when the µPD750008 is connected as a slave device to the serial bus. SVA is an 8bit register for a slave to set its slave address (number assigned to it). The master outputs a slave address to the connected slaves to select a particular slave. Two data values (a slave address output from the master and the value of SVA) are compared with each other by the address comparator.
µPD750008 USER'S MANUAL Address FE0H 7 6 5 4 CSIE COI WUP 3 2 1 0 CSIM4 CSIM3 CSIM2 CSIM1 CSIM0 CSIM Serial clock selection bit (W)Note Serial interface operation mode selection bit (W) Wake-up function specification bit (W) Match signal from address comparator (R) Serial interface operation enable/disable specification bit (W) Note The status of the P01/SCK pin is selectable.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.6.5 Three-Wire Serial I/O Mode Operations The three-wire serial I/O mode is compatible with other modes used in the 75 XL series, 75X series, µPD7500 series, and 87AD series. Communication is performed using three lines: Serial clock (SCK), serial output (SO), and serial input (SI). Figure 5-43.
µPD750008 USER'S MANUAL Serial interface operation enable/disable specification bit (W) Shift register operation CSIE 1 Shift operation enabled Serial clock counter IRQCSI flag Count operation Can be set SO/SB0 and SI/SB1 pins Used in each mode as well as for port 0 Signal from address comparator (R) COI Note Condition for being cleared (COI = 0) When the slave address register (SVA) does not match the data of the shift register Condition for being set (COI = 1) When the slave address register (S
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (b) Serial bus interface control register (SBIC) To use the three-wire serial I/O mode, set SBIC as shown below. (For details on SBIC format, see (2) in Section 5.6.3.) SBIC is manipulated using a bit memory manipulation instruction. When the RESET signal is input, SBIC is set to 00H. In the figure below, hatched portions indicate the bits used in the three-wire serial I/O mode.
µPD750008 USER'S MANUAL Figure 5-44. Timing of Three-Wire Serial I/O Mode 1 SCK 2 3 4 5 6 7 8 SI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 IRQCSI Completion of transfer Transfer operation is started in phase with falling edge of SCK. Execution of instruction that writes data to SIO (Transfer start request) The SO pin becomes a CMOS output and outputs the state of the SO latch.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (4) Signals Figure 5-45 shows operations of RELT and CMDT. Figure 5-45. Operations of RELT and CMDT SO latch RELT CMDT (5) Switching between MSB and LSB as the first transfer bit The three-wire serial I/O mode has a function that can switch between the MSB and LSB as the first bit of transfer. Figure 5-46 shows the configuration of shift register (SIO) and internal bus.
µPD750008 USER'S MANUAL (6) Transfer start Serial transfer is started by writing transfer data into shift register (SIO), provided that the following two conditions are satisfied: • The serial interface operation enable/disable specification bit (CSIE) is set to 1. • The internal serial clock is not operating after 8-bit serial transfer, or SCK is high. Caution Setting CSIE after writing data to the shift register does not start transfer.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (b) Data is transmitted and received starting with the LSB on an external clock (slave operation). (In this case, the function of inverting the MSB/LSB is used for shift register read/write operation.
µPD750008 USER'S MANUAL (master side): CLR1 MBE MOV MOV XA,#10000011B CSIM,XA ; Set transfer mode MOV MOV XA,TDATA SIO,XA ; Set transfer data, and start transfer . . . . . . . . . . LOOP : SKTCLR BR MOV IRQCSI LOOP ; Test IRQCSI XA,SIO ; Read in receive data 5.6.6 Two-Wire Serial I/O Mode The two-wire serial I/O mode can be made compatible with any communication format by programming.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (a) Serial operation mode register (CSIM) To use the two-wire serial I/O mode, set CSIM as shown below. (For details on CSIM format, see (1) in Section 5.6.3.) CSIM is manipulated using an 8-bit manipulation instruction. Bits 7, 6, and 5 of CSIM can be manipulated bit by bit. When the RESET signal is input, CSIM is set to 00H. In the figure below, hatched portions indicate the bits used in the two-wire serial I/O mode.
µPD750008 USER'S MANUAL Serial interface operation mode selection bit (W) CSIM4 CSIM3 CSIM2 0 1 1 Shift register sequence SIO7-0 <—> XA (Transfer starting with MSB) 1 SO pin function SI pin function SB0/P02 (N-ch open-drain I/O) P03 input P02 input SB1/P03 (N-ch open-drain I/O) Serial clock selection bit (W) CSIM1 CSIM0 Serial clock SCK pin mode 0 0 External clock applied to SCK pin Input 0 1 Timer/event counter output (TOUT0) Output 1 0 fX/2 6 (65.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Bus release trigger bit (W) RELT Control bit for bus release signal (REL) trigger output. By setting RELT = 1, the SO latch is set to 1. Then the RELT bit automatically cleared to 0. Caution Never use bits other than RELT and CMDT in the two-wire serial I/O mode. (2) Communication operation The two-wire serial I/O mode transfers data, with eight bits as one block. Data is transferred bit by bit in phase with the serial clock.
µPD750008 USER'S MANUAL (3) Serial clock selection To select the serial clock, manipulate bits 0 and 1 of serial operation mode register (CSIM). The serial clock can be selected out of the following four clocks: Table 5-8.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (6) Error detection In the two-wire serial I/O mode, the state of serial bus SB0 or SB1 being used for communication is loaded into the shift register (SIO) of the transmitting device. So a transmission error can be detected by the methods described below. (a) Comparing SIO data before start of transmission with SIO data after start of transmission With this method, the occurrence of a transmission error is assumed when two SIO values disagree with each other.
µPD750008 USER'S MANUAL The µPD750008, which is the master microcomputer, outputs a serial clock, and all slave microcomputers operate with an external clock. 5.6.7 SBI Mode Operation The SBI (serial bus interface) is a high-speed serial interface that conforms to the NEC serial bus format. To allow communication with multiple devices on a single-master and high-speed serial bus using two signal lines, the SBI has a bus configuration function added to the clock synchronous serial I/O method.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Cautions 1. In the SBI mode, the serial data bus pin SB0 (or SB1) is an open-drain output. So the serial data bus line is placed in the wired OR state. A pull-up resistor is required for the serial data bus line. 2. To switch between the master and slave, a pull-up resistor is required also for the serial clock line (SCK) because SCK input/output switching is performed between the master and slave asynchronously.
µPD750008 USER'S MANUAL (2) SBI definition The format of serial data and signal used in the SBI mode are described below. Serial data to be transferred in the SBI mode is classified into three types: Address, command, and data. Serial data forms one frame as shown below. Figure 5-51 is a timing chart for transferring address, command, and data. Figure 5-51.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (a) Bus release signal (REL) When the SCK line is high (the serial clock is not output), the SB0 (or SB1) line changes from low to high. This signal is called the bus release signal, and is output by the master. Figure 5-52. Bus Release Signal "H" SCK SB0, SB1 This signal indicates that the master is to send an address to a slave. Slaves contain hardware to detect the bus release signal.
µPD750008 USER'S MANUAL Figure 5-55. Slave Selection Using an Address Master Slave 1 Not selected Slave 2 Selected Slave 3 Not selected Slave 4 Not selected Transmits address for slave 2 (d) Command and data The master sends commands to the slave selected by sending an address. The master also transfers data to or from the slave. Figure 5-56. Command 1 SCK 2 C7 SB0, SB1 3 C6 4 C5 5 C4 6 C3 7 8 C2 C1 C0 6 7 8 Command Command signal Figure 5-57.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-58. Acknowledge Signal [When output in phase with the 11th clock of SCK] SCK 8 9 SB0, SB1 10 11 ACK [When output in phase with the 9th clock of SCK] SCK SB0, SB1 8 9 ACK The acknowledge signal is a one-shot pulse output in phase with the falling edge of SCK after 8-bit data transfer. This signal may be synchronized with any clock of SCK. The transmitter checks if the receiver returns the acknowledge signal after 8-bit data transfer.
µPD750008 USER'S MANUAL (f) Busy signal (BUSY) and ready signal (READY) The busy signal informs the master that a slave is getting ready for data transfer. The ready signal informs the master that a slave is ready for data transfer. Figure 5-59. Busy and Ready Signals 8 SCK 9 ACK SB0, SB1 BUSY READY In the SBI mode, a slave notifies the master of the busy state by changing SB0 (or SB1) from high to low. The busy signal is output following the acknowledge signal output by the master or a slave.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Serial interface operation enable/disable specification bit (W) Shift register operation CSIE 1 Shift operation enabled Serial clock counter IRQCSI flag Count operation Can be set SO/SB0 and SI/SB1 pins Used in each mode as well as for port 0 Signal from address comparator (R) COINote Condition for being cleared (COI = 0) When the slave address register (SVA) does not match the data of the shift register Condition for being set (COI = 1) When the slave addr
µPD750008 USER'S MANUAL Serial clock selection bit (W) CSIM1 CSIM0 Serial clock SCK pin mode 0 0 External clock applied to SCK pin Input 0 1 Timer/event counter output (TOUT0) Output 1 0 fX/2 4 (262 kHz) 1 1 fX/2 3 (524 kHz) Remark The value at 4.19 MHz is indicated in parentheses. (b) Serial bus interface control register (SBIC) To use the SBI mode, set SBIC as shown below. (For details on SBIC format, see(2) in Section 5.6.3.) SBIC is manipulated using a bit manipulation instruction.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Acknowledge detection flag (R) ACKD Condition for being cleared (ACKD = 0) <1> The transfer operation is started. <2> The RESET signal is entered. Condition for being set (ACKD = 1) The acknowledge signal (ACK) is detected (in phase with the rising edge of SCK). Acknowledge enable bit (R/W) ACKE 0 Disables automatic output of the acknowledge signal. (Output by ACKT is possible.) 1 When set before transfer ACK is output in phase with the 9th clock of SCK.
µPD750008 USER'S MANUAL Bus release trigger bit (W) RELT Control bit for bus release signal (REL) trigger output. By setting RELT = 1, the SO latch is set to 1. Then the RELT bit automatically cleared to 0. Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) before or after serial transfer. (4) Serial clock selection To select the serial clock, manipulate bits 0 and 1 of serial operation mode register (CSIM).
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-60. Operations of RELT, CMDT, RELD, and CMDD (Master) Transfer start request SIO SCK "H" SO latch RELT CMDT RELD CMDD Figure 5-61. Operations of RELT, CMDT, RELD, and CMDD (Slave) Transfer start request Write to SIO.
µPD750008 USER'S MANUAL Figure 5-62. Operation of ACKT When ACKT is set after transfer completion SCK 6 SB0, SB1 7 D2 8 D1 9 D0 ACK signal is output during the first clock cycle immediately after ACKT is set. ACK ACKT When set during this period Caution Do not set the ACKT until the transfer is completed. Figure 5-63.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-63. Operation of ACKE (2/2) (d) When ACKE = 1 period is too short SCK The ACK signal is not output. SB0, SB1 ACKE When ACKE is set or cleared during this period and ACKE = 0 at the falling edge of SCK Figure 5-64.
µPD750008 USER'S MANUAL Figure 5-64. Operation of ACKD (2/2) (c) Clear timing for case where start of transfer is directed during BUSY Transfer start request SIO Transfer start SCK 6 SB0, SB1 7 D2 8 D1 9 D0 ACK BUSY D7 D6 ACKD Figure 5-65.
Master Command signal Ready signal (READY) Slave Slave Busy signal (BUSY) Master/ slave Acknowledge signal (ACK) (CMD) Master Output device Bus release signal (REL) Signal name High level signal output on SB0 or SB1 before serial transfer is started or after serial transfer is completed [Synchronous BUSY signal] Low level signal output on SB0 or SB1 after acknowledge signal Low level signal output on SB0 or SB1 during one SCK clock cycle after serial reception is completed Falling edge of S
166 Master Master/ slave Command (C7 - C0) Data (D7 - D0) CMD signal being output 8-bit data transferred in phase with SCK, with neither REL signal nor not being output output, with REL signal phase with SCK after only CMD signal is 8-bit data transferred in signal output 8-bit data transferred in phase with SCK after REL signal and CMD BUSY signal, and so on. Address/command/data is output during first 8 clock cycles.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (6) Pin configuration The configurations of serial clock pin SCK and serial data bus pin (SB0 or SB1) are as follows: (a) SCK: Pin for serial clock I/O <1> Master : CMOS, push-pull output <2> Slave : Schmitt input (b) SB0, SB1: Pin for serial data I/O Output to SB0 or SB1 is an N-ch open-drain output and input is Schmitt input for both the master and a slave. The serial data bus line must be externally pulled up because it has originally an N-ch open-drain output.
µPD750008 USER'S MANUAL (7) Address match detection method In the SBI mode, communication starts when the master selects a particular slave device by outputting an address. An address match is detected by hardware. The slave address register (SVA) is available. In the wakeup state (WUP = 1), IRQCSI is set only when the address transmitted by the master and the value held in SVA match. Cautions 1.
SB0 or SB1 pin SCK pin Hardware operation Program processing Slave device processing (receiver) Transfer line Hardware operation Program processing Master device processing (transmitter) Write to SIO Set RELD Set Clear Set CMDD CMDD CMDD Set Set Set CMDT RELT CMDT 1 A7 A6 2 3 A5 A3 5 A2 6 Serial reception Address A4 4 Serial transmission A1 7 8 A0 Generate IRQCSI WUP<-0 (When SVA = SIO) 9 Generate IRQCSI Clear BUSY Clear BUSY Output Output ACK BUSY BUSY Set ACKT ACK
170 SB0 or SB1 pin SCK pin Hardware operation Program processing Slave device processing (receiver) Transfer line Hardware operation Program processing Master device processing (transmitter) Write to SIO Set CMDD Set CMDT 1 C7 2 C6 3 C5 C4 5 C3 6 Serial reception Command 4 C2 Serial transmission 7 C1 8 C0 9 Generate IRQCSI Read SIO Generate IRQCSI Analyze command Clear BUSY Clear BUSY Output Output BUSY ACK BUSY Set ACKT ACK Set ACKD READY Stop SCK Interrupt handl
SB0 or SB1 pin SCK pin Hardware operation Program processing Slave device processing (receiver) Transfer line Hardware operation Program processing Master device processing (transmitter) Write to SIO 1 D7 D6 2 3 D5 D3 5 D2 6 Serial reception Data D4 4 Serial transmission D1 7 8 D0 9 Generate IRQCSI Read SIO Generate IRQCSI Clear BUSY Clear BUSY Output Output ACK BUSY BUSY Set ACKT ACK Set ACKD READY Stop SCK Interrupt handling (preparation for next serial transfer) Fi
172 SB0 or SB1 pin SCK pin BUSY Data D4 5 D3 6 D2 7 D1 8 D0 9 Generate IRQCSI ACK BUSY READY Set Output Clear ACKD BUSY BUSY Serial transmission 4 Clear BUSY D5 3 Output ACK 1 D7 D6 2 Serial reception Receive data processing Hardware operation D6 2 Generate IRQCSI Write Set FFH to ACKT SIO Write to SIO D7 1 Serial reception Read SIO Write to SIO READY Stop SCK Write FFH to SIO Program processing Slave device processing (transmitter) Transfer line Hardware oper
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (10) Transfer start Serial transfer is started by writing transfer data in shift register (SIO), provided that the following two conditions are satisfied: • The serial interface operation enable/disable bit (CSIE) is set to 1. • The internal serial clock is not operating after 8-bit serial transfer, or SCK is high. Cautions 1. Transfer cannot be started by setting CSIE to 1 after writing data to the shift register. 2.
µPD750008 USER'S MANUAL (12) SBI mode This section describes an example of application which performs serial data communication in the SBI mode. In the example, the µPD750008 can be used as either the master CPU or a slave CPU on the serial bus. The master can be switched to another CPU with a command. (a) Serial bus configuration In the serial bus configuration used for the example of this section, a µPD750008 is connected to the bus line as a device on the serial bus.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (b) Explanation of commands (i) Types of commands This example uses the following commands: <1> READ command <2> WRITE command : Transfers data from slave to master. : Transfers data from master to slave. <3> END command <4> STOP command : Informs slave of WRITE command completion. : Informs slave of WRITE command interruption. <5> STATUS command : Reads slave status. <6> RESET command : Sets currently selected slave as non-selected slave.
µPD750008 USER'S MANUAL When the slave receives a transmission data count, if it has data enough for transmitting the specified number of bytes of data, the slave returns ACK. If the slave does not have enough data for transmission, an error occurs; ACK is not returned in this case. The master sends ACK to the slave each time it receives one byte. <2> WRITE command, END command, STOP command These commands write data to a slave. One to 256 bytes of data can be written.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS <3> STATUS command The STATUS command reads the status of the current slave. Figure 5-75. Transfer Format of the STATUS Command M S S S STATUS ACK Status ACK Data Command Remark M: Output by the master S: Output by the slave The slave returns the status in the format shown in Figure 5-78. Figure 5-76.
µPD750008 USER'S MANUAL <4> RESET command The RESET command changes the currently selected slave to a non-selected slave. When a RESET command is transmitted, any slave can be placed in the non-selected state. Figure 5-77. Transfer Format of the RESET Command M S RESET ACK Command Remark M: Output by the master S: Output by the slave <5> CHGMST command The CHGMST command passes the master authority to the currently selected slave. Figure 5-78.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS If ACK is not returned from the slave within a predetermined period after transmission completion, the occurrence of an error is assumed; the master outputs the ACK signal as a dummy. Figure 5-79. Master and Slave Operation in Case of Error Reception is completed. Error is assumed, and processing is halted. Processing by slave SB0, SB1 Erroneous data ACK ACK wait time Processing by master ACK from slave is checked. Transfer is completed. ACK check is started.
µPD750008 USER'S MANUAL Example To output one SCK/P01 pin clock cycle by software SEL MB15 ; or CLR1 MBE MOV MOV XA,#10000011B CSIM,XA CLR1 0FF0H.1 SET1 0FF0H.1 ; SCK (fX/23), output mode ; SCK/P01 <- 0 ; SCK/P01 <- 1 Figure 5-80. SCK/P01 Pin Circuit Configuration P01/SCK To internal circuit Address FF0H.1 P01 output latch SCK From the serial clock control circuit SCK pin output mode The P01 output latch is mapped to bit 1 of address FF0H. A RESET signal sets the P01 output latch to 1.
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.7 BIT SEQUENTIAL BUFFER: 16-BIT The bit sequential buffer (BSB) is special data memory for bit manipulations. In particular, the buffer allows bit manipulations to be performed very easily by sequentially changing address and bit specifications. So the buffer is useful in processing long data bit by bit. This data memory consists of 16 bits, and allows pmem.@L addressing with a bit manipulation instruction.
µPD750008 USER'S MANUAL Example To output 16-bit data of BUFF1 and BUFF2 serially from bit 0 of port 3: LOOP0: LOOP1: CLR1 MOV MBE XA,BUFF1 MOV MOV BSB0,XA ; Set BSB0 and BSB1 XA,BUFF2 MOV MOV BSB2,XA L,#0 SKT BR BSB0, @L ; Tests the specification bit of BSB LOOP1 NOP SET1 PORT3. 0 BR CLR1 LOOP2 PORT3.
CHAPTER 6 INTERRUPT AND TEST FUNCTIONS CHAPTER 6 INTERRUPT AND TEST FUNCTIONS The µPD750008 has seven vectored interrupt sources and two test inputs, allowing a wide range of applications. In addition, the interrupt control circuitry of the µPD750008 has the following features for very high-speed interrupt processing.
184 Note IRQW INTW Falling edge detection circuit IM2 IRQ2 IRQT1 INTT1 Selector IRQT0 INTT0 Rising edge detection circuit IRQCSI IRQ1 IRQ0 IRQ4 IRQBT INTCSI Both-edge detection circuit Edge detection circuit Edge detection circuit INTBT IM0 4 Interrupt enable flag (IExxx) Note Noise eliminator (when the noise eliminator is selected, standby mode cannot be released.
CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 6.2 TYPES OF INTERRUPT SOURCES AND VECTOR TABLES Table 6-1 lists the types of interrupt sources, and Figure 6-2 shows vector tables. Table 6-1.
µPD750008 USER'S MANUAL The column of interrupt priority in Table 6-1 indicates a priority assigned when multiple interrupt requests occur concurrently or are held. A vector table contains interrupt processing start addresses and MBE and RBE setting values during interrupt processing. An assembler pseudo instruction (VENTn) is used to set a vector table. Example A vector table is set for INTBT/INT4.
CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 6.3 VARIOUS DEVICES TO CONTROL INTERRUPT FUNCTIONS (1) Interrupt request flags and interrupt enable flags The following seven interrupt request flags (IRQxxx) corresponding to the interrupt sources are provided.
µPD750008 USER'S MANUAL Table 6-2. Set Signals for Interrupt Request Flags Interrupt request flag Set signals for interrupt request flags Interrupt enable flag IRQBT Set by a reference time interval signal from the basic interval timer/watchdog timer. IEBT IRQ4 Set by a detected rising or falling edge of an INT4/P00 pin input signal. IE4 IRQ0 Set by a detected edge of an INT0/P10 pin input signal. The detection edge is specified by the INT0 edge detection mode register (IM0).
CHAPTER 6 INTERRUPT AND TEST FUNCTIONS Figure 6-3. Interrupt Priority Specification Register Address FB2H Symbol 3 2 1 0 IPS3 IPS2 IPS1 IPS0 IPS High-order interrupt selection 0 0 0 All low-order interrupt 0 0 1 VRQ1 (INTBT/INT4) 0 1 0 VRQ2 (INT0) 0 1 1 VRQ3 (INT1) 1 0 0 VRQ4 (INTCSI) 1 0 1 VRQ5 (INTT0) 1 1 0 VRQ6 (INTT1) 1 1 1 Not to be set The listed vectored interrupts are treated as high-order interrupts.
µPD750008 USER'S MANUAL (3) Configurations of the INT0, INT1, and INT4 circuits (a) As shown in Figure 6-4 (a), the INT0 circuit accepts an external interrupt at its rising or falling edge. The edge to be detected can be selected. The INT0 circuit has a noise elimination function (see Figure 6-5), called a noise eliminator, using a sampling clock, which removes pulses shorter than two sampling clock cyclesNote as noise.
CHAPTER 6 INTERRUPT AND TEST FUNCTIONS Figure 6-4.
µPD750008 USER'S MANUAL Figure 6-5.
CHAPTER 6 INTERRUPT AND TEST FUNCTIONS Figure 6-6. Format of Edge Detection Mode Registers (a) INT0 edge detection mode register (IM0) Address FB4H Symbol 3 2 1 0 IM03 IM02 IM01 IM00 IM0 IM01 IM00 0 0 Specifies rising edge. 0 1 Specifies falling edge. 1 0 Specifies both rising and falling edges. 1 1 Ignored (No interrupt request flag is set.) IM02 Detection edge specification Noise eliminator selection bit Sampling 0 Selects a noise eliminator.
µPD750008 USER'S MANUAL (4) Interrupt status flags The interrupt status flags (IST0 and IST1), which are contained in the PSW, indicate the status of processing currently executed by the CPU. By using the content of these flags, the interrupt priority control circuit controls multiple interrupts as indicated in Table 6-3.
CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 6.4 INTERRUPT SEQUENCE When an interrupt occurs, it is processed using the procedure shown in Figure 6-7. Figure 6-7. Interrupt Sequence Interrupt (INTxxx) occurrence IRQxxx setting No IExxx set? Hold until IExxx is set. Yes Corresponding VRQn occurrence IME = 1 No Hold until IME is set. Yes Is VRQn high-order interrupt? Hold until processing being executed is finished.
µPD750008 USER'S MANUAL 6.5 MULTIPLE INTERRUPT PROCESSING CONTROL The µPD750008 can handle multiple interrupts by either of the following methods. (1) Multiple interrupt processing by a high-order interrupt In this method, the µPD750008 selects an interrupt source among multiple interrupt sources, enabling double interrupt processing. That is, the high-order interrupt specified by the interrupt priority specification register (IPS) is enabled when the processing status is 0 or 1.
CHAPTER 6 INTERRUPT AND TEST FUNCTIONS (2) Multiple interrupt processing by changing the interrupt status flags Changing the interrupt status flags with the program causes multiple interrupts to be enabled. That is, when the interrupt processing program changes both IST1 and IST0 to 0 (status 0), multiple interrupt processing is enabled. This method is used when two or more interrupts are to be enabled at a time or when the processing of three or more interrupts is to be performed.
µPD750008 USER'S MANUAL 6.6 PROCESSING OF INTERRUPTS SHARING A VECTOR ADDRESS Interrupt sources INTBT and INT4 share a vector table, so an interrupt source is selected as described below. (1) Using only one interrupt The interrupt enable flag for desired one of the two interrupt sources sharing a vector table is set to 1, and the interrupt enable flag for the other is cleared to 0. In this case, the enabled (IExxx = 1) interrupt source causes an interrupt request.
CHAPTER 6 INTERRUPT AND TEST FUNCTIONS Examples 1. To use both INTBT and INT4 as having the higher priority and give priority to INT4 * DI SKTCLR IRQ4 BR . VSUBBT . . . ; IRQ4 = 1 ? Processing routine EI of INT4 RETI. . . VSUBBT: CLR1 EI .. . . . . .. . . IRQBT Processing routine of INTBT RETI 2. To use both INTBT and INT4 as having the lower priority and give priority to INT4 SKTCLR IRQ4 BR . VSUBBT . . . .. . . . . ; * IRQ4 = 1 ? Processing routine of INT4 RETI VSUBBT: CLR1.
µPD750008 USER'S MANUAL 6.7 MACHINE CYCLES FOR STARTING INTERRUPT PROCESSING With the µPD750008 series, the following machine cycles are used to start the execution of the interrupt service routine after an interrupt request flag (IRQn) is set.
CHAPTER 6 INTERRUPT AND TEST FUNCTIONS (2) When IRQn is set during an instruction other than that described in (1) (a) When IRQn is set at the last machine cycle of the instruction being executed In this case, an instruction preceded by the instruction being executed is executed, and an interrupt processing of three machine cycles is executed, then the interrupt service routine is started. An instruction other than interrupt control instruction A B C D A: IRQn is set.
µPD750008 USER'S MANUAL 6.8 EFFECTIVE USE OF INTERRUPTS The interrupt function can be used more effectively in the ways described below. (1) MBE = 0 is set for the interrupt service routine By allocating addresses 00H to 7FH as data memory used by the interrupt service routine and specifying MBE = 0 in an interrupt vector table, the user can code a program without being concerned with a memory bank.
CHAPTER 6 INTERRUPT AND TEST FUNCTIONS (1) Interrupt enable/disable <1> Reset •• •• •• •• • <2> EI IE0 EI IET0 Interrupt disabled <3> EI •• •• •• •• • INT0 and INTT0 enabled <4> DI IE0 •• •• •• •• • INTT0 enabled <5> DI •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• Interrupt disabled <1> A RESET signal disables all interrupts. <2> Interrupt enable flags are set by the EI IExxx instruction. At this stage, all interrupts are disabled.
µPD750008 USER'S MANUAL (2) Example of using INTBT, INT0 (falling edge active), and INTT0 without multiple interrupt processing <1> Reset <2> MOV MOV CLR1 <3> EI EI EI EI •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• • ; RBE = 1, MBE = 0 A, #1 IM0, A IRQ0 IEBT IE0 IET0 Status 0 ; RBE = 0 <4> INT0 Status 1 Status 0 <5> RETI <1> A RESET signal disables all interrupts, setting status 0.
CHAPTER 6 INTERRUPT AND TEST FUNCTIONS (3) Nesting of interrupts with higher priority (INTBT has higher priority and INTT0 and INTCSI have lower priority) Reset SEL EI EI EI <1> MOV MOV RB2 IEBT IET0 IECSI A, #9 IPS, A ; RBE = 1, MBE = 0 Status 0 ; RBE = 0 Status 1 <2> INTT0 ; RBE = 1 <4> SEL RB1 Status 2 <3> INTBT <5> SEL RB2 RETI Status 1 Status 0 RETI <1> INTBT is specified as having the higher priority by setting of IPS, and the interrupt is enab
µPD750008 USER'S MANUAL (4) Execution of held interrupts (interrupt requests when interrupts are disabled) Reset EI IE0 •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• • <1> INT0 <3> INTCSI <2> EI •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• • <4> EI RETI IECSI •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• • RETI <1> If INT0 is set when interrupts are d
CHAPTER 6 INTERRUPT AND TEST FUNCTIONS (5) Execution of held interrupts – two interrupts with lower priority occur concurrently – Reset EI IET0 EI IE0 EI •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• <1> INT0 INTT0 <2> RETI RETI <1> When INT0 and INTT0 with the lower priority occur co
µPD750008 USER'S MANUAL * (6) Executing pending interrupt – interrupt occurs during interrupt processing (INTBT has higher priority and INTT0 and INTCSI have lower priority) – Reset EI EI EI MOV MOV IEBT IET0 IECSI A, #9 IPS, A PUSH rp <2> INTCSI INTT0 POP rp <3> RETI <1> INTBT <4> RETI RETI <1> When INTBT with the higher priority and INTT0 with the lower priority occur at the same time, the processing of th
CHAPTER 6 INTERRUPT AND TEST FUNCTIONS (7) Enabling of level-two interrupts (enabling level-two INTT0 and INT0 interrupts with INTCSI and INT4 handled as level-one interrupts) Reset EI IET0 EI EI EI EI IE0 IECSI IE4 •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• •• Status 0 <2> DI <1> INTCSI Status 1 CL
µPD750008 USER'S MANUAL 6.10 TEST FUNCTION 6.10.1 Test Sources The µPD750008 has two test sources. INT2 provides two types of edge-detection-test inputs. Table 6-5. Test Source Test source INT2 INTW 6.10.
CHAPTER 6 INTERRUPT AND TEST FUNCTIONS (2) INT2 and key interrupt (KR0 to KR7) hardware Figure 6-10 shows the configuration of INT2 and KR0 to KR7. The IRQ2 set signal is output in either of the following edge detection modes, which is selected with the INT2 edge detection mode register (IM2). (a) Detection of a rising edge on the INT2 input pin IRQ2 is set when a rising edge is detected on the INT2 input pin.
212 KR0/P60 KR1/P61 KR2/P62 KR3/P63 KR4/P70 KR5/P71 KR6/P72 KR7/P73 INT2/P12 Input buffer Internal bus 4 IM2 Falling edge detection circuit Rising edge detection circuit Figure 6-10.
CHAPTER 6 INTERRUPT AND TEST FUNCTIONS Figure 6-11. Format of INT2 Edge Detection Mode Register (IM2) Address FB6H Symbol 3 2 1 0 0 0 IM21 IM20 IM2 IM21 IM20 0 0 0 1 1 0 1 1 INT2 interrupt source Specifies rising edge of INT2 pin input. Interrupt input pin INT2 (1) KR4 - KR7 (4) Specifies falling edge of any of KRx pin inputs. KR2 - KR7 (6) KR0 - KR7 (8) Cautions 1. When the edge detection mode register is modified, test request flags may be set in some cases.
µPD750008 USER'S MANUAL [MEMO] 214
CHAPTER 7 STANDBY FUNCTION CHAPTER 7 STANDBY FUNCTION The µPD750008 provides a standby function to reduce the power consumption by the system. The standby function is available in the two modes: the STOP mode and HALT mode. Differences between these two modes are as follows: (1) STOP mode In the STOP mode, the main system clock oscillator is stopped, and the entire system stops. The current used by the CPU is reduced to quite a low level.
µPD750008 USER'S MANUAL 7.1 SETTING OF STANDBY MODES AND OPERATION STATUS Table 7-1.
CHAPTER 7 STANDBY FUNCTION Caution 2. Reset all the interrupt request flags before setting the standby mode. If an interrupt source whose interrupt request flag and interrupt enable flag are both set exists, the initiated standby mode is released immediately after it is set (see Figure 6-1).
µPD750008 USER'S MANUAL Figure 7-1. Standby Mode Release Operation (2/2) (c) Release of the HALT mode by RESET signal Wait Note HALT instruction RESET signal Operating mode Operating mode HALT mode Oscillation Clock (d) Release of the HALT mode by the occurrence of an interrupt HALT instruction Standby release signal Operating mode Clock HALT mode Operating mode Oscillation Note The following two wait times can be selected by a mask option: 217/fX (21.8 ms at 6.00 MHz, 31.3 ms at 4.
CHAPTER 7 STANDBY FUNCTION Table 7-2. Selection of a Wait Time with BTM Wait timeNote BTM3 BTM2 BTM1 BTM0 – 0 0 – 0 – – ( ) indicates the value for f X = 6.00 MHz ( ) indicates the value for f X = 4.19 MHz 0 Approx. 2 20/f X (Approx. 175 ms) Approx. 2 20/f X (Approx. 250 ms) 1 1 Approx. 2 17/f X (Approx. 21.8 ms) Approx. 2 17/f X (Approx. 31.3 ms) 1 0 1 Approx. 2 15/f X (Approx. 5.46 ms) Approx. 2 15/f X (Approx. 7.81 ms) 1 1 1 Approx. 2 13/f X (Approx. 1.37 ms) Approx.
µPD750008 USER'S MANUAL 7.4 SELECTION OF A MASK OPTION For the standby function of the µPD750008, either of the following two values can be selected by a mask option as the wait time during which the start of oscillation deferred from the generation of a RESET signal: <1> 217 /fX (21.8 ms at 6.00 MHz, 31.3 ms at 4.19 MHz) <2> 215 /fX (5.46 ms at 6.00 MHz, 7.81 ms at 4.19 MHz) However, the µPD75P0016 dose not have a mask option and its wait time is fixed to 215/fX. 7.
CHAPTER 7 STANDBY FUNCTION VDD Voltage on VDD 0V P00/INT4 Wait CPU operation Operating mode Low-speed High-speed operation operation STOP mode 31.3 ms 31.3 ms INT4 INT4 STOP instruction (INT4 service program, MBE = 0) VSUB4: WAIT: PDOWN: SKT BR PORT0.0 PDOWN ; P00 = 1? ; Power-down SET1 SKT BTM.3 IRQBT ; Power-on ; Wait for 31.3 ms. BR SKT WAIT PORT0.0 ; Chattering check BR MOV PDOWN A,#0011B MOV MOV PCC,A XA.
µPD750008 USER'S MANUAL (2) Application of the HALT mode (at fX = 4.19 MHz) • The main system clock is switched to the subsystem clock on the falling edge of INT4. • The oscillation of the main system clock is stopped, and HALT mode is set. • In the standby mode, intermittent operation is performed at intervals of 0.5 s. • The subsystem clock is switched back to the main system clock on the rising edge of INT4. • INTBT is not used.
CHAPTER 7 STANDBY FUNCTION (Initialization) MOV MOV A,#0011B PCC,A ; High-speed mode MOV MOV XA,#05 WM,XA ; Subsystem clock EI EI IE4 IEW EI ; Enable interrupt (Main routine) SKT HALT NOP SKTCLR PORT0.0 ; Power normal? ; Power-down mode IRQW ; Power normal? ; Flag set for 0.5 second? BR CALL MAIN: . . . . . . . . . . (INT4 service routine) VINT4: SKT MAIN WATCH ; NO ; Clock subroutine PORT0.0 ; Power normal? MBE = 0 BR CLR1 PDOWN SCC.
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CHAPTER 8 RESET FUNCTION CHAPTER 8 RESET FUNCTION The µPD750008 is reset with the external reset signal (RESET) or the reset signal received from the basic interval timer/watchdog timer. When either reset signal is input, the internal reset signal is generated. Figure 8-1 shows the configuration of the reset circuit. Figure 8-1.
µPD750008 USER'S MANUAL Table 8-1. Status of the Hardware after a Reset (1/2) Generation of a RESET signal in a standby mode Generation of a RESET signal during operation µPD750004 4 low-order bits at address 0000H in program memory are set in PC bits 11 to 8, and the data at address 0001H are set in PC bits 7 to 0. 4 low-order bits at address 0000H in program memory are set in PC bits 11 to 8, and the data at address 0001H are set in PC bits 7 to 0.
CHAPTER 8 RESET FUNCTION Table 8-1.
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CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) The program memory in the µPD75P0016 consists of a one-time PROM (16384 x 8 bits). Writing to and verifying the contents of the one-time PROM is accomplished by using the pins shown in the table below. Note that address inputs are not used; instead, the address is updated using the clock input from the X1 pin.
µPD75008 USER'S MANUAL 9.1 OPERATING MODES WHEN WRITING TO AND VERIFYING THE PROGRAM MEMORY If +6 V is applied to the VDD pin and +12.5 V is applied to the VPP pin, the µPD75P0016 enters program memory write/verify mode. The specific operating mode is then selected by the setting of the MD0 through MD3 pins as listed in the table below. Operating mode specification Operating mode VPP VDD MD0 MD1 MD2 MD3 +12.
CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) The timing for steps (2) to (12) is shown below.
µPD75008 USER'S MANUAL 9.3 READING THE PROGRAM MEMORY The procedure for reading the contents of program memory is described below. The read is performed in the verify mode. (1) Pull low all unused pins to VSS by means of resistors. Bring X1 to low level. (2) Apply 5 V to VDD and VPP. (3) Wait 10 µs. (4) Select program memory address clear mode. (5) Apply 6 V to VDD and 12.5 V to VPP. (6) Select program inhibit mode. (7) Select verify mode.
CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) 9.4 SCREENING OF ONE-TIME PROM * Because of its structure, it is difficult for NEC to completely test the one-time PROM product before shipment. It is therefore recommended that screening be performed to verify the PROM contents after the necessary data has been written to the PROM and the product has been stored under the following conditions.
µPD75008 USER'S MANUAL [MEMO] 234
CHAPTER 10 MASK OPTION CHAPTER 10 MASK OPTION 10.1 * PIN The pins of the µPD750008 have the following mask options: Table 10-1. Selecting Mask Option of Pin Pin P40-P43 Mask Option Pull-up resistor can be connected in 1-bit units. P50-P53 P40 through P43 (port 4) or P50 through P53 (port 5) can be connected with pull-up resistors by mask option. The mask option can be specified in 1-bit units. If the pull-up resistor is connected by mask option, port 4 or 5 goes high on reset.
µPD750008 USER'S MANUAL 10.3 MASK OPTION FOR FEEDBACK RESISTOR OF SUBSYSTEM CLOCK For the subsystem clock of the µPD750008, whether to enable the feedback resistor is selected by the mask option. <1> Enable the feedback resistor (switches on or off by software). <2> Disable the feedback resistor (cuts by hardware). To use the feedback resistor after selecting <1>, turn the feedback resistor on by setting SOS.0 to 0 (for details, see (6) in Section 5.2.2). Select <1> to use the subsystem clock.
CHAPTER 11 INSTRUCTION SET CHAPTER 11 INSTRUCTION SET The instruction set of the µPD750008 is an improved and extended version of the 75X series instruction set.
µPD750008 USER'S MANUAL 11.1.2 Bit Manipulation Instructions With the µPD750008, a variety of instructions are available for bit manipulation. (a) Bit setting: SET1 mem.bit (b) Bit clearing: SET1 CLR1 mem.bit* mem.bit (c) Bit testing: CLR1 SKT mem.bit* mem.bit (d) Bit testing: SKT SKF mem.bit* mem.bit SKF mem.bit* (e) Bit testing and clearing: SKTCLR mem.bit* (f) Boolean operation: AND1 OR1 CY,mem.bit* CY,mem.bit* XOR1 CY,mem.bit* mem.
CHAPTER 11 INSTRUCTION SET 11.1.4 Number System Conversion Instructions An application may need to convert the result of a 4-bit data addition or subtraction (performed in binary) to a decimal number. A time-related application may require sexagesimal conversion. For this reason, the instruction set of the µPD750008 contains number system conversion instructions for converting the result of a 4-bit data addition or subtraction to a number in an arbitrary number system.
µPD750008 USER'S MANUAL 11.1.5 Skip Instructions and the Number of Machine Cycles Required for a Skip The instruction set of the µPD750008 is designed to organize a program by testing a condition with the skip function. When a skip instruction satisfies the skip condition, the immediately following instruction is skipped to execute the instruction immediately after the skipped instruction.
CHAPTER 11 INSTRUCTION SET 11.2 INSTRUCTION SET AND OPERATION (1) Operand identifier and description The operand field of an instruction must contain an operand coded according to the description rule for the operand identifier of the instruction. (Refer to RA75X Assembler Package User’s Manual: Language (EEU-1343) for detailed information.) When there are multiple descriptions for an identifier, one item is to be selected.
µPD750008 USER'S MANUAL (2) Legend A: 242 A register; 4-bit accumulator B: C: B register C register D: E: D register E register H: L: H register L register X: XA: X register Register pair (XA), 8-bit accumulator BC: DE: Register pair (BC) Register pair (DE) HL: XA’: Register pair (HL) Extended register pair (XA’) BC’: DE’: Extended register pair (BC’) Extended register pair (DE’) HL’: PC: Extended register pair (HL’) Program counter SP: CY: Stack pointer Carry flag, bit accumulator PSW
CHAPTER 11 INSTRUCTION SET (3) Explanation of symbols used for the addressing area column *1 MB = MBE · MBS (MBS = 0, 1, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (00H – 7FH) MB = 15 (F80H – FFFH) MBE = 1 : MB = MBS (MBS =0, 1, 15) *4 MB = 15, fmem = FB0H – FBFH, FF0H – FFFH *5 MB = 15, pmem = FC0H – FFFH *6 µPD750004 addr, addr1 = 0000H – 0FFFH µPD750006 addr, addr1 = 0000H – 17FFH µPD750008 addr, addr1 = 0000H – 1FFFH µPD75P0016 addr, addr1 = 0000H – 3FFFH *7 Data memory addressing addr ,
µPD750008 USER'S MANUAL (4) Explanation of the machine cycle column S represents the number of machine cycles required when a skip instruction with the skip function performs a skip operation.
CHAPTER 11 INSTRUCTION SET In struction Mnemonic Transfer MOV XCH Operation Number Machine of cycle bytes Operation Addressing area Skip condition A,#n4 1 1 A <– n4 String-effect A reg1,#n4 2 2 reg1 <– n4 XA,#n8 2 2 XA <– n8 String-effect A HL,#n8 2 2 HL <– n8 String-effect B rp2,#n8 2 2 rp2 <– n8 A,@HL 1 1 A <– (HL) *1 A,@HL+ 1 2+S A <– (HL), then L <– L+1 *1 L=0 A,@HL– 1 2+S A <– (HL), then L <– L–1 *1 L=FH A,@rpa1 1 1 A <– (rpa1) *2 XA,@HL 2 2 XA
µPD750008 USER'S MANUAL Instruction Mnemonic Operand MOVT XA,@PCDE Number Machine of cycle bytes 1 3 Operation Addressing area Skip condition • µPD750004 XA <– (PC11-8+DE)ROM • µPD750006, µPD750008 XA <– (PC12-8+DE)ROM Table reference • µPD75P0016 XA <– (PC13-8+DE)ROM XA,@PCXA 1 3 • µPD750004 XA <– (PC11-8+XA)ROM • µPD750006, µPD750008 XA <– (PC12-8+XA)ROM • µPD75P0016 XA <– (PC13-8+XA)ROM Bit transfer MOV1 Arithmetic/logical ADDS ADDC SUBS SUBC XA,@BCDE 1 3 XA <– (BCDE)ROMNote *
CHAPTER 11 INSTRUCTION SET Instruction Mnemonic Arithmetic/logical AND Accumulator manipulation Increment/decrement Number Machine of cycle bytes Operation Addressing area Skip condition A,#n4 2 2 A <– A n4 A,@HL 1 1 A <– A (HL) XA,rp’ 2 2 XA <– XA rp’ rp’1,XA 2 2 rp’1 <– rp’1 XA A,#n4 2 2 A <– A n4 A,@HL 1 1 A <– A (HL) XA,rp’ 2 2 XA <– X A rp’ rp’1,XA 2 2 rp’1 <- rp’1 XA A,#n4 2 2 A <– A n4 A,@HL 1 1 A <– A (HL) XA,rp’ 2 2 XA <– XA rp’ rp’1,XA 2 2
µPD750008 USER'S MANUAL In struction Mnemonic SET1 CLR1 Memory bit manipulation SKT SKF OR1 XOR1 Number Machine of cycle bytes Operation Addressing area Skip condition mem.bit 2 2 (mem.bit) <– 1 *3 fmem.bit 2 2 (fmem.bit) <– 1 *4 pmem.@L 2 2 (pmem7-2 +L3-2.bit(L 1-0)) <– 1 *5 @H+mem.bit 2 2 (H+mem 3-0.bit) <– 1 *1 mem.bit 2 2 (mem.bit) <– 0 *3 fmem.bit 2 2 (fmem.bit) <– 0 *4 pmem.@L 2 2 (pmem7-2 +L3-2.bit(L 1-0)) <– 0 *5 @H+mem.bit 2 2 (H+mem 3-0.
CHAPTER 11 INSTRUCTION SET In struction Mnemonic BR Operand addr Number Machine of cycle bytes — — Operation • µPD750004 PC11-0 <– addr The assembler selects the most adequate instruction from instructions below. • BR !addr • BR $addr • BRCB !caddr Addressing area Skip condition *6 Branch • µPD750006, µPD750008 PC12-0 <– addr The assembler selects the most adequate instruction from instructions below.
µPD750008 USER'S MANUAL In struction Mnemonic Operand BR !addr Number Machine of cycle bytes 3 3 Operation • µPD750004 PC11-0 <– addr Addressing area *6 • µPD750006, µPD750008 PC12-0 <– addr • µPD75P0016 PC13-0 <– addr $addr 1 2 • µPD750004 PC11-0 <– addr *7 • µPD750006, µPD750008 PC12-0 <– addr • µPD75P0016 PC13-0 <– addr $addr1 1 2 • µPD750004 PC11-0 <– addr1 *7 • µPD750006, µPD750008 PC12-0 <– addr1 • µPD75P0016 PC13-0 <– addr1 2 3 Branch PCDE • µPD750004 PC11-0 <– PC11-8+DE • µP
CHAPTER 11 INSTRUCTION SET In struction Mnemonic Operand BR BCXA Number Machine of cycle bytes 2 3 Operation • µPD750004 PC11-0 <– BCXANote 1 Addressing area Skip condition * 11 • µPD750006, µPD750008 PC12-0 <– BCXANote 2 • µPD75P0016 PC13-0 <– BCXANote 3 !addr1 3 3 Branch BRANote 1 • µPD750004 PC11-0 <– addr * 11 • µPD750006, µPD750008 PC12-0 <– addr • µPD75P0016 PC13-0 <– addr1 BRCB !caddr 2 2 • µPD750004 PC11-0 <– caddr11-0 *8 • µPD750006, µPD750008 PC12-0 <– PC12+caddr11-0 • µP
µPD750008 USER'S MANUAL In struction Mnemonic Operand CALLNote !addr Number Machine of cycle bytes 3 3 Operation • µPD750004 (SP–3) <– MBE,RBE, 0, 0 (SP–4)(SP–1)(SP–2) <– PC11-0 PC11-0 <– addr, SP <– SP–4 Addressing area Skip condition *6 • µPD750006, µPD750008 (SP–3) <– MBE,RBE, 0, PC12 (SP–4)(SP–1)(SP–2) <– PC11-0 PC12-0 <– addr, SP <– SP–4 • µPD75P0016 (SP–3) <– MBE,RBE, PC13, PC12 (SP–4)(SP–1)(SP–2) <– PC11-0 PC13-0 <– addr1, SP <– SP–4 Subroutine stack control 4 • µPD750004 (SP–2) <– x,
CHAPTER 11 INSTRUCTION SET In struction Mnemonic Operand CALLFNote !faddr Number Machine of cycle bytes 2 3 Operation • µPD750004 (SP–2) –> x, x, MBE,RBE (SP–6)(SP–3)(SP–4) <– PC11-0 (SP–5) <– 0, 0, 0, 0 PC11-0 <– 0+faddr, SP <– SP–6 Addressing area Skip condition *9 • µPD750006, µPD750008 (SP–2) –> x, x, MBE,RBE (SP–6)(SP–3)(SP–4) <– PC11-0 (SP–5) <– 0, 0, 0, PC12 PC12-0 <– 00+faddr, SP <– SP–6 • µPD75P0016 (SP–2) <– x, x, MBE,RBE (SP–6)(SP–3)(SP–4) <– PC11-0 (SP–5) <– 0, 0, PC13, PC12 PC13-0
µPD750008 USER'S MANUAL In struction Mnemonic RETSNote Operand Number Machine of cycle bytes 1 3+S Operation • µPD750004 MBE, RBE, 0, 0 <– (SP+1) PC11-0 <– (SP)(SP+3)(SP+2) SP <– SP+4 Then skip unconditionally Addressing area Skip condition Unconditionally • µPD750006, µPD750008 MBE, 0, 0, PC12 <– (SP+1) PC11-0 <– (SP)(SP+3)(SP+2) SP <– SP+4 Then skip unconditionally • µPD75P0016 MBE, RBE, PC13, PC12 <– (SP+1) PC11-0 <– (SP)(SP+3)(SP+2) SP <– SP+4 Then skip unconditionally Subroutine stack contr
CHAPTER 11 INSTRUCTION SET In struction Mnemonic Operand Subroutine stack control RETINote 1 1 Addressing area Skip condition • µPD750004 0, 0, 0, 0 <– (SP+1) PC11-0 <– (SP)(SP+3)(SP+2) PSW <– (SP+4)(SP+5), SP <– SP+6 • µPD75P0016 0, 0, PC13, PC12 <– (SP+1) PC11-0 <– (SP)(SP+3)(SP+2) PSW <– (SP+4)(SP+5), SP <– SP+6 PUSH rp 1 1 (SP–1)(SP–2) <– rp, SP <– SP–2 BS 2 2 (SP–1) <– MBS, (SP–2) <– RBS, SP <– SP–2 rp 1 1 rp <– (SP+1)(SP), SP <– SP+2 BS 2 2 MBS <– (SP+1), RBS <– (SP), SP <– S
µPD750008 USER'S MANUAL In struction Mnemonic SEL GETINote Operand Number Machine of cycle bytes Operation RBn 2 2 RBS <– n (n=0 - 3) MBn 2 2 MBS <– n (n=0, 1, 15) taddr 1 3 • µPD750004 When the TBR instruction is used PC11-0 <– (taddr)3-0+(taddr+1) Addressing area Skip condition * 10 When the TCALL instruction is used (SP–4)(SP–1)(SP–2) <– PC11-0 (SP–3) <– MBE, RBE, 0, 0 PC11-0 <– (taddr)3-0+(taddr+1) SP <– SP–4 When an instruction other than the TBR or TCALL instruction is used Execu
CHAPTER 11 INSTRUCTION SET In struction Mnemonic Operand 1 Operation 3 • µPD750004 When the TBR instruction is used PC11-0 <– (taddr)3-0+(taddr+1) 4 When the TCALL instruction is used (SP–6)(SP–3)(SP–4) <– PC11-0 (SP–5) <– 0, 0, 0, 0 (SP–2) <– x, x, MBE, RBE PC11-0 <– (taddr)3-0+(taddr+1) SP <– SP–6 3 When an instruction other than the TBR or TCALL instruction is used Execution of (taddr)(taddr+1) instruction 3 • µPD750006, µPD750008 When the TBR instruction is used PC12-0 <– (taddr)4-0+(taddr+
µPD750008 USER'S MANUAL 11.
CHAPTER 11 INSTRUCTION SET (2) Bit manipulation addressing instruction codes *1 in the operand field indicates that there are three types of bit manipulation addressing, fmem.bit, pmem.@L, and @H+mem.bit. The table below lists the second byte *1 fmem.bit *2 of an instruction code corresponding to the above addressing. Second byte of instruction code Accessible bits 1 0 B1 B0 F3 F2 F1 F0 FB0H-FBFH manipulatable bits 1 1 B1 B0 F3 F2 F1 F0 FF0H-FFFH manipulatable bits pmem.
µPD750008 USER'S MANUAL Instruction Transfer Mnemonic MOV XCH Table reference Bit transfer 260 MOVT MOV1 Instruction code Operand B1 B2 A,#n4 0 1 1 1 I3 I2 I1 I0 reg1,#n4 1 0 0 1 1 0 rp,#n8 1 0 0 0 1 P2 P1 1 A,@rpa1 1 1 1 0 0 Q2 Q1 Q0 XA,@HL 1 0 1 0 1 0 1 0 @HL,A 1 1 1 0 1 0 0 0 @HL,XA 1 0 1 0 1 0 1 A,mem 1 0 1 0 0 0 XA,mem 1 0 1 0 0 mem,A 1 0 0 1 mem,XA 1 0 0 A,reg 1 0 XA,rp’ 1 reg1,A 1 0 I3 I2 I1 I0 1 B3 R 2 R
CHAPTER 11 INSTRUCTION SET Instruction Arithmetic/ ADDS logical ADDC SUBS SUBC AND OR XOR Accumulator RORC manipulation Instruction code Mnemonic NOT Operand B1 B2 B3 A,#n4 0 1 1 0 I 3 I2 I 1 I0 XA,#n8 1 0 1 1 1 0 0 1 A,@HL 1 1 0 1 0 0 1 0 XA,rp’ 1 0 1 0 1 0 1 0 1 1 0 0 1 P2 P1 P0 rp’1,XA 1 0 1 0 1 0 1 0 1 1 0 0 0 P2 P1 P0 A,@HL 1 0 1 0 1 0 0 1 XA,rp’ 1 0 1 0 1 0 1 0 1 1 0 1 1 P2 P1 P0 rp’1,XA 1 0 1 0 1 0 1 0 1
µPD750008 USER'S MANUAL Instruction Mnemonic Increment/ INCS decrement Instruction code Operand B1 B2 B3 reg 1 1 0 0 0 R 2 R1 R 0 rp1 1 0 0 0 1 P2 P1 0 @HL 1 0 0 1 1 0 0 1 0 mem 1 0 0 0 0 0 1 0 D7 D6 D5 D4 D3 D 2 D1 D 0 reg 1 1 0 0 1 R 2 R1 R 0 rp’ 1 0 1 0 1 0 1 0 0 1 P2 P1 P 0 reg,#n4 1 0 0 1 1 0 1 0 I3 I2 I1 I0 0 R 2 R1 R 0 @HL,#n4 1 0 0 1 1 0 0 1 0 1 1 0 I3 I2 I1 I0 A,@HL 1 0 0 0 0 0 0 0 XA,@HL 1 0 1 0 1
CHAPTER 11 INSTRUCTION SET Instruction Branch Subroutine stack control Mnemonic BR 1 0 1 0 $addr1 0 (+16) to (+2) 0 0 0 A 3 A2 A 1 A0 (–1) to (–15) 1 1 1 1 S 3 S2 S 1 S0 PCDE 1 0 0 1 1 0 0 1 0 0 0 0 0 1 0 0 PCXA 1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 BCDE 0 0 0 0 0 1 0 1 BCXA 1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 BRA !addr1 1 0 1 1 1 0 1 0 0 BRCB !caddr 0 1 0 1 CALL !addr 1 0 1 0 1 0 1 1 0 CALLA !addr1 1 0 1 1 1 0
µPD750008 USER'S MANUAL 11.4 FUNCTIONS AND APPLICATIONS OF THE INSTRUCTIONS This section explains functions and applications of the instructions. For the µPD750004, µPD750006, µPD750008, and µPD75P0016, usable instructions and their functions in Mk I mode are different from those in Mk II mode. Read the following explanation.
CHAPTER 11 INSTRUCTION SET MOV reg1,#n4 Function: reg1 <– n4 n4 = I 3-0: 0-FH Transfers the 4-bit immediate data n4 to A register reg1 (X, H, L, D, E, B, C). MOV XA,#n8 Function: XA <– n8 * n8 = I7-0: 00H-FFH Transfers the 8-bit immediate data n8 to register pair XA. The string effect can be utilized.
µPD750008 USER'S MANUAL Then skips the immediately following instruction. When HL– (automatic decrement) is specified for the register pair, automatically decrements the contents of the L register by one after the data transfer, and continues the operation until the contents are set to FH. Then skips the immediately following instruction.
CHAPTER 11 INSTRUCTION SET MOV XA,mem Function: A <– (mem), X <– (mem+1) mem = D7-0: 00H-FEH Transfers the data at the data memory location addressed by the 8-bit immediate data mem to the A register, and transfers the data at the next address to the X register. An even address can be specified with mem. Example The data at addresses 40H and 41H are transferred to the XA register pair.
µPD750008 USER'S MANUAL MOV reg1,A Function: reg1 <– A Transfers the contents of the A register to register reg1 (X, H, L, D, E, B, C). MOV rp’1,XA Function: rp’1 <– XA Transfers the contents of the XA register pair to register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, BC’).
CHAPTER 11 INSTRUCTION SET XCH XA,@HL Function: A <–> (HL), X <–> (HL+1) Exchanges the contents of the A register with the data at the data memory location addressed by the HL register pair, and exchanges the contents of the X register with the data at the next memory address. However, if the contents of the L register are odd- numbered, an address with the low-order bit ignored is specified.
µPD750008 USER'S MANUAL 11.4.2 Table Reference Instructions MOVT XA,@PCDE Function: For the µPD750006 and µPD750008 XA <– ROM (PC12-8+DE) Transfers the low-order four bits of the table data in program memory to the A register, and the high-order four bits to the X register. The table data is addressed by the program counter (PC) with its low-order eight bits (PC7-0) exchanged with the contents of the DE register pair.
CHAPTER 11 INSTRUCTION SET For example, if MOVT XA,@PCDE is located at a as shown above, the table data in page 3 specified by the contents of the DE register pair is transferred to the XA register pair instead of that in page 2. Example The 16-byte data at addresses xxF0H-xxFFH in program memory is transferred to addresses 30H-4FH in data memory.
µPD750008 USER'S MANUAL MOVT XA,@BCXA Function: For the µPD750006 and µPD750008 XA <– (BCXA) ROM Transfers the low-order four bits of the table data (eight bits) in program memory to the A register, and the high-order four bits to the X register. The table data is addressed by the low-order one bit of the B register and the contents of the C, X, and A registers. The table area must have necessary data loaded by an assembler pseudo instruction (DB instruction).
CHAPTER 11 INSTRUCTION SET 11.4.3 Bit Transfer Instructions MOV1 CY,fmem.bit MOV1 CY,pmem.@l MOV1 CY,@H+mem.bit Function: CY <– (bit specified in operand) Transfers the data memory bit specified by bit manipulation addressing (fmem.bit, pmem.@L, @H+mem.bit) to the carry flag (CY). MOV1 fmem.bit,CY MOV1 pmem.@L,CY MOV1 @H+mem.bit,CY Function: (bit specified in operand) <– CY Transfers the carry flag (CY) bit to the data memory bit specified by bit manipulation addressing (fmem.bit, pmem.@L,@H+mem.
µPD750008 USER'S MANUAL ADDS XA,#n8 Function: XA <– XA+n8 ; Skip if carry. n8 = I7-0: 00H-FFH Adds the 8-bit immediate data n8 to the contents of the XA register pair in binary, then skips the next instruction if the addition generates a carry. The carry flag is not affected. ADDS A,@HL Function: A <– A+(HL) ; Skip if carry.
CHAPTER 11 INSTRUCTION SET ADDC XA,rp’ Function: XA, CY <– XA+rp’+CY Adds the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’, BC’) together with the carry flag to the contents of the XA register pair in binary. If the addition generates a carry, the carry flag is set. If no carry is generated, the carry flag is reset.
µPD750008 USER'S MANUAL SUBS rp’1,XA Function: rp’1 <– rp’1+XA ; Skip if borrow Subtracts the contents of the XA register pair from the contents of register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, BC’), then sets the result in register pair rp’1. If the subtraction generates a borrow, the immediately following instruction is skipped. The carry flag is not affected.
CHAPTER 11 INSTRUCTION SET AND A,@HL Function: A <– A (HL) ANDs the contents of the A register with the data at the data memory location addressed by the HL register pair, then sets the result in the A register. AND XA,rp’ Function: XA <– XA rp’ ANDs the contents of the XA register pair with the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’, BC’), then sets the result in the XA register pair.
µPD750008 USER'S MANUAL OR rp’1,XA Function: rp’1 <– rp’ XA ORs the contents of register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, BC’) with the contents of the XA register pair, then sets the result in register pair rp’1. XOR A,#n4 Function: A <– A n4 n4 = I3-0: 0-FH Exclusive-ORs the contents of the A register with the 4-bit immediate data n4, then sets the result in the A register. Example The high-order four bits of an accumulator is inverted.
CHAPTER 11 INSTRUCTION SET 11.4.5 Accumulator Manipulation Instructions RORC A Function: CY <- A0, An-1 <- An, A3 <- CY (n = 1–3) Rotates the contents of the A register (4-bit accumulator) through the carry flag one bit position to the right. A •• •• •• •• CY 3 2 1 0 Before execution 0 0 1 0 1 After execution 1 0 0 1 0 RORC A NOT A Function: A <– A Obtains the one’s complement of the A register (4-bit accumulator), that is, inverts each bit of the A register. 11.4.
µPD750008 USER'S MANUAL INCS mem Function: (mem) <– (mem)+1 ; Skip if (mem) = 0, mem = D7-0: 00H-FFH Increments the data at the data memory location addressed by the 8-bit immediate data mem. If the result of increment produces data that is 0, the immediately following instruction is skipped. DECS reg Function: reg <– reg–1 ; Skip if reg = FH Decrements the contents of register reg (X, A, H, L, D, E, B, C). If the result of decrement produces reg = FH, the immediately following instruction is skipped.
CHAPTER 11 INSTRUCTION SET SKE XA,@HL Function: Skip if A = (HL) and X = (HL+1) Skips the immediately following instruction if the contents of the A register match the data at the data memory location addressed by the HL register pair, and the contents of the X register match the data at the next address in data memory. However, if the contents of the L register are odd- numbered, an address with the lowest-order bit ignored is specified.
µPD750008 USER'S MANUAL NOT1 CY Function: CY <– CY Inverts the carry flag. If it is 0, it is set to 1, or vice versa. 11.4.9 Memory Bit Manipulation Instructions SET1 mem.bit Function: (mem.bit) <– 1 mem = D7-0: 00H-FFH, bit = B1-0: 0–3 Sets the bit specified by the 2-bit immediate data bit at the address specified by the 8-bit immediate data mem. SET1 fmem.bit SET1 pmem.@L SET1 @H+mem.
CHAPTER 11 INSTRUCTION SET Skips the immediately following instruction if the bit specified by the 2-bit immediate data bit at the address specified by the 8-bit immediate data mem is 1. SKT fmem.bit SKT pmem.@L SKT @H+mem.bit Function: Skip if (bit specified in operand) = 1 Skips the immediately following instruction if the bit in data memory specified by bit manipulation addressing (fmem.bit, pmem.@L, @H+mem.bit) is set to 1. SKF mem.bit Function: Skip if (mem.
µPD750008 USER'S MANUAL AND1 CY, fmem.bit AND1 CY, pmem.@L AND1 CY, @H+mem.bit Function: CY <– CY (bit specified in operand) ^ ANDs the content of the carry flag with the bit in data memory specified by bit manipulation addressing (fmem.bit, pmem.@L, @H+mem.bit), then sets the result in the carry flag. OR1 CY, fmem.bit OR1 CY, pmem.@L OR1 CY, @H+mem.
CHAPTER 11 INSTRUCTION SET II BR addr1 Function: For the µPD750008 PC12-0 <– addr1 addr1 = 0000H-1FFFH Branches to the address specified by the immediate data addr1. This instruction is an assembler pseudo instruction, and the assembler automatically replaces this instruction with the BRA !addr1 instruction, BR !addr instruction, BRCB !caddr instruction, or BR $addr1 instruction as required at assembly time.
µPD750008 USER'S MANUAL Remark "Function" in this section is applicable to the µPD750008 whose program counter consists of 13 bits (addr = 0000H to 1FFFH). However, this is also applicable to the µPD750004 whose program counter consists of 12 bits (addr = 0000H to 0FFFH), the µPD750006 whose program counter consists of 13 bits (addr = 0000H to 17FFH), and the µPD75P0016 whose program counter consists of 14 bits (addr = 0000H to 3FFFH).
CHAPTER 11 INSTRUCTION SET BR PCDE Function: For the µPD750008 PC12-0 <– PC12-8 + DE PC7- 4 <– D, PC3-0 <– E Branches to the address specified by the program counter whose low-order 8 bits (PC7-0) have been replaced with the contents of the DE register pair. The high-order bits of the program counter are not affected. Caution The BR PCDE instruction usually causes a branch within the page containing the instruction.
µPD750008 USER'S MANUAL BR BCDE Function: For the µPD750008 PC12-0 <– BCDE Branches to the address specified by the program counter whose bits have been replaced with the contents of the B0, C, D, and E registers. 12 11 87 43 0 PC 0 3 B 0 3 C 0 3 D 0 E BR BCXA Function: For the µPD750008 PC12-0 <– BCXA Branches to the address specified by the program counter whose bits have been replaced with the contents of the B0, C, X, and A registers.
CHAPTER 11 INSTRUCTION SET 11.4.
µPD750008 USER'S MANUAL I/II CALLF !faddr Function: For the µPD750008 [Mk I mode] (SP–1) <– PC7-4, (SP–2) <– PC3-0 (SP–3) <– MBE, RBE, 0, PC12 (SP–4) <– PC11-8, SP <– SP – 4 PC12-0 <– 00 + faddr faddr = 0000H – 07FFH [Mk II mode] (SP–2) <– x, x, MBE, RBE (SP–3) <– PC7-4, (SP–4) <– PC3-0 (SP–5) <– 0, 0, 0, PC12, (SP–6) <– PC11-8 SP <– SP–6 PC12-0 <– 00 + faddr faddr = 0000H – 07FFH Saves the contents of the program counter (PC; Return address), memory bank enable flag (MBE), and register bank enable flag
CHAPTER 11 INSTRUCTION SET I/II RET Function: For the µPD750008 [Mk I mode] PC11-8 <– (SP) MBE, RBE, 0, PC12 <– (SP+1) PC3-0 <– (SP+2) PC7-4 <– (SP+3), SP <– SP+4 [Mk II mode] PC11-8 <– (SP), x, x, x, PC12 <– (SP+1) PC3-0 <– (SP+2), PC7-4 <– (SP+3) x, x, MBE, RBE <– (SP+4) SP <– SP+6 Restores the program counter (PC), memory bank enable flag (MBE), and register bank enable flag (RBE) with the data at the data memory location (stack) addressed by the stack pointer (SP), then increments the contents of
µPD750008 USER'S MANUAL Remark "Function" in this section is applicable to the µPD750008 whose program counter consists of 13 bits (addr = 0000H to 1FFFH). However, this is also applicable to the µPD750004 whose program counter consists of 12 bits (addr = 0000H to 0FFFH),the µPD750006 whose program counter consists of 13 bits (addr = 0000H to 17FFH),and the µPD75P0016 whose program counter consists of 14 bits (addr = 0000H to 3FFFH).
CHAPTER 11 INSTRUCTION SET PUSH BS Function: (SP–1) <– MBS, (SP–2) <– RBS, SP <– SP–2 Saves the contents of the memory bank select register (MBS) and the register bank select register (RBS) to the data memory location (stack) addressed by the stack pointer (SP), then decrements SP. POP rp Function: rpL <– (SP), rpH <– (SP+1), SP <– SP+2 Restores register pair rp (XA, HL, DE, BC) with the data at the data memory location (stack) addressed by the stack pointer (SP), then increments SP.
µPD750008 USER'S MANUAL DI IExxx Function: IExxx <– 0 xxx = N5, N2-0 Resets an interrupt enable flag (IExxx) to 0 to disable an interrupt. (xxx = BT, CSI, T0, T1, W, 0, 1, 2, 4) 11.4.13 I/O Instructions IN A,PORTn Function: A <– PORTn n = N3-0: 0–8 Transfers the contents of the port specified by PORTn (n = 0-8) to the A register. Caution Before this instruction can be executed, MBE = 0 or (MBE = 1, MBS = 15) must be set. A number from 0 to 8 can be specified as n.
CHAPTER 11 INSTRUCTION SET Caution Before this instruction can be executed, MBE = 0 or (MBE = 1, MBS = 15) must be set. Only 4 or 6 can be specified as n. 11.4.14 CPU Control Instructions HALT Function: PCC.2 <– 1 Sets the HALT mode. (This instruction is used to set bit 2 of the processor clock control register.) Caution The instruction immediately following a HALT instruction must be a NOP instruction. STOP Function: PCC.3 <– 1 Sets the STOP mode.
µPD750008 USER'S MANUAL I/II GETI taddr Function: taddr = T5-0, 0 : 20H-7FH For the µPD750008 [Mk I mode] • When a table defined by the TBR instruction is referenced PC12-0 <– (taddr) 4-0 + (taddr+1) • When a table defined by the TCALL instruction is referenced (SP–1) <– PC7-4, (SP–2) <– PC3-0 (SP–3) <– MBE, RBE, 0, PC12 (SP–4) <– PC11-8 PC12-0 <– (taddr) 4-0 + (taddr+1) SP <– SP–4 • When a table defined by an instruction other than the TBR or TCALL instruction is referenced An instruction using (taddr)
CHAPTER 11 INSTRUCTION SET Caution All 2-byte instructions (except the BRCB instruction and CALLF instruction) set in the reference table must be 2-machine-cycle instructions. Pairs of 1-byte instructions can be set as indicated in the table below.
µPD750008 USER'S MANUAL Example MOV HL, #00H MOV XA, #FFH CALL SUB1 BR are replaced with GETI instructions.
APPENDIX A FUNCTIONS OF THE µPD75008, µPD750008, AND µPD75P0016 (1/2) Item µPD750008 µPD75P0016 Masked ROM 0000H - 1F7FH (8064 x 8 bits) Masked ROM 0000H - 1FFFH (8192 x 8 bits) One-time PROM 0000H - 3FFFH (16384 x 8 bits) Program memory µPD75008 000H - 1FFH (512 x 4 bits) 75X standard CPU 75XL CPU (equivalent to the 75X high-end CPU) Oscillation settling time 31.3 ms 215/fX, 217/fX (selectable by a mask option) When selecting the main system clock 0.95, 1.91, 15.3 µs (when operating at 4.
µPD750008 USER'S MANUAL (2/2) Item µPD75008 channels Basic interval timer: 1 Timer/event counter: 1 Clock timer: 1 µPD750008 µPD75P0016 Timer 3 • • • Clock output (PCL) F, 524, 262, 65.5 kHz (when the main system clock operates at 4.19 MHz) • F, 524, 262, 65.5 kHz (when the main system clock operates at 4.19 MHz) • F, 750, 375, 93.7 kHz (when the main system clock operates at 6.0 MHz) BUZ output (BUZ) 2 kHz • 2, 4, 32 kHz (when the main system clock operates at 4.19 MHz) • 2.86, 5.72, 45.
APPENDIX B DEVELOPMENT TOOLS The following development tools are provided for the development of a system which employs the µPD750008. In the 75XL series, use the common relocatable assembler together with a device file of each model. RA75X relocatable assembler Host machine PC-9800 series IBM PC/AT and compatibles Device file Host machine PC-9800 series IBM PC/AT and compatibles OS MS-DOS Ver. 3.30 to Ver. 6.2Note See "OS for IBM PC." OS MS-DOS Ver. 3.30 to Ver. 6.2Note See "OS for IBM PC.
µPD750008 USER'S MANUAL PROM programming tools Hardware Software PG-1500 The PG-1500 PROM programmer is used together with an accessory board and optional program adapter. It allows the user to program a single chip microcomputer containing PROM from a standalone terminal or a host machine. The PG-1500 can be used to program typical 256K-bit to 4M-bit PROMs. PA-75P008CU The PA-75P008CU is a PROM programmer adapter provided for the µPD75P008CU/ GB and µPD75P0016CU/GB.
APPENDIX B DEVELOPMENT TOOLS Debugging Tools The in-circuit emulators (IE-75000-R and IE-75001-R) are provided to debug programs used for the µPD750008. The following system is shown below. IE-75000-RNote 1 The IE-75000-R is an in-circuit emulator used to debug hardware and software when developing an application system using the 75X series and 75XL series. Use this emulator together with optional emulation board IE-75300-R-EM and emulation probe to develop application systems of the µPD750008 subseries.
µPD750008 USER'S MANUAL * OS for IBM PC The following IBM PC OSs are supported. OS PC DOS Version Ver. 3.1 to Ver. 6.3 J6.1/VNote to J6.3/VNote Note MS-DOS Ver. 5.0 to Ver. 6.22 5.0/VNote to J6.2/VNote IBM DOSTM J5.02/VNote Only English version is supported. Caution These software products cannot use the task swap function, which is available in MS-DOS Ver. 5.00 or later.
Device file Relocatable assembler + Host machine PC-9800 series IBM PC/AT (Symbolic debugging is possible.) RS-232-C PG-1500 controller IE control program Centronics interface PA-75P008CU Programmer adapter + PG-1500 PROM programmer Emulation board IE-75300-R-EMNote 1 IE-75000-R or IE-75001-R In-circuit emulator EP-75008CU-R EP-75008GB-R Emulation probe Note 2 Target sysytem 2. EV-9200G-44 the IE-75300-R-EM (to be ordered). Notes 1.
µPD750008 USER'S MANUAL Drawings of the Conversion Socket (EV-9200G-44) and Recommended Pattern on Boards Figure B-1.
APPENDIX B DEVELOPMENT TOOLS Figure B-2. Recommended Pattern on Boards for the EV-9200G-44 (Reference) EV-9200G-44-P0 Caution Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (IEI-1207).
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APPENDIX C MASKED ROM ORDERING PROCEDURE After program development is completed, the masked ROM is ordered by the following procedure: <1> Advance notice of an order for masked ROM Give advance notice of masked ROM ordering to a special agent or NEC’s Sales Department, otherwise the ordered products may be delivered with delay. <2> Preparation of media for ordering Use three UV-EPROMs having the same contents, or 3.5- or 5.25-inch IBM format floppy disk in ordering a masked ROM.
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APPENDIX D INSTRUCTION INDEX D.1 INSTRUCTION INDEX (BY FUNCTION) [Transfer instructions] MOVT XA,@PCXA ... 246, 271 MOV A,#n4 ... 245, 264 MOVT XA,@BCDE ... 246, 272 MOV reg1,#n4 ... 245, 265 MOVT XA,@BCXA ... 246, 272 MOV XA,#n8 ... 245, 265 MOV HL,#n8 ... 245, 265 [Bit transfer instructions] MOV rp2,#n8 ... 245, 265 MOV1 CY,fmem.bit ... 246, 273 MOV A,@HL ... 245, 265 MOV1 CY,pmem.@L ... 246, 273 MOV A,@HL+ ... 245, 265 MOV1 CY,@H+mem.bit ... 246, 273 MOV A,@HL– ...
µPD750008 USER'S MANUAL OR A,@HL ... 247, 277 SET1 pmem.@L ... 248, 282 OR XA,rp’ ... 247, 277 SET1 @H+mem.bit ... 248, 282 OR rp’1,XA ... 247, 278 CLR1 mem.bit ... 248, 282 XOR A,#n4 ... 247, 278 CLR1 fmem.bit ... 248, 282 XOR A,@HL ... 247, 278 CLR1 pmem.@L ... 248 282 XOR XA,rp’ ... 247, 278 CLR1 @H+mem.bit ... 248, 282 XOR rp’1,XA ... 247, 278 SKT mem.bit ... 248, 283 SKT fmem.bit ... 248, 283 [Accumulator manipulation instructions] SKT pmem.@L ... 248, 283 RORC A ...
APPENDIX D INSTRUCTION INDEX BRA !addr1 ... 251, 285 BRCB !caddr ... 251, 286 TBR addr ... 256, 288 [Subroutine stack control instructions] CALLA !addr1 ... 251, 289 CALL !addr ... 252, 289 CALLF !faddr ... 252, 290 TCALL !addr ... 256, 290 RET ... 253, 291 RETS ... 254, 291 RETI ... 254, 292 PUSH rp ... 255, 292 PUSH BS ... 255, 293 POP rp ... 255, 293 POP BS ... 255, 293 [Interrupt control instructions] EI ... 255, 293 EI IExxx ... 255, 293 DI ... 255, 293 DI IExxx ...
µPD750008 USER'S MANUAL D.2 INSTRUCTION INDEX (ALPHABETICAL ORDER) CLR1 mem.bit ... 248, 282 A,@HL ... 246, 274 CLR1 pmem.@L ... 248 282 ADDC rp’1,XA .. 246, 275 CLR1 @H+mem.bit ... 248, 282 ADDC XA,rp’ ... 246, 275 ADDS A,#n4 ... 246, 273 [D] ADDS A,@HL ... 246, 274 DECS reg ... 247, 280 ADDS rp’1,XA ... 246, 274 DECS rp’ ... 247, 280 ADDS XA,rp’ ... 246, 274 DI ... 255, 293 ADDS XA,#n8 ... 246, 274 DI AND A,#n4 ... 247, 276 AND A,@HL ... 247, 277 AND rp’1,XA ...
APPENDIX D INSTRUCTION INDEX MOV A,@rpa1 ... 245, 265 OR1 CY,@H+mem.bit ... 248, 284 MOV HL,#n8 ... 245, 265 OUT PORTn,A ... 255, 294 MOV mem,A ... 245, 267 OUT PORTn,XA ... 255, 294 MOV mem,XA ... 245, 267 MOV reg1,A ... 245, 268 MOV reg1,#n4 ... 245, 265 [P] POP BS ... 255, 293 MOV rp’1,XA ... 245, 268 POP rp ... 255, 293 MOV rp2,#n8 ... 245, 265 PUSH BS ... 255, 293 MOV XA,mem ... 245, 267 PUSH rp ... 255, 292 MOV XA,rp’ ... 245, 267 MOV XA,#n8 ...
µPD750008 USER'S MANUAL SKT pmem.@L ... 248, 283 SKT @H+mem.bit ... 248, 283 SKTCLR fmem.bit ... 248, 283 SKTCLR pmem.@L ... 248, 283 SKTCLR @H+mem.bit ... 248, 283 STOP ... 255, 295 SUBC A,@HL ... 246, 276 SUBC rp’1,XA ... 246, 276 SUBC XA,rp’ ... 246, 276 SUBS A,@HL ... 246, 275 SUBS rp’1,XA ... 246, 276 SUBS XA,rp’ ... 246, 275 [T] TBR addr ... 256, 288 TCALL !addr ... 256, 290 [X] XCH A,mem ... 245, 269 XCH A,reg1 ... 245, 269 XCH A,@HL ... 245, 268 XCH A,@HL+ ...
APPENDIX E HARDWARE INDEX E.1 HARDWARE INDEX (ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE NAME) [A] INT0 interrupt enable flag ... 187 Acknowledge detection flag ... 132 INT0 interrupt request flag ... 187 Acknowledge enable bit ... 132 INT1 edge detection mode register ... 193 Acknowledge trigger bit ... 132 INT1 interrupt enable flag ... 187 INT1 interrupt request flag ... 187 [B] INT2 edge detection mode register ... 213 Bank select register ... 65 INT2 interrupt enable flag ...
µPD750008 USER'S MANUAL [R] [W] Register bank enable flag ... 34, 64 Wake-up function specification bit ... 128 Register bank select register ... 34, 65 Watchdog timer enable flag ... 101 [S] Serial bus interface control register ... 131 Serial interface interrupt enable flag ... 187 Serial interface interrupt request flag ... 187 Serial interface operation enable/disable specification bit ... 128 Serial operation mode register ... 127 Shift register ... 134 Signal from address comparator ...
APPENDIX E HARDWARE INDEX E.2 HARDWARE INDEX (ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE SYMBOL) [A] IRQ1 ... 187 ACKD ... 132 IRQ2 ... 210 ACKE ... 132 IRQ4 ... 187 ACKT ... 132 IRQBT ... 187 IRQCSI ... 187 [B] IRQT0 ... 187 BS ... 65 IRQT1 ... 187 BSB0-BSB3 ... 181 IRQW ... 210 BSYE ... 132 IST0 ... 63, 194 BT ... 99 IST1 ... 63, 194 BTM ... 99 [K] [C] KR0-KR7 ... 211 CLOM ... 97 CMDD ... 132 [M] CMDT ... 133 MBE ... 21, 64 COI ... 128 MBS ... 21, 65 CSIE ... 128 CSIM ..
µPD750008 USER'S MANUAL [S] SBIC ... 131 SBS ... 46, 58 SCC ... 88 SIO ... 134 SK0, SK1, SK2 ... 63 SOS ... 93 SP ... 58 SVA ... 134 [T] T0 ... 109 T1 ... 110 TOE0 ... 114 TOE1 ... 114 TM0 ... 112 TM1 ... 113 TMOD0 ... 109 TMOD1 ... 110 [W] WDTM ... 101 WM ... 106 WUP ...
APPENDIX F REVISION HISTORY Major revisions in this edition are shown below. The revised chapters refer to this edition. Edition Second Major revisions from previous edition The 44-pin plastic QFP package was changed from µPD750008GB-xxx-3B4 to µPD750008GB-xxx-3BS-MTX. Revised chapters All The µPD75P0016 under development has been changed to the already-developed µPD75P0016. The input withstand voltage at ports 4 and 5 during open drain was changed from 12 V to 13 V.
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