User manual

µPD750008 USER'S MANUAL

3.2 GENERAL REGISTER BANK CONFIGURATION

The µPD750008 contains four register banks, each consisting of eight general registers: X, A, B, C, D,

E, H, and L. These registers are mapped to addresses 00H to 1FH in memory bank 0 of the data memory

(see Figure 3-5). To specify a general register bank, a register bank enable flag (RBE) and a register bank

select register (RBS) are contained. The RBS is a register used to select a register bank, and the RBE is

a flag used to determine whether a register bank selected using the RBS is to be enabled. The register bank

(RB) enabled at instruction execution is determined as

RB = RBE·RBS

Table 3-2. Register Bank to Be Selected with the RBE and RBS

Remark x: Don’t care

The contents of the RBE are automatically saved or restored at the beginning or end of subroutine

processing, so that the RBE can be freely modified during subroutine processing. In interrupt processing,

the RBE is automatically saved or restored, and when interrupt processing is started, the contents of the RBE

can be specified for the interrupt processing by setting the interrupt vector table. Therefore, as indicated in

Table 3-3, by selecting a register bank depending on whether the processing is normal or interrupt, the general

be saved and restored for the level-two interrupt processing, thus speeding up interrupt processing.

Table 3-3. Recommended Use of Register Banks with Normal Routines and Interrupt Routines

Normal processing Use register banks 2 and 3 with RBE = 1.

Level-one interrupt processing Use register bank 0 with RBE = 0.

Level-two interrupt processing Use register bank 1 with RBE = 1.

(In this case, the RBS needs to be saved and restored.)

Multiple (triple or more) interrupt processing Save and restore the registers with PUSH or POP.

Bank 0 is always selected.

RBE

RBS

3210

000xx

Bank 0 is selected.00

Bank 1 is selected.

100

Bank 2 is selected.10

Bank 3 is selected.11

Always 0