Intel® Xeon® Processor E5-2400 v2 Product Family Datasheet - Volume One January 2014 Reference Number:329819-002
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Table of Contents 1 Overview ................................................................................................................. 13 1.1 Introduction ..................................................................................................... 13 1.1.1 Processor Feature Details ........................................................................ 14 1.1.2 Supported Technologies .......................................................................... 14 1.2 Interfaces .............
2.5.4 2.5.5 2.5.6 2.5.7 2.5.3.1 Power-up Sequencing ................................................................ 68 2.5.3.2 Device Discovery ...................................................................... 69 2.5.3.3 Client Addressing ...................................................................... 69 2.5.3.4 C-states .................................................................................. 70 2.5.3.5 S-states ........................................................................
4.3 4.4 4.2.4.4 Core C6 State........................................................................... 91 4.2.4.5 Delayed Deep C-States.............................................................. 91 4.2.5 Package C-States ................................................................................... 91 4.2.5.1 Package C0 .............................................................................. 93 4.2.5.2 Package C1/C1E .......................................................................
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 Processor Signaling ......................................................................................... 124 7.1.1 System Memory Interface Signal Groups ................................................. 124 7.1.2 PCI Express* Signals ............................................................................ 124 7.1.3 DMI2/PCI Express* Signals.................................................................... 124 7.1.
9.5 9.6 9.7 9.8 10 Package Insertion Specifications........................................................................ 198 Processor Mass Specification ............................................................................. 199 Processor Materials.......................................................................................... 199 Processor Markings.......................................................................................... 199 Boxed Processor Specifications .............
2-29 2-30 2-31 2-32 2-33 2-34 2-35 2-36 2-37 2-38 2-39 2-40 2-41 2-42 2-43 2-44 2-45 2-46 2-47 2-48 2-49 2-50 4-1 4-2 4-3 5-1 5-2 5-3 5-4 5-5 5-6 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 9-1 9-2 9-3 9-4 10-1 10-2 10-3 10-4 Package Temperature Read Data ......................................................................... 52 Temperature Target Read................................................................................... 53 Thermal Status Word .........................................
10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 Boxed Processor Motherboard Keepout Zones (1 of 4) .......................................... 204 Boxed Processor Motherboard Keepout Zones (2 of 4) .......................................... 205 Boxed Processor Motherboard Keepout Zones (3 of 4) .......................................... 206 Boxed Processor Motherboard Keepout Zones (4 of 4) .......................................... 207 Boxed Processor Heat Sink Volumetric (1 of 2) ........................
5-2 5-3 5-4 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 8-1 8-2 9-1 9-2 9-3 10-1 10-2 10-3 10-4 Digital Thermal Sensor Specification Summary .................................................... 103 Embedded Case Temperature Thermal Specifications ........................................... 105 Embedded DTS Thermal Specifications ...............................................
Revision History Revision Number Description Revision Date 001 Initial Release January 2014 002 Added Protected Processor Inventory Number (PPIN) January 2014 Intel® Xeon® Processor E5-2400 v2 Product Family Datasheet Volume One 11
Intel® Xeon® Processor E5-2400 v2 Product Family Datasheet Volume One 12
Overview 1 Overview 1.1 Introduction Datasheet - Volume One provides DC specifications, land and signal definitions, and an overview of additional processor feature interfaces. This document is intended to be distributed as a part of a document set. The structure and scope of the volumes are provided in Table 1-2. Table 1-1.
Overview Table 1-2. Volume Structure and Scope (Sheet 2 of 2) • Boxed Processor Specifications Volume 2: Register Information • Configuration Process and Registers • Processor Integrated I/O (IIO) Configuration Registers • Processor Uncore Configuration Registers Figure 1-1. Processor Two-Socket Platform 1.1.
Overview • Intel® Virtualization Technology Processor Extensions • Intel® Trusted Execution Technology (Intel® TXT) • Intel® 64 Architecture • Intel® Streaming SIMD Extensions 4.1 (Intel® SSE4.1) • Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.
Overview — DRAM Single Device Data Correction (SDDC) for any single x4 or x8 DRAM device failure. Independent channel mode supports x4 SDDC. x8 SDDC requires lockstep mode — Lockstep mode where channels 2 & 3 are operated in lockstep mode — Data scrambling with address to ease detection of write errors to an incorrect address.
Overview portion of the fixed 4-KB block of memory-mapped space above that (starting at 100h) is known as extended configuration space. • PCI Express* Enhanced Access Mechanism. Accessing the device configuration space in a flat memory mapped fashion. • Automatic discovery, negotiation, and training of link out of reset. • Supports receiving and decoding 64 bits of address from PCI Express*.
Overview • Supports only x4 link width when in DMI2 mode • Operates at PCI Express* 1.0 or 2.0 speeds • Transparent to software • Processor and peer-to-peer writes and reads with 64-bit address support • APIC and Message Signaled Interrupt (MSI) support. Will send Intel-defined “End of Interrupt” broadcast message when initiated by the processor.
Overview Architecture registers and PCI configuration space (both within the processor package and downstream devices) • PECI address determined by SOCKET_ID configuration • Single domain (Domain 0) is supported 1.3 Power Management Support 1.3.
Overview • Running Average Power Limit (RAPL), Processor and DRAM Thermal and Power Optimization Capabilities 1.5 Package Summary The Processor socket type is noted as Socket B2. It is a 45 mm x 42.5 mm FCLGA12 package (LGA1356-2). 1.6 Terminology Term Description ASPM Active State Power Management BMC Baseboard Management Controllers Cbo Cache and Core Box. It is a term used for internal logic providing ring interface to LLC and Core.
Overview Term Description Intel® TXT Intel® Trusted Execution Technology Intel® Virtualization Technology (Intel® VT) Processor virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple, robust independent software environments inside a single platform. Intel® VT-d Intel® Virtualization Technology (Intel® VT) for Directed I/O.
Overview Term Description Rank A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC. These devices are usually, but not always, mounted on a single side of a DDR3 DIMM. SCI System Control Interrupt. Used in ACPI protocol. SSE Intel® Streaming SIMD Extensions (Intel® SSE) SKU A processor Stock Keeping Unit (SKU) to be installed in either server or workstation platforms.
Overview Table 1-3. Related Documents and Specifications (Sheet 2 of 2) Document Document Number/ Location PCI Express Base Specification - Revision 2.1 and 1.1 PCI Express Base Specification - Revision 3.0 http://www.pcisig.com System Management Bus (SMBus) Specification http://smbus.org/ DDR3 SDRAM Specification http://www.jedec.org Low (JESD22-A119) and High (JESD-A103) Temperature Storage Life Specifications http://www.jedec.
Interfaces 2 Interfaces This chapter describes the interfaces supported by the processor. For functional descriptions and additional details of these interfaces see Intel® Xeon® Processor E5 v2 Product Family Datasheet, Volume Two: Registers. 2.1 System Memory Interface 2.1.1 System Memory Technology Support The Integrated Memory Controller (IMC) supports DDR3 protocols with threeindependent 64-bit memory channels with 8 bits of ECC for each channel (total of 72-bits) and supports 2 DIMMs per channel.
Interfaces 2.2 PCI Express* Interface This section describes the PCI Express* 3.0 interface capabilities of the processor. See the PCI Express* Base Specification for details of PCI Express* 3.0. 2.2.1 PCI Express* Architecture Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged. The PCI Express* configuration uses standard mechanisms as defined in the PCI Plug-and-Play specification.
Interfaces Figure 2-2. Packet Flow through the Layers Framing Sequence Number Header Date ECRC LCRC Framing Transaction Layer Data Link Layer Physical Layer 2.2.1.1 Transaction Layer The upper layer of the PCI Express* architecture is the Transaction Layer. The Transaction Layer's primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as read and write, as well as certain types of events.
Interfaces 2.2.2 PCI Express* Configuration Mechanism The PCI Express* link is mapped through a PCI-to-PCI bridge structure. PCI Express* extends the configuration space to 4096 bytes per-device/function, as compared to 256 bytes allowed by the Conventional PCI Specification.
Interfaces 2.4 Intel® QuickPath Interconnect (Intel® QPI) The Intel® QuickPath Interconnect is a high speed, packetized, point-to-point interconnect used in the processor. The narrow high-speed links stitch together processors in distributed shared memory and integrated I/O platform architecture. It offers much higher bandwidth with low latency. The Intel® QuickPath Interconnect has an efficient architecture allowing more interconnect performance to be achieved in real systems.
2.5 Platform Environment Control Interface (PECI) The Platform Environment Control Interface (PECI) uses a single wire for self-clocking and data transfer. The bus requires no additional control lines. The physical layer is a self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle level near zero volts. The duration of the signal driven high depends on whether the bit value is a logic ‘0’ or logic ‘1’.
• Processor and DRAM thermal management • Platform manageability functions including thermal, power, and error monitoring — The platform ‘power’ management includes monitoring and control for both the processor and DRAM subsystem to assist with data center power limiting. 2.5.1.1 Thermal Management Processor fan speed control is managed by comparing Digital Thermal Sensor (DTS) thermal readings acquired via PECI against the processor-specific fan speed control reference point, or TCONTROL.
Figure 2-3. Ping() Byte # Byte Definition 0 1 2 3 Client Address Write Length 0x00 Read Length 0x00 FCS An example Ping() command to PECI device address 0x30 is shown below. Figure 2-4. Ping() Example Byte # Byte Definition 2.5.2.2 0 1 2 3 0x30 0x00 0x00 0xe1 GetDIB() The processor PECI client implementation of GetDIB() includes an 8-byte response and provides information regarding client revision number and the number of supported domains.
2.5.2.2.2 Device Info The Device Info byte gives details regarding the PECI client configuration. At a minimum, all clients supporting GetDIB will return the number of domains inside the package via this field. With any client, at least one domain (Domain 0) must exist. Therefore, the Number of Domains reported is defined as the number of domains in addition to Domain 0. For example, if bit 2 of the Device Info byte returns a ‘1’, that would indicate that the PECI client supports two domains. Figure 2-6.
Table 2-2. Minor Revision Number Meaning Minor Revision Supported Command Suite 5 Ping(), GetDIB(), GetTemp(), WrPkgConfig(), RdPkgConfig(), RdIAMSR(), RdPCIConfigLocal(), WrPCIConfigLocal(), RdPCIConfig(), WrPCIConfig() 6 Ping(), GetDIB(), GetTemp(), WrPkgConfig(), RdPkgConfig(), RdIAMSR(), RdPCIConfigLocal(), WrPCIConfigLocal(), RdPCIConfig(), WrPCIConfig(), WrIAMSR() For the processor PECI client that is designed to meet the RS - Platform Environment Control Interface (PECI) Specification, Rev 3.
Example bus transaction for a thermal sensor device located at address 0x30 returning a value of negative 10 counts is show in Figure 2-9. Figure 2-9. GetTemp() Example Byte # Byte Definition 2.5.2.3.2 0 1 2 3 0x30 0x01 0x02 0x01 4 5 6 7 0xef 0x80 0xfd 0x4b Supported Responses The typical client response is a passing FCS and valid thermal data. Under some conditions, the client’s response will indicate a failure. GetTemp() response definitions are listed in Table 2-3. Refer to Section 2.
regarding completion codes. Figure 2-10. RdPkgConfig() Note: The 2-byte parameter field and 4-byte read data field defined in Figure 2-10 are sent in standard PECI ordering with LSB first and MSB last. 2.5.2.4.2 Supported Responses The typical client response is a passing FCS, a passing Completion Code and valid data. Under some conditions, the client’s response will indicate a failure. Table 2-4. RdPkgConfig() Response Definition Response Bad Write FCS 2.5.2.
2.5.2.5.1 Command Format The WrPkgConfig() format is as follows: Write Length: 0x0a(dword) Read Length: 0x01 Command: 0xa5 AW FCS Support: Yes Description: Writes data to the processor PCS entry as specified by the ‘index’ and ‘parameter’ fields. This command supports only dword data writes on the processor PECI clients. All command responses include a completion code that provides additional pass/fail status information. Refer to Section 2.5.5.2 for details regarding completion codes.
2.5.2.5.2 Supported Responses The typical client response is a passing FCS, a passing Completion Code and valid data. Under some conditions, the client’s response will indicate a failure. Table 2-5. WrPkgConfig() Response Definition Response Bad Write FCS 2.5.2.6 Meaning Electrical error or AW FCS failure Abort FCS Illegal command formatting (mismatched RL/WL/Command Code) CC: 0x40 Command passed, data is valid. CC: 0x80 Response timeout.
Table 2-6.
Table 2-6.
2.5.2.6.3 DRAM Rank Temperature Write This feature allows the PECI host to program into the processor, the temperature for all the ranks within a DIMM up to a maximum of four ranks as shown in Figure 2-13. The DIMM index and Channel index are specified through the parameter field as shown in Table 2-7.
Figure 2-14. DIMM Temperature Read / Write 31 24 23 Reserved 16 Reserved 15 8 7 0 DIMM# 0 Absolute Temp (In Degrees C) DIMM# 1 Absolute Temp (In Degrees C) DIMM Temperature Data 15 3 2 Reserved 0 Channel Index Parameter Format 2.5.2.6.5 DIMM Ambient Temperature Write / Read This feature allows the PECI host to provide an ambient temperature reference to be used by the processor for activity-based DRAM temperature estimation.
Figure 2-16. DRAM Channel Temperature 31 24 Channel 3 Maximum Temperature (in Degrees C) 23 16 Channel 2 Maximum Temperature (in Degrees C) 15 8 7 Channel 1 Maximum Temperature (in Degrees C) 1 RESERVED Channel Temperature Data 2.5.2.6.7 Accumulated DRAM Energy Read This feature allows the PECI host to read the DRAM energy consumed by all the DIMMs within all the channels or all the DIMMs within just a specified channel. The parameter field is used to specify the channel index.
The minimum DRAM power in Figure 2-18 corresponds to a minimum bandwidth setting of the memory interface. It does ‘not’ correspond to a processor IDLE or memory self-refresh state. The ‘time window’ in Figure 2-18 is representative of the rate at which the power control unit (PCU) samples the DRAM energy consumption information and reactively takes the necessary measures to meet the imposed power limits.
in the same command cycle. All RAPL parameter values including the power limit value, control time window, and enable bit will have to be specified correctly even if the intent is to change just one parameter value when programming over PECI. The following conversion formula should be used for encoding or programming the ‘Control Time Window’ in bits [23:17]. Control Time Window (in seconds) = ([1 + 0.
Figure 2-20. DRAM Power Limit Performance Data 0 31 Accumulated DRAM Throttle Time DRAM Power Limit Performance 2.5.2.6.11 CPU Thermal and Power Optimization Capabilities Table 2-8 provides a summary of the processor power and thermal optimization capabilities that can be accessed over PECI. Note: The Index values referenced in Table 2-8 are in decimal format.
Table 2-8. Service RdPkgConfig() & WrPkgConfig() CPU Thermal and Power Optimization Services Summary (Sheet 2 of 4) Index Value (decimal) Parameter RdPkgConfig() WrPkgConfig Value Data () (word) (dword) Data (dword) Description Alternate Inband MSR or CSR Access Package Power SKU Read 28 0x0000 Package Power SKU[31:0] N/A Returns Thermal Design Power and minimum package power values for the processor SKU.
Table 2-8. Service RdPkgConfig() & WrPkgConfig() CPU Thermal and Power Optimization Services Summary (Sheet 3 of 4) Index Value (decimal) Parameter RdPkgConfig() WrPkgConfig Value Data () (word) (dword) Data (dword) Description Alternate Inband MSR or CSR Access Thermally Constrained Time Read 32 0x0000 Thermally Constrained Time N/A Read the time for which the processor has been operating in a lowered power state due to internal TCC activation.
Table 2-8.
type and processor stepping. Refer to the processor BIOS Writer’s Guide for more information. Figure 2-22. Platform ID Data 31 3 2 0 Processor Flag Reserved Platform ID Data • PCU Device ID: This information can be used to uniquely identify the processor power control unit (PCU) device when combined with the Vendor Identification register content and remains constant across all SKUs. Refer to the appropriate register description for the exact processor PCU Device ID value. Figure 2-23.
package asserted IERR and bit 31 is set if the package asserted CAT_ERR_N. The CAT_ERR_N may be used to signal the occurrence of a MCERR or IERR. Figure 2-26. Machine Check Status 31 30 CATERR IERR 29 28 0 MCERR Reserved MCA Error Source Log 2.5.2.6.13 Package Power SKU Unit Read This feature enables the PECI host to read the units of time, energy and power used in the processor and DRAM power control registers for calculating power and timing parameters.
The minimum package power in bits [30:16] is applicable to both the ‘Power Limit1’ & ‘Power Limit2’ fields and corresponds to a mode when all the cores are operational and in their lowest frequency mode. Attempts to program the power limit below the minimum power value may not be effective since BIOS/OS, and not the PCU, controls disabling of cores and core activity.
2.5.2.6.17 Package Temperature Read This read returns the maximum processor die temperature in 16-bit PECI format. The upper 16 bits of the response data are reserved. The PECI temperature data returned by this read is an exponential moving average of the maximum sensor temperature (max(core and uncore sensors)), updated once every ms.
Figure 2-30. Temperature Target Read 2.5.2.6.20 Package Thermal Status Read / Clear The Thermal Status Read provides information on package level thermal status. Data includes: • Thermal Control Circuit (TCC) activation • Bidirectional PROCHOT_N signal assertion • Critical Temperature Both status and sticky log bits are managed in this status word. All sticky log bits are set upon a rising edge of the associated status bit and the log bits are cleared only by Thermal Status reads or a processor reset.
Figure 2-32. Thermal Averaging Constant Write / Read 31 4 3 0 PECI Temperature Averaging Constant RESERVED Thermal Averaging Constant 2.5.2.6.22 Thermally Constrained Time Read This features allows the PECI host to access the total time for which the processor has been operating in a lowered power state due to TCC activation. The returned data includes the time required to ramp back up to the original P-state target after TCC activation expires.
When determining energy changes by subtracting energy values between successive reads, Intel advocates using the 2’s complement method to account for counter wraparounds. Alternatively, adding all ‘F’s (‘0xFFFFFFFF’) to a negative result from the subtraction will accomplish the same goal. Figure 2-34. Accumulated Energy Read Data 0 31 Accumulated CPU Energy Accumulated Energy Status 2.5.2.6.
Figure 2-35. Power Limit Data for VCC Power Plane 31 24 RESERVED 23 17 Control Time Window 16 Clamp Mode 15 14 Power Limit Enable 0 VCC Plane Power Limit VCC Power Plane Power Limit Data 2.5.2.6.26 Package Power Limits For Multiple Turbo Modes This feature allows the PECI host to program two power limit values to support multiple turbo modes. The operating systems and drivers can balance the power budget using these two limits.
Figure 2-36. Package Turbo Power Limit Data 63 56 55 49 Control Time Window #2 RESERVED 48 Clamp Mode #2 47 46 Power Limit Enable #2 32 Power Limit # 2 Package Power Limit 2 31 24 RESERVED 23 17 Control Time Window #1 16 Clamp Mode #1 15 14 Power Limit Enable #1 0 Power Limit # 1 Package Power Limit 1 2.5.2.6.27 Package Power Limit Performance Status Read This service allows the PECI host to assess the performance impact of the currently active power limiting modes.
2.5.2.6.29 ACPI P-T Notify Write & Read This feature enables the processor turbo capability when used in conjunction with the PECI package RAPL or power limit. When the BMC sets the package power limit to a value below TDP, it also determines a new corresponding turbo frequency and notifies the OS using the ‘ACPI Notify’ mechanism as supported by the _PPC or performance present capabilities object.
Bit[11] is the Read Mode bit and should be set to ‘0’ for TOR reads. The Read Mode bit can alternatively be set to ‘1’ to read the ‘Core ID’ (with associated valid bit as shown in Figure 2-40) that points to the first core that asserted the IERR. In this case bits [10:0] of the parameter field are ignored. The ‘Core ID’ read may not return valid data until at least 1 mS after the IERR assertion. Figure 2-40. Caching Agent TOR Read Data Note: 2.5.2.6.
Description: Returns the data maintained in the processor IA MSR space as specified by the ‘Processor ID’ and ‘MSR Address’ fields. The Read Length dictates the desired data return size. This command supports only qword responses. All command responses are prepended with a completion code that contains additional pass/fail status information. Refer to Section 2.5.5.2 for details regarding completion codes. 2.5.2.7.
Figure 2-43. RdIAMSR() Note: 2.5.2.7.3 The 2-byte MSR Address field and read data field defined in Figure 2-43 are sent in standard PECI ordering with LSB first and MSB last. Supported Responses The typical client response is a passing FCS, a passing Completion Code and valid data. Under some conditions, the client’s response will indicate a failure. Table 2-10. RdIAMSR() Response Definition Response Bad FCS 2.5.2.7.
cores supported by a particular processor SKU. Any attempt to read processor MSRs that are not accessible over PECI or simply not implemented will result in a completion code of 0x90. PECI access to these registers is expected only when in-band access mechanisms are not available. Table 2-11.
Notes: 1. The MCi_ADDR and MCi_MISC registers for machine check banks 2 & 4 are not implemented on the processors. The MCi_CTL register for machine check bank 2 is also not implemented. 2. The PECI host must determine the total number of machine check banks and the validity of the MCi_ADDR and MCi_MISC register contents prior to issuing a read to the machine check bank similar to standard machine check architecture enumeration and accesses. 3.
processor PECI clients. All command responses are prepended with a completion code that includes additional pass/fail status information. Refer to Section 2.5.5.2 for details regarding completion codes. Figure 2-45. RdPCIConfig() Note: 2.5.2.8.2 The 4-byte PCI configuration address and read data field defined in Figure 2-45 are sent in standard PECI ordering with LSB first and MSB last. Supported Responses The typical client response is a passing FCS, a passing Completion Code and valid data.
PECI originators may conduct a device/function enumeration sweep of this space by issuing reads in the same manner that the BIOS would. A response of all 1’s may indicate that the device/function/register is unimplemented even with a ‘passing’ completion code. Alternatively, reads to unimplemented or hidden registers may return a completion code of 0x90 indicating an invalid request.
Note: 2.5.2.9.2 The 3-byte PCI configuration address and read data field defined in Figure 2-47 are sent in standard PECI ordering with LSB first and MSB last. Supported Responses The typical client response is a passing FCS, a passing Completion Code and valid data. Under some conditions, the client’s response will indicate a failure. The PECI client response can also vary depending on the address and data.
Read Length: 0x01 Command: 0xe5 AW FCS Support: Yes Description: Writes the data sent to the requested register address. Write Length dictates the desired write granularity. The command always returns a completion code indicating pass/fail status. Refer to Section 2.5.5.2 for details on completion codes. Figure 2-48. WrPCIConfigLocal() 0 1 2 3 Client Address Write Length {0x07, 0x08, 0x0a} Read Length 0x01 Cmd Code 0xe5 Byte # Byte Definition 4 Host ID[7:1] & Retry[0] 8 LSB Note: 2.5.2.10.
Table 2-14. WrPCIConfigLocal() Response Definition Response 2.5.2.10.3 Meaning CC: 0x82 The processor hardware resources required to service this command are in a low power state. Retry may be appropriate after modification of PECI wake mode behavior if appropriate. CC: 0x90 Unknown/Invalid/Illegal Request CC: 0x91 PECI control hardware, firmware or associated logic error. The processor is unable to process the request.
Table 2-16.
to a different PECI addresses. Strapping the SOCKET_ID[1:0] pins results in the client addresses shown in Table 2-17. These package strap(s) are evaluated at the assertion of PWRGOOD (as depicted in Figure 2-49). Refer to the Romley Platform Design Guide for recommended resistor values for establishing non-default SOCKET_ID settings. The client address may not be changed after PWRGOOD assertion, until the next power cycle on the processor.
Table 2-18. Power Impact of PECI Commands vs. C-states (Sheet 2 of 2) Command RdPCIConfig() 2.5.3.5 Power Impact May require package ‘pop-up’ to C2 state S-states The processor PECI client is always guaranteed to be operational in the S0 sleep state. • The Ping(), GetDIB(), GetTemp(), RdPkgConfig(), WrPkgConfig(), RdPCIConfigLocal() and WrPCIConfigLocal() will be fully operational in S0 and S1. Responses in S3 or deeper states are dependent on POWERGOOD assertion status.
2.5.3.7.1 BMC INIT Mode The BMC INIT boot mode is used to provide a quick and efficient means to transfer responsibility for uncore configuration to a service processor like the BMC. In this mode, the socket performs a minimal amount of internal configuration and then waits for the BMC or service processor to complete the initialization. 2.5.3.7.2 Link Init Mode In cases where the Firmware Agent socket cannot be resolved, the socket is placed in Link Init mode.
The processor PECI client will not clear the semaphore that was acquired to service the request until the originator sends the ‘retry’ request in a timely fashion to successfully retrieve the response data. In the absence of any automatic timeouts, this could tie up shared resources and result in artificial bandwidth conflicts. 2.5.3.10 Enumerating PECI Client Capabilities The PECI host originator should be designed to support all optional but desirable features from all processors of interest.
Table 2-20. Multi-Domain Command Code Reference (Sheet 2 of 2) Command Name Domain 0 Code Domain 1 Code WrPCIConfigLocal() 0xe5 0xe6 2.5.5 Client Responses 2.5.5.1 Abort FCS The Client responds with an Abort FCS (refer to RS - Platform Environment Control Interface (PECI) Specification, Rev 3.0 for details) under the following conditions: • The decoded command is not understood or not supported on this processor (this includes good command codes with bad Read Length or Write Length bytes).
Note: The codes explicitly defined in Table 2-22 may be useful in PECI originator response algorithms. Reserved or undefined codes may also be generated by a PECI client device, and the originating agent must be capable of tolerating any code. The Pass/Fail mask defined in Table 2-21 applies to all codes, and general response policies may be based on this information. Refer to Section 2.5.6 for originator response policies and recommendations. 2.5.
2.5.7.2 Interpretation The resolution of the processor’s Digital Thermal Sensor (DTS) is approximately 1°C, which can be confirmed by a RDMSR from the IA32_THERM_STATUS MSR where it is architecturally defined. The MSR read will return only bits [13:6] of the PECI temperature sensor data defined in Figure 2-50. PECI temperatures are sent through a configurable low-pass filter prior to delivery in the GetTemp() response data.
Technologies 3 Technologies 3.1 Intel® Virtualization Technology (Intel® VT) Intel® Virtualization Technology (Intel® VT) makes a single system appear as multiple independent systems to software. This allows multiple, independent operating systems to run simultaneously on a single system. Intel VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets.
Technologies 3.1.2 Intel® VT-x Features The processor core supports the following Intel VT-x features: • Extended Page Tables (EPT) — hardware assisted page table virtualization — eliminates VM exits from guest OS to the VMM for shadow page-table maintenance • Virtual Processor IDs (VPID) — Ability to assign a VM ID to tag processor core hardware structures (e.g., TLBs) — This avoids flushes on VM transitions to give a lower-cost VM transition time and an overall reduction in virtualization overhead.
Technologies partitions in the same operating system, or there can be multiple operating system instances running on the same system – offering benefits such as system consolidation, legacy migration, activity partitioning or security. 3.1.3.
Technologies The Intel TXT platform helps to provide the authenticity of the controlling environment such that those wishing to rely on the platform can make an appropriate trust decision. The Intel TXT platform determines the identity of the controlling environment by accurately measuring and verifying the controlling software. Another aspect of the trust decision is the ability of the platform to resist attempts to change the controlling environment.
Technologies The architecture consists of six instructions that offer full hardware support for AES. Four instructions support the AES encryption and decryption, and the other two instructions support the AES key expansion. Together, they offer a significant increase in performance compared to pure software implementations. The AES instructions have the flexibility to support all three standard AES key lengths, all standard modes of operation, and even some nonstandard or future variants.
Technologies Processor E5 v2 Product Family Datasheet, Volume Two: Registers details. for enabling For more information on Intel Hyper-Threading Technology, see http://www.intel.com/products/ht/hyperthreading_more.htm. 3.6 Intel® Turbo Boost Technology Intel Turbo Boost Technology is a feature that allows the processor to opportunistically and automatically run faster than its rated operating frequency if it is operating below power, temperature, and current limits.
Technologies • Clock Partitioning and Recovery. The bus clock continues running during state transition, even when the core clock and Phase-Locked Loop are stopped, which allows logic to remain active. The core clock is also able to restart more quickly under Enhanced Intel SpeedStep Technology. For additional information on Enhanced Intel SpeedStep Technology see Section 4.2.1. 3.
Technologies — Application domain can scale out with advanced platform interconnect fabrics, such as Intel QPI. • Power Efficiency - Intel AVX is extremely power efficient. Incremental power is insignificant when the instructions are unused or scarcely used. Combined with the high performance that it can deliver, applications that lend themselves heavily to using Intel AVX can be much more energy efficient and realize a higher performance-per-watt.
Power Management 4 Power Management This chapter provides information on the following power management topics: • ACPI States • System States • Processor Core/Package States • Integrated Memory Controller (IMC) and System Memory States • Direct Media Interface Gen 2 (DMI2)/PCI Express* Link States • Intel QuickPath Interconnect States 4.1 ACPI States Supported The ACPI states supported by the processor are described in this section. 4.1.1 System States Table 4-1. System States State 4.1.
Power Management Table 4-2.
Power Management Table 4-4. System Memory Power States (Sheet 2 of 2) State Self-Refresh Description CKE de-asserted. In this mode, no transactions are executed and the system memory consumes the minimum possible power. Self refresh modes apply to all memory channels for the processor. • IO-MDLL Off: Option that sets the IO master DLL off when self refresh occurs. • PLL Off: Option that sets the PLL off when self refresh occurs.
Power Management 4.2 Processor Core/Package Power Management While executing code, Enhanced Intel SpeedStep® Technology optimizes the processor’s frequency and core voltage based on workload. Each frequency and voltage operating point is defined by ACPI as a P-state. When the processor is not executing code, it is idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power C-states have longer entry and exit latencies. 4.2.
Power Management Figure 4-1. Idle Power Management Breakdown of the Processor Cores T h re a d 0 T h re a d 1 C o r e 0 S ta te T h re a d 0 T h re a d 1 C o r e N S ta te P r o c e s s o r P a c k a g e S ta te Figure 4-2. Thread and Core C-State Entry and Exit While individual threads can request low power C-states, power saving actions only take place once the core C-state is resolved. Core C-states are automatically resolved by the processor.
Power Management For legacy operating systems, P_LVLx I/O reads are converted within the processor to the equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result in I/O reads to the system. The feature, known as I/O MWAIT redirection, must be enabled in the BIOS. To enable it, refer to the Intel® Xeon® Processor E5 v2 Product Family Datasheet, Volume Two: Registers . Note: The P_LVLx I/O Monitor address needs to be set up before using the P_LVLx I/O read interface.
Power Management While a core is in C1/C1E state, it processes bus snoops and snoops from other threads. For more information on C1E, see Section 4.2.5.2, “Package C1/C1E”. To operate within specification, BIOS must enable the C1E feature for all installed processors. 4.2.4.3 Core C3 State Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C3) instruction.
Power Management The processor exits a package C-state when a break event is detected. Depending on the type of break event, the processor does the following: • If a core break event is received, the target core is activated and the break event message is forwarded to the target core. — If the break event is not masked, the target core enters the core C0 state and the processor enters package C0. — If the break event is masked, the processor attempts to re-enter its previous package state.
Power Management Figure 4-3. Package C-State Entry and Exit C1 C0 C2 C3 4.2.5.1 C6 Package C0 The normal operating state for the processor. The processor remains in the normal state when at least one of its cores is in the C0 or C1 state or when the platform has not granted permission to the processor to go into a low power state. Individual cores may be in lower power idle states while the package is in C0. 4.2.5.
Power Management 4.2.5.3 Package C2 State Package C2 state is an intermediate state which represents the point at which the system level coordination is in progress. The package cannot reach this state unless all cores are in at least C3.
Power Management 4.2.6 Package C-State Power Specifications The table below lists the processor package C-state power specifications for various processor SKUs. Table 4-10.
Power Management 4.3 System Memory Power Management The DDR3 power states can be summarized as the following: • Normal operation (highest power consumption). • CKE Power-Down: Opportunistic, per rank control after idle time. There may be different levels. — Active Power-Down. — Precharge Power-Down with Fast Exit. — Precharge power Down with Slow Exit. • Self Refresh: In this mode no transaction is executed. The DDR consumes the minimum possible power. 4.3.
Power Management 4.3.2.1 Self Refresh Entry Self refresh entrance can be either disabled or triggered by an idle counter. Idle counter always clears with any access to the memory controller and remains clear as long as the memory controller is not drained. As soon as the memory controller is drained, the counter starts counting, and when it reaches the idle-count, the memory controller will place the DRAMs in self refresh state. Power may be removed from the memory controller core at this point.
Thermal Management Specifications 5 Thermal Management Specifications 5.1 Package Thermal Specifications The processor requires a thermal solution to maintain temperatures within operating limits. Any attempt to operate the processor outside these limits may result in permanent damage to the processor and potentially other components within the system, see section Section 7.7.1, “Storage Condition Specifications”. Maintaining the proper thermal environment is key to reliable, long-term system operation.
Thermal Management Specifications The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit (TCC) activation, as indicated by PROCHOT_N (see Section 7, “Electrical Specifications”). Systems that implement fan speed control must be designed to use this data. Systems that do not alter the fan speed need to guarantee the case temperature meets the thermal profile specifications.
Thermal Management Specifications 5.1.2 TCASE and DTS Based Thermal Specifications To simplify compliance to thermal specifications at processor run time, the processor has added a Digital Thermal Sensor (DTS) based thermal specification. Digital Thermal Sensor reports a relative die temperature as an offset from TCC activation temperature. TCASE thermal based specifications are used for heat sink sizing and DTS based specs are used for acoustic and fan speed optimizations.
5.1.3 Processor Operational Thermal Specifications Each SKU has a unique thermal profile that ensures reliable operation for the intended form factor over the processor’s service life. These specifications are based on final silicon characterization. 5.1.3.1 Minimum operating case temperature Minimum case operating temperature is specified at 5°C for every Intel® Xeon® processor E5-2400 v2 product family processor SKU. 5.1.3.
Table 5-1. Case Temperature Thermal Specifications TDP (W) Core Count TLA (°C) PSICA (°C/W) Minimum TCASE (°C) Maximum TCASE (°C) 60 6 51.0 0.301 5.0 69.0 Figure 5-1. Case Temperature Thermal Profile 5.1.3.3 Digital Thermal Sensor (DTS) thermal profiles Each DTS thermal profile is unique to each TDP and core count combination.
5.1.3.4 Processor Digital Thermal Sensor (DTS) Specifications Table 5-2. Digital Thermal Sensor Specification Summary Figure 5-2. TDP (W) Core Count 95 10 52.6 0.398 90.4 95 8 52.6 0.431 93.5 80 6 51.7 0.473 89.6 80 4 51.7 0.542 95.1 80 (1S) 4 50.5 0.505 90.9 80 (1S) 2 50.5 0.624 100.4 60 10 51.0 0.381 73.9 60 6 51.0 0.456 78.
5.1.4 Embedded Server Thermal Profiles Network Equipment Building System (NEBS) is the most common set of environmental design guidelines applied to telecommunications equipment in the United States. Embedded server SKU’s target operation at higher case temperatures and/or NEBS thermal profiles for embedded communications server and storage form factors. The term “Embedded” is used to refer to those segments collectively. Thermal profiles in this section pertain only to those specific Embedded SKU’s.
Table 5-3 provides the PSICA and TLA parameters that define TCASE thermal profile for each TDP/Core count combination. Figure 5-3 illustrates the general form of the resulting linear graph resulting from TCASE = PSICA * P + TLA. Table 5-3. Embedded Case Temperature Thermal Specifications Core Count TLA (°C) TLA-ST (°C) PSICA (°C/W) Minimum TCASE (°C) Nominal Maximum TCASE (°C) Short-Term Maximum TCASE (°C) 10 50.0 65.0 0.383 5.0 76.8 91.8 LV60W-8C 8 52.0 67.0 0.369 5.0 74.1 89.
TLA is the Local Ambient temperature for the Nominal thermal profile. TLA-ST designates the Local Ambient temperature for Short-Term operation. P is the processor power dissipation. Table 5-4 provides the PSIPA and TLA parameters that define TDTS thermal profile for each TDP/Core count combination. Figure 5-4 illustrates the general form of the resulting linear graph resulting from TDTS = PSIPA * P + TLA. The slope of a DTS profile assumes full fan speed which is not required over much of the power range.
Figure 5-4. Embedded DTS Thermal Profile 5.1.5 Thermal Metrology The minimum and maximum case temperatures (TCASE) are measured at the geometric top center of the processor integrated heat spreader (IHS). Figure 5-5 illustrates the location where TCASE temperature measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the Intel® Xeon® Processor E5-2400 v2 Product Family Thermal/Mechanical Design Guide (TMDG).
Figure 5-5. Case Temperature (TCASE) Measurement Location Notes: 1. Figure is not to scale and is for reference. 2. B1: Max = 45.07 mm, Min = 44.93 mm 3. B2: Max = 42.57 mm, Min = 42.43 mm 4. C1: Max = 39.1 mm, Min = 38.9 mm 5. C2: Max = 36.6 mm, Min = 36.4 mm 6. C3: Max = 2.3 mm, Min = 2.2 mm 7. C4: Max = 2.3 mm, Min = 2.
5.2 Processor Core Thermal Features 5.2.1 Processor Temperature A new feature in the processor is a software readable field in the TEMPERATURE_TARGET MSR register that contains the minimum temperature at which the TCC will be activated and PROCHOT_N will be asserted. The TCC activation temperature is calibrated on a part-by-part basis and normal factory variation may result in the actual TCC activation temperature being higher than the value listed in the register.
5.2.2.1 Frequency/SVID Control The processor uses Frequency/SVID control whereby TCC activation causes the processor to adjust its operating frequency (via the core ratio multiplier) and VCC input voltage (via the SVID signals). This combination of reduced frequency and voltage results in a reduction to the processor power consumption. This method includes multiple operating points, each consisting of a specific operating frequency and voltage.
Figure 5-6. Frequency and Voltage Ordering 5.2.2.2 Clock Modulation Clock modulation is performed by alternately turning the clocks off and on at a duty cycle specific to the processor (factory configured to 37.5% on and 62.5% off for TM1). The period of the duty cycle is configured to 32 microseconds when the TCC is active. Cycle times are independent of processor frequency.
increments. On-Demand mode may be used in conjunction with the Adaptive Thermal Monitor; however, if the system tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the On-Demand mode. 5.2.4 PROCHOT_N Signal An external signal, PROCHOT_N (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature.
5.2.6 Integrated Memory Controller (IMC) Thermal Features 5.2.6.1 DRAM Throttling Options The Integrated Memory Controller (IMC) has two, independent mechanisms that cause system memory throttling: • Open Loop Thermal Throttling (OLTT) and Hybrid OLTT (OLTT_Hybrid) • Closed Loop Thermal Throttling (CLTT) and Hybrid CLTT (CLTT_Hybrid) Please refer to Intel® Xeon® Processor E5 v2 Product Family Datasheet, Volume Two: Registers, section 8.11 for further details 5.2.6.1.
• Output Function: The output behavior of the MEM_HOT_{C1/C23}_N signals supports Level mode. In this mode, MEM_HOT_{C1/C23}_N event temperatures are programmable via TEMP_OEM_HI, TEMP_LOW, TEMP_MID, and TEMP_HI threshold settings in the iMC. In Level mode, when asserted, the signal indicates to the platform that a BIOS-configured thermal threshold has been reached by one or more DIMMs in the covered channel pair. 5.2.6.
Signal Descriptions 6 Signal Descriptions This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. 6.1 System Memory Interface Signals Table 6-1. Memory Channel DDR1, DDR2, DDR3 Signal Name DDR{1/2/3}_BA[2:0] Description Bank Address. Defines the bank which is the destination for the current Activate, Read, Write, or Precharge command. DDR{1/2/3}_CAS_N Column Address Strobe. DDR{1/2/3}_CKE[3:0] Clock Enable.
Signal Descriptions Table 6-2. Memory Channel Miscellaneous Signal Name Description DDR_RESET_C1_N DDR_RESET_C23_N System memory reset: Reset signal from processor to DRAM devices on the DIMMs. DDR_RESET_C1_N is used for memory channel 1 while DDR_RESET_C23_N is used for memory channels 2 and 3. DDR_SCL_C1 DDR_SCL_C23 SMBus clock for the dedicated interface to the serial presence detect (SPD) and thermal sensors (TSoD) on the DIMMs.
Signal Descriptions Table 6-4. PCI Express* Port 3 Signals (Sheet 2 of 2) Signal Name Table 6-5.
Signal Descriptions 6.4 Intel® QuickPath Interconnect Signals Table 6-7. Intel QPI Port Signals Signal Name Table 6-8. Description QPI_CLKRX_DN/DP Reference Clock Differential Input. These pins provide the PLL reference clock differential input. The Intel QPI forward clock frequency is half the Intel QPI data rate. QPI_CLKTX_DN/DP Reference Clock Differential Output. These pins provide the PLL reference clock differential input.
Signal Descriptions 6.7 JTAG and TAP Signals Table 6-11. JTAG and TAP Signals Signal Name BPM_N[7:0] Breakpoint and Performance Monitor Signals: I/O signals from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. These are 100 MHz signals. EAR_N External Alignment of Reset, used to bring the processor up into a deterministic state. This signal is pulled up on the die, refer to Table 7-6 for details.
Signal Descriptions Table 6-13. Processor Asynchronous Sideband Signals (Sheet 2 of 4) Signal Name Description BMCINIT BMC Initialization Strap. Indicates whether Service Processor Boot Mode should be used. Used in combination with FRMAGENT and SOCKET_ID inputs. • 0: Service Processor Boot Mode Disabled.
Signal Descriptions Table 6-13. Processor Asynchronous Sideband Signals (Sheet 3 of 4) Signal Name Description PROCHOT_N PROCHOT_N will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit has been activated, if enabled. This signal can also be driven to the processor to activate the Thermal Control Circuit. This signal is sampled after PWRGOOD assertion.
Signal Descriptions Table 6-13. Processor Asynchronous Sideband Signals (Sheet 4 of 4) Signal Name Description THERMTRIP_N Assertion of THERMTRIP_N (Thermal Trip) indicates one of two possible critical over-temperature conditions: One, the processor junction temperature has reached a level beyond which permanent silicon damage may occur and Two, the system memory interface has exceeded a critical temperature limit set by BIOS.
Signal Descriptions 6.10 Processor Power and Ground Supplies Table 6-15. Power and Ground Signals Signal Name VCC Description Variable power supply for the processor cores, lowest level caches (LLC), ring interface, and home agent. It is provided by a VRM/EVRD 12.0 compliant regulator for each CPU socket. The output voltage of this supply is selected by the processor, using the serial voltage ID (SVID) bus. Note: VCC has a Vboot setting of 0.0V and is not included in the PWRGOOD indication.
Electrical Specifications 7 Electrical Specifications 7.1 Processor Signaling The processor includes 1356 lands, which utilize various signaling technologies. Signals are grouped by electrical characteristics and buffer type into various signal groups.
Electrical Specifications 7.1.5 Platform Environmental Control Interface (PECI) PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external system management logic and thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature.
Electrical Specifications The processor core frequency is configured during reset by using values stored within the device during manufacturing. The stored value sets the lowest core multiplier at which the particular processor can operate. If higher speeds are desired, the appropriate ratio can be configured via the IA32_PERF_CTL MSR (MSR 199h); Bits [15:0].
Electrical Specifications For clean on-chip power distribution, processors include lands for all required voltage supplies. These are listed in Table 7-1. Table 7-1. Power and Ground Lands Power and Ground Lands VCC VCCPLL VCCD 7.1.9.2 Number of Lands 135 2 16 Comments Each VCC land must be supplied with the voltage determined by the SVID Bus signals. Table 7-3 Defines the voltage level associated with each core SVID pattern.Table 7-12, Figure 7-2represent VCC static and transient limits.
Electrical Specifications processor to set the maximum supported VID code and if the programmed VID code is higher than the VID supported by the VR, then VR will respond with a “not supported” acknowledgement. See the VR12/IMVP7 Pulse Width Modulation Specification for further details. 7.1.9.3.1 SVID Commands The processor provides the ability to operate while transitioning to a new VID setting and its associated processor voltage rails (VCC, VSA, and VCCD). This is represented by a DC shift.
Electrical Specifications The SetVID- Decay command is preemptive, i.e, the VR interrupts its current processes and moves to the new VID. 7.1.9.3.5 SVID Power State Functions: SetPS The processor has three power state functions and these will be set seamlessly via the SVID bus using the SetPS command. Based on the power state command, the SetPS commands sends information to VR controller to configure the VR to improve efficiency, especially at light loads.
Electrical Specifications Figure 7-2. VR Power-State Transitions PS0 PS1 7.1.9.3.6 PS2 SVID Voltage Rail Addressing The processor addresses 4 different voltage rail control segments within VR12 (VCC, VCCD, and VSA). The SVID data packet contains a 4-bit addressing code: Table 7-2. SVID Address Usage PWM Address (HEX) Processor 00 Vcc 01 Vsa 02 VCCD 03 N/A 04 N/A 05 N/A Notes: 1. Check with VR vendors for determining the physical address assignment method for their controllers. 2.
Electrical Specifications Table 7-3. VR12.0 Reference Code Voltage Identification (VID) Table (Sheet 2 of 2) HEX VCC, VSA, VCCD 1.23500 E9 1.41000 1.24000 EA 1.41500 HEX VCC, VSA, VCCD HEX VCC, VSA, VCCD HEX VCC, VSA, VCCD HEX VCC, VSA, VCCD HEX VCC, VSA, VCCD 3A 0.53500 5D 0.71000 80 0.88500 A3 1.06000 C6 3B 0.54000 5E 0.71500 81 0.89000 A4 1.06500 C7 3C 0.54500 5F 0.72000 82 0.89500 A5 1.07000 C8 1.24500 EB 1.42000 3D 0.55000 60 0.72500 83 0.
Electrical Specifications signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. Resistor values should be within ± 20% of the impedance of the baseboard trace, unless otherwise noted in the appropriate platform design guidelines. 7.2 Signal Group Summary Signals are grouped by buffer type and similar characteristics as listed in Table 7-5. The buffer type indicates which signaling technology and specifications apply to the signals.
Electrical Specifications Table 7-5. Signal Groups (Sheet 2 of 3) Differential/Single Ended Single ended Signals1 Buffer Type CMOS1.
Electrical Specifications Table 7-5. Signal Groups (Sheet 3 of 3) Differential/Single Ended Signals1 Buffer Type SMBus Single ended Open Drain CMOS Input/Output DDR_SCL_C{1/23} DDR_SDA_C{1/23} PEHPSCL PEHPSDA CMOS1.0v Input TCK, TDI, TMS, TRST_N CMOS1.0v Input/Output PREQ_N JTAG & TAP Signals Single ended CMOS1.0v Output PRDY_N Open Drain CMOS Input/Output BPM_N[7:0] EAR_N Open Drain CMOS Output TDO Serial VID Interface (SVID) Signals Single ended CMOS1.
Electrical Specifications Table 7-6.
Electrical Specifications 7.4 Fault Resilient Booting (FRB) The processor supports both socket and core level Fault Resilient Booting (FRB), which provides the ability to boot the system as long as there is one processor functional in the system. One limitation to socket level FRB is that the system cannot boot if the legacy socket that connects to an active PCH becomes unavailable since this is the path to the system BIOS. See Table 7-8 for a list of output tri-state FRB signals.
Electrical Specifications Product Family Datasheet, Volume Two: Registers MSR and setting the processor core frequency. for details on the FLEX_RATIO Not all operating systems can support dual processors with mixed frequencies. Mixing processors of different steppings but the same model (as per CPUID instruction) is supported provided there is no more than one stepping delta between the processors, for example, S and S+1.
Electrical Specifications 2. 7.7.1 Overshoot and undershoot voltage guidelines for input, output, and I/O signals are outlined in Section 7.9.5. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor. Storage Condition Specifications Environmental storage condition limits define the temperature and relative humidity limits to which the device is exposed to while being stored in a Moisture Barrier Bag.
7.8.1 Voltage and Current Specifications Table 7-11. Voltage Specification Symbol Parameter VCC VID VCC VID Range VRetention VID Retention Voltage VID in Package C3 and C6 states VCC Core Voltage (Launch - FMB) VVID_STEP (Vcc, Vsa, Vccd) VID step size during a transition VCCPLL PLL Voltage VCCD Voltage Plane Max Unit Notes1 1.35 V 2, 3 0.65 V 2, 3 See Table 7-13 and Figure 7-3 V 3, 4, 7, 8, 12, 14, 18 5.0 mV 10 Min Typ 0.6 VCC VCCPLL 0.955*VCCPLL_TYP 1.70 1.
14. 15. 16. 17. For Power State Functions see Section 7.1.9.3.5. VSA_VID does not have a loadline, the output voltage is expected to be the VID value. VCCD tolerance at processor pins. Tolerance for VR at remote sense is ±3.3%*VCCD. The VCCPLL, VCCD voltage specification requirements are measured across vias on the platform. Choose VCCPLL, VCCD vias close to the socket and measure with a DC to 100MHz bandwidth oscilloscope limit (or DC to 20 MHz for older model oscilloscopes), using 1.
Table 7-13. Processor VCC Static and Transient Tolerance (Sheet 2 of 2) ICC [A] VCC_MAX [V] VCC_TYP [V] VCC_MIN [V] Notes 10 VID + 0.003 VID - 0.013 VID - 0.028 1,2,3,4 15 VID - 0.004 VID - 0.019 VID - 0.034 1,2,3,4 20 VID - 0.010 VID - 0.025 VID - 0.040 1,2,3,4 25 VID - 0.016 VID - 0.031 VID - 0.046 1,2,3,4 30 VID - 0.023 VID - 0.038 VID - 0.053 1,2,3,4 35 VID - 0.029 VID - 0.044 VID - 0.059 1,2,3,4 40 VID - 0.035 VID - 0.050 VID - 0.065 1,2,3,4 45 VID - 0.
Figure 7-3.
7.8.2 Die Voltage Validation Core voltage (VCC) overshoot events at the processor must meet the specifications in Table 7-14 when measured across the VCC_SENSE and VSS_VCC_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope. Figure 7-4. Load Current Versus Time Notes: 1. The peak current for any 5 second sample does not exceed Icc_max. 2.
Table 7-14. VCC Overshoot Specifications (Sheet 2 of 2) Symbol TOS_MAX Parameter Min Max Units Figure 25 μs 7-5 Time duration of VCC overshoot above VccMAX value at the new lighter load Figure 7-5. Notes VCC Overshoot Example Waveform VOS_MAX Voltage [V] VID + VOS_MAX VccMAX (I1) TOS_MAX 0 5 10 15 20 25 30 Time [us] Notes: 1. VOS_MAX is the measured overshoot voltage. 2. TOS_MAX is the measured time duration above VccMAX(I1). 3.
Table 7-15. DDR3 and DDR3L Signal DC Specifications (Sheet 2 of 2) Symbol Parameter Min Typ Max Units Notes1 VOL Output Low Voltage (VCCD / 2)* (RON /(RON+RVTT_TERM)) V 2, 7 VOH Output High Voltage VCCD - ((VCCD / 2)* (RON/(RON+RVTT_TE RM)) V 2, 5, 7 Reference Clock Signal RON DDR3 Clock Buffer On Resistance 21 31 Ω 6 RON DDR3 Command Buffer On Resistance 16 24 Ω 6 RON DDR3 Reset Buffer On Resistance 25 75 Ω 6 VOL_CMOS1.
11. DRAM_PWR_OK_C{1/23} must have a maximum of 30 ns rise or fall time over VCCD * 0.55 +300 mV and -200 mV and the edge must be monotonic. 12. The DDR1/23_RCOMP error tolerance is +/- 15% from the compensated value. 13. DRAM_PWR_OK_C{1/23}: Data Scrambling must be enabled for production environments. Disabling Data scrambling can be used for debug and testing purposes only. Running systems with Data Scrambling off will make the configuration out of specification.
8. For Vin between 0 and Vih. Table 7-18. SMBus DC Specifications Symbol Parameter Min VIL Input Low Voltage VIH Input High Voltage 0.7*VTT VHysteresis Hysteresis 0.1*VTT VOL Output Low Voltage RON Buffer On Resistance IL Leakage Current Max Units 0.3*VTT V V V 0.2*VTT Output Edge Rate (50 ohm to VTT, between VIL and VIH) Notes V 4 14 Ω 50 200 μA 0.05 0.6 V/ns Table 7-19.
Table 7-20. Serial VID Interface (SVID) DC Specifications (Sheet 2 of 2) Symbol Parameter Min Input Edge Rate Signal: SVIDALERT_N 0.05 Output Edge Rate (50 ohm to VTT) 0.20 Typ Max 1.5 Units Notes V/ns 5, 6 V/ns 5 Notes: 1. VTT refers to instantaneous VTT. 2. Measured at 0.31*VTT 3. Vin between 0V and VTT 4. Refer to the Platform Design Guide (PDG) for routing design guidelines. 5. These are measured between VIL and VIH. 6.
Table 7-22. Miscellaneous Signals DC Specifications (Sheet 2 of 2) Symbol Parameter Min Typical VO_ABS_MAX Output Absolute Max Voltage IO Output Current N/A VO_ABS_MAX Output Absolute Max Voltage 3.30 IOMAX Output Max Current Max Units 1.80 V Notes 1, 2 1, 2 SKTOCC_N Signal 3.50 V 1 1 mA 1 Notes: 1. For specific routing guidelines, see the Platform Design Guide (PDG) for details. 2. IVT_ID_N land is connected to the Vss plane within the package substrate. 7.8.3.
7.8.3.6 DMI2/PCI Express* AC Specifications The processor AC specifications for the PCI Express* are available in the PCI Express Base Specification 2.0 and 1.0. This document will provide only the processor exceptions to the PCI Express Base Specification 2.0 and 1.0. 7.8.3.7 Intel® QuickPath Interconnect AC Specifications Intel® QuickPath Interconnect specifications are defined at the processor lands. Please refer to the appropriate platform design guidelines for specific implementation details.
Figure 7-7. BCLK{0/1} Differential Clock Measurement Points for Duty Cycle and Period Clock Period (Differential) Positive Duty Cycle (Differential) Negative Duty Cycle (Differential) 0.0V BCLK Figure 7-8. BCLK{0/1} Differential Clock Measurement Points for Edge Rate Rise Edge Rate Fall Edge Rate VIH = +150 mV 0.0V VIL = -150 mV BCLK Figure 7-9. BCLK{0/1} Differential Clock Measurement Point for Ringback T STABLE VRB-Differential VIH = +150 mV VRB = +100 mV 0.
Figure 7-10. BCLK{0/1} Single Ended Clock Measurement Points for Absolute Cross Point and Swing VMAX = 1.40V BCLK_DN VCROSS MAX = 550mV VCROSS MIN = 250mV BCLK_DP VMIN = -0.30V Figure 7-11. BCLK{0/1} Single Ended Clock Measurement Points for Delta Cross Point BCLK_DN VCROSS DELTA = 140 mV BCLK_DP 7.9 Signal Quality Data transfer requires the clean reception of data signals and clock signals.
7.9.1 DDR3 Signal Quality Specifications Various scenarios for the DDR3 Signals have been simulated to generate a set of layout guidelines which are available in the Platform Design Guide (PDG). Overshoot (or undershoot) is the absolute value of the maximum voltage above or below VSS. The overshoot/undershoot specifications limit transitions beyond specified maximum voltages or VSS due to the fast signal edge rates.
Table 7-23. Processor I/O Overshoot/Undershoot Specifications Signal Group Minimum Undershoot Maximum Overshoot Overshoot Duration Undershoot Duration Notes Intel QuickPath Interconnect -0.2 * VTT 1.2 * VTT 39 ps 15 ps 1,2 DDR3 -0.2 * VCCD 1.2 * VCCD 0.25*TCH 0.1*TCH 1,2,3 System Reference Clock (BCLK{0/1}) PWRGOOD Signal -0.3V 1.15V N/A N/A 1,2 -0.420V VTT + 0.28 N/A N/A 4 Notes: 1. These specifications are measured at the processor pad. 2.
7.9.5.4 Reading Overshoot/Undershoot Specification Tables The overshoot/undershoot specification for the processor is not a simple single value. Instead, many factors are needed to determine the over/undershoot specification. In addition to the magnitude of the overshoot, the following parameters must also be known: the width of the overshoot and the activity factor (AF). To determine the allowed overshoot for a particular overshoot event, the following must be done: 1.
Figure 7-12.
Processor Land Listing 8 Processor Land Listing This chapter provides sorted land list in Section 8.1 and Section 8.2. Table 8-1 is a listing of all Intel® Xeon® processor E5-2400 v2 product family lands ordered alphabetically by land name. Table 8-2 is a listing of all processor lands ordered by land number. 8.1 Listing by Land Name Table 8-1.
Processor Land Listing Table 8-1. Land Name (Sheet 3 of 37) Land Number Buffer Type Direction DDR1_DQ[09] T36 SSTL I/O DDR1_DQ[10] N36 SSTL DDR1_DQ[11] N35 SSTL DDR1_DQ[12] U35 DDR1_DQ[13] U36 Land Name Table 8-1.
Processor Land Listing Table 8-1. Land Name (Sheet 5 of 37) Table 8-1.
Processor Land Listing Table 8-1. Land Name DDR2_DQ[02] Land Name (Sheet 7 of 37) Table 8-1.
Processor Land Listing Table 8-1. Land Name (Sheet 9 of 37) Land Name Land Number Buffer Type Direction DDR2_DQS_DN[14] H8 SSTL I/O DDR2_DQS_DN[15] R5 SSTL DDR2_DQS_DN[16] AB5 SSTL DDR2_DQS_DN[17] D32 DDR2_DQS_DP[00] AA38 Table 8-1.
Processor Land Listing Table 8-1. Land Name (Sheet 11 of 37) Land Number Buffer Type Direction D11 SSTL O DDR3_CS_N[4] A15 SSTL DDR3_CS_N[5] B14 SSTL DDR3_CS_N[6] C11 DDR3_CS_N[7] Table 8-1.
Processor Land Listing Table 8-1. Land Name (Sheet 13 of 37) Land Name Land Number Buffer Type Direction DDR3_DQS_DN[07] T3 SSTL I/O Table 8-1.
Processor Land Listing Table 8-1. Land Name (Sheet 15 of 37) Land Number Buffer Type Direction DMI_TX_DP[3] AJ37 PCIEX O TXT_PLTEN AN8 CMOS DRAM_PWR_OK_C1 Y10 CMOS_1.5V DRAM_PWR_OK_C2 3 AD40 EAR_N Table 8-1. Land Name (Sheet 16 of 37) Land Number Buffer Type Direction PE1B_RX_DP[6] AW38 PCIEX3 I I PE1B_RX_DP[7] AV37 PCIEX3 I I PE1B_TX_DN[4] AF41 PCIEX3 O CMOS_1.
Processor Land Listing Table 8-1. Land Name (Sheet 17 of 37) Table 8-1.
Processor Land Listing Table 8-1. Land Name (Sheet 19 of 37) Land Name QPI1_DRX_DP[05] Land Number Buffer Type Direction AP2 Intel QPI I Table 8-1.
Processor Land Listing Table 8-1. Land Name (Sheet 21 of 37) Land Name Land Number Buffer Type Table 8-1.
Processor Land Listing Table 8-1. Land Name (Sheet 23 of 37) Land Number Buffer Type VCC AL25 PWR VCC AL27 VCC AL28 VCC Table 8-1.
Processor Land Listing Table 8-1. Land Name (Sheet 25 of 37) Land Number Buffer Type VCC AW19 PWR VCC AW21 VCC AW22 VCC Table 8-1.
Processor Land Listing Table 8-1. Land Name (Sheet 27 of 37) Land Number Buffer Type VSA AY42 PWR VSA_SENSE AE33 Land Name Table 8-1.
Processor Land Listing Table 8-1. Land Name (Sheet 29 of 37) Land Number Buffer Type VSS AL26 GND VSS AL29 VSS AL35 VSS Table 8-1.
Processor Land Listing Table 8-1. Land Name VSS Land Name (Sheet 31 of 37) Land Number Buffer Type AV8 GND Table 8-1.
Processor Land Listing Table 8-1. Land Name (Sheet 33 of 37) Table 8-1.
Processor Land Listing Table 8-1. Land Name (Sheet 35 of 37) Table 8-1.
Processor Land Listing Table 8-1. Land Name (Sheet 37 of 37) Land Number Buffer Type VTTD M26 PWR VTTD M29 PWR VTTD M30 PWR VTTD M31 PWR VTTD_SENSE AK34 Land Name Direction O 8.2 Listing by Land Number Table 8-2. Land Number (Sheet 1 of 37) Table 8-2.
Processor Land Listing Table 8-2. Land Number Land Number (Sheet 3 of 37) Land Name Buffer Type Table 8-2.
Processor Land Listing Table 8-2. Land Number AF1 Land Number (Sheet 5 of 37) Land Name BMCINIT Buffer Type Direction CMOS I Table 8-2.
Processor Land Listing Table 8-2. Land Number AJ38 Land Number (Sheet 7 of 37) Land Name VSS Buffer Type Table 8-2.
Processor Land Listing Table 8-2. Land Number AL29 Land Number (Sheet 9 of 37) Land Name VSS Buffer Type Table 8-2.
Processor Land Listing Table 8-2. Land Number (Sheet 11 of 37) Land Number Land Name Buffer Type Direction Intel QPI I Table 8-2.
Processor Land Listing Table 8-2. Land Number (Sheet 13 of 37) Table 8-2.
Processor Land Listing Table 8-2. Land Number (Sheet 15 of 37) Land Number AT40 Land Name VSA Buffer Type Table 8-2.
Processor Land Listing Table 8-2.
Processor Land Listing Table 8-2. Land Number Land Number (Sheet 19 of 37) Land Name AY27 VCC AY28 VCC AY29 PE3D_RX_DP[15] AY3 Buffer Type Table 8-2.
Processor Land Listing Table 8-2. Land Number BA28 Land Number (Sheet 21 of 37) Land Name VCC Buffer Type Table 8-2.
Processor Land Listing Table 8-2. Land Number D27 Land Number (Sheet 23 of 37) Land Name DDR2_CKE[0] Table 8-2.
Processor Land Listing Table 8-2. Land Number Land Number (Sheet 25 of 37) Land Name Buffer Type Direction SSTL O Table 8-2.
Processor Land Listing Table 8-2. Land Number Land Number (Sheet 27 of 37) Land Name Buffer Type Direction SSTL I/O Table 8-2.
Processor Land Listing Table 8-2. Land Number J39 Land Number (Sheet 29 of 37) Land Name DDR2_DQ[17] Table 8-2.
Processor Land Listing Table 8-2. Land Number L3 Land Number (Sheet 31 of 37) Land Name DDR3_DQS_DN[15] Table 8-2.
Processor Land Listing Table 8-2. Land Number Land Number (Sheet 33 of 37) Land Name Buffer Type Table 8-2.
Processor Land Listing Table 8-2. Land Number Land Number (Sheet 35 of 37) Land Name Buffer Type Direction I/O Table 8-2.
Processor Land Listing Table 8-2.
Package Mechanical Specifications 9 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FCLGA12)package that interfaces with the baseboard via an 1356-2 socket. The package consists of a processor mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Package Mechanical Specifications 7. Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the Intel® Xeon® Processor E52400 v2 Product Family Thermal/Mechanical Design Guide (TMDG).
Package Mechanical Specifications Figure 9-2.
Package Mechanical Specifications Figure 9-3.
Package Mechanical Specifications 9.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep-out zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Do not contact the Test Pad Area with conductive material. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 9-2 through Figure 9-3 for keep-out zones.
Package Mechanical Specifications 9.6 Processor Mass Specification The typical mass of the processor is currently 35 grams. This mass [weight] includes all the components that are included in the package. 9.7 Processor Materials Table 9-3 lists some of the package components and associated materials. Table 9-3. Processor Materials Component Material Integrated Heat Spreader (IHS) Nickel Plated Copper Substrate Halogen Free, Fiber Reinforced Resin Substrate Lands 9.
Boxed Processor Specifications 10 Boxed Processor Specifications 10.1 Introduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels. The Intel® Xeon® processor E52400 v2 product family (LGA1356) processors will be offered as Intel boxed processors, however the thermal solutions will be sold separately. Boxed processors will not include a thermal solution in the box.
Boxed Processor Specifications Figure 10-1. STS100C Passive/Active Combination Heat Sink (with Removable Fan) Figure 10-2. STS100C Passive/Active Combination Heat Sink (with Fan Removed) 10.1.3 Intel Thermal Solution STS100A (Active Heat Sink Solution) The STS100A in the active fan configuration is primarily designed to be used in a pedestal chassis where sufficient air inlet space is present (see Figure 10-3).
Boxed Processor Specifications on the PWM and PECI interface along with Digital Thermal Sensors (DTS). Figure 10-3. STS100A Active Heat Sink 10.1.4 Intel Thermal Solution STS100P (Boxed 25.5 mm Tall Passive Heat Sink Solution) The STS100Pis available for use with boxed processors that have TDP’s of 95W and lower. The 25.5 mm Tall passive solution is designed to be used in SSI Blades, 1U, and 2U chassis where ducting is present. The use of a 25.
Boxed Processor Specifications 10.2 Mechanical Specifications This section documents the mechanical specifications of the boxed processor solution. 10.2.1 Boxed Processor Heat Sink Dimensions and Baseboard Keepout Zones The boxed processor and boxed thermal solutions will be sold separately. Clearance is required around the thermal solution to ensure unimpeded airflow for proper cooling. Baseboard keepout zones are Figure 10-5 - Figure 10-8.
Boxed Processor Specifications Figure 10-5.
Boxed Processor Specifications Figure 10-6.
Boxed Processor Specifications Figure 10-7.
Boxed Processor Specifications Figure 10-8.
Intel® Xeon® Processor E5-2400 v2 Product Family Datasheet Volume One 208 A B C D 8 7 6 5 8 [ B 0 91.50 -0.25 +0.000 3.602 -0.009 C ] 7 +1.00 0 +0.039 -0.000 TOP VIEW ] 0.472 0 -0.25 +0.000 -0.009 3.602 91.50 [ [ 4X 12.00 ] 6 A +1.00 0 +0.039 -0.000 0.472 ] 64.00 [2.520] MAX. AIRFLOW DIRECTION [ 4X 12.00 5 THIS DRAWING CONTAINS INTEL CORPORAT ION CONFIDENTIAL INFORMATION.
Intel® Xeon® Processor E5-2400 v2 Product Family Datasheet Volume One 209 A B C D 8 7 6 5 8 80.00 [3.150] 9 38.00 #0.50 [1.496 #0.019 ] A 7 A-A 9 80.00 [3.150] 38.00 #0.50 [1.496 #0.019 ] SECTION 6 BOTTOM VIEW FLATNESS ZONE, SEE NOTE 7 0.077 [0.0030] B SEE DETAIL 5 AIRFLOW DIRECTION A C SEE DETAIL AIRFLOW DIRECTION TOP VIEW THIS DRAWING CONTAINS INTEL CORPORAT ION CONFIDENTIAL INFORMATION.
Boxed Processor Specifications Figure 10-11.
Boxed Processor Specifications Figure 10-12.
Boxed Processor Specifications 10.2.2 Boxed Processor Retention Mechanism and Heat Sink Support (URS) Baseboards designed for use by a system integrator should include holes that are in proper alignment with each other to support the boxed processor. Refer to Figure 10-5 through Figure 10-8 for LGA1356 mounting hole dimensions. LGA1356 Unified Retention System (URS) and the Unified Backplate Assembly.
Boxed Processor Specifications Figure 10-13.Fan Cable Connector Pin Out For 4-Pin Active Thermal Solution Table 10-3. PWM Fan Connector Pin and Wire Description 10.3.1 Pin Number Signal Wire Color 1 Ground Black 2 Power (+12V) Yellow 3 Sense: 2 pulse per revolution Green 4 Control: 21KHz - 28KHz Blue Boxed Processor Cooling Requirements As previously stated the boxed processor will have three thermal solutions available. Each configuration will require unique design considerations.
Boxed Processor Specifications In the passive configuration it is assumed that a chassis duct will be implemented. For a list processor and thermal solution boundary conditions, such as Psica, TLA, airflow, flow impedance, etc, Table 10-4. It is recommended that the ambient air temperature outside of the chassis be kept at or below 35 °C. Meeting the processor’s temperature specification is the responsibility of the system integrator.
Boxed Processor Specifications Table 10-4. Processor Thermal Solution Boundary Conditions Form Factor Thermal Solution Heatsink Volumetric4 (mm) Airflow 3 (CFM) (inch of H2O) Delta P STS100A (with fan) Pedestal 90 x 90 x 64 Max RPM N/A STS100C (with fan) TDP (W) Core Count (˚C/W) ΨCA2 TLA 1 (˚C) 95 10 0.281 53.3 95 8 0.285 52.9 80 6/4 0.298 52.2 60 10 0.278 51.3 60 6 0.299 51.1 95 10 0.180 62.9 95 8 0.184 62.5 80 6/4 0.197 60.2 60 10 0.177 57.4 60 6 0.
Boxed Processor Specifications 10.4 Boxed Processor Contents The Boxed Processor and Boxed Thermal Solution contents are outlined below.
