Datasheet

Intel® Xeon® Processor E5-2400 v2 Product Family 118
Datasheet Volume One
Signal Descriptions
6.4 Intel® QuickPath Interconnect Signals
Note: Refer to the Platform Design Guide (PDG) for additional implementation details.
6.5 PECI Signal
6.6 System Reference Clock Signals
Table 6-7. Intel QPI Port Signals
Signal Name Description
QPI_CLKRX_DN/DP Reference Clock Differential Input. These pins provide the PLL
reference clock differential input. The Intel QPI forward clock
frequency is half the Intel QPI data rate.
QPI_CLKTX_DN/DP Reference Clock Differential Output. These pins provide the PLL
reference clock differential input. The Intel QPI forward clock
frequency is half the Intel QPI data rate.
QPI_DRX_DN/DP[19:00] Intel QPI Receive data input.
QPI_DTX_DN/DP[19:00] Intel QPI Transmit data output.
Table 6-8. Intel QPI Miscellaneous Signals
Signal Name Description
QPI_RBIAS This input is used to control Intel QPI bias currents. QPI_RBIAS is
required to be connected as if the link is being used even when QPI
is not used. Refer to the Platform Design Guide (PDG) for further
details.
QPI_RBIAS_SENSE Provides dedicated bias resistor sensing to minimize the voltage
drop caused by packaging and platform effects.
QPI_RBIAS_SENSE is required to be connected as if the link is
being used even when Intel QPI is not used. Refer to the Platform
Design Guide (PDG) for further details.
QPI_VREF_CAP Intel QPI voltage reference used to measure the actual output
voltage and comparing it to the assumed voltage. Refer to the
Platform Design Guide (PDG) for further details.
Table 6-9. PECI Signals
Signal Name Description
PECI PECI (Platform Environment Control Interface) is the serial
sideband interface to the processor and is used primarily for
thermal, power and error management. Details regarding the PECI
electrical specifications, protocols and functions can be found in
the Platform Environment Control Interface Specification.
Table 6-10. System Reference Clock (BCLK) Signals
Signal Name Description
BCLK{0/1}_D[N/P] Reference Clock Differential input. These pins provide the PLL
reference clock differential input into the processor. 100 MHz
typical BCLK0 is the Intel QPI reference clock (system clock) and
BCLK1 is the PCI Express* reference clock.