Datasheet

Intel® Xeon® Processor E5-2400 v2 Product Family 130
Datasheet Volume One
Electrical Specifications
7.1.9.3.6 SVID Voltage Rail Addressing
The processor addresses 4 different voltage rail control segments within VR12 (VCC,
VCCD, and VSA). The SVID data packet contains a 4-bit addressing code:
Notes:
1. Check with VR vendors for determining the physical address assignment method for their controllers.
2. VR addressing is assigned on a per voltage rail basis.
3. Dual VR controllers will have two addresses with the lowest order address, always being the higher phase
count.
4. For future platform flexibility, the VR controller should include an address offset, as shown with +1 not
used.
Figure 7-2. VR Power-State Transitions
PS0
PS2PS1
Table 7-2. SVID Address Usage
PWM Address (HEX) Processor
00 V
cc
01 V
sa
02 V
CCD
03 N/A
04 N/A
05 N/A
Table 7-3. VR12.0 Reference Code Voltage Identification (VID) Table (Sheet 1 of 2)
HEX
VCC, VSA,
VCCD
HEX
VCC, VSA,
VCCD
HEX
VCC, VSA,
VCCD
HEX
VCC, VSA,
VCCD
HEX
VCC, VSA,
VCCD
HEX
VCC, VSA,
VCCD
00 0.00000 55 0.67000 78 0.84500 9B 1.02000 BE 1.19500 E1 1.37000
33 0.50000 56 0.67500 79 0.85000 9C 1.02500 BF 1.20000 E2 1.37500
34 0.50500 57 0.68000 7A 0.85500 9D 1.03000 C0 1.20500 E3 1.38000
35 0.51000 58 0.68500 7B 0.86000 9E 1.03500 C1 1.21000 E4 1.38500
36 0.51500 59 0.69000 7C 0.86500 9F 1.04000 C2 1.21500 E5 1.39000
37 0.52000 5A 0.69500 7D 0.87000 A0 1.04500 C3 1.22000 E6 1.39500
38 0.52500 5B 0.70000 7E 0.87500 A1 1.05000 C4 1.22500 E7 1.40000
39 0.53000 5C 0.70500 7F 0.88000 A2 1.05500 C5 1.23000 E8 1.40500