Datasheet

Intel® Xeon® Processor E5-2400 v2 Product Family 132
Datasheet Volume One
Electrical Specifications
signals to power or ground. When tying any signal to power or ground, a resistor will
also allow for system testability. Resistor values should be within ± 20% of the
impedance of the baseboard trace, unless otherwise noted in the appropriate platform
design guidelines.
7.2 Signal Group Summary
Signals are grouped by buffer type and similar characteristics as listed in Table 7-5. The
buffer type indicates which signaling technology and specifications apply to the signals.
Table 7-4. Signal Description Buffer Types
Signal Description
Analog Analog reference or output. May be used as a threshold voltage or for buffer
compensation
Asynchronous
1
Signal has no timing relationship with any system reference clock.
CMOS CMOS buffers: 1.0 V or 1.5 V tolerant
DDR3 DDR3 buffers: 1.5 V and 1.35 V tolerant
DMI2 Direct Media Interface Gen 2 signals. These signals are compatible with PCI Express*
2.0 and 1.0 Signaling Environment AC Specifications.
Intel® QPI Current-mode 6.4 GT/s and 8.0 GT/s forwarded-clock Intel QuickPath Interconnect
signaling
Open Drain CMOS Open Drain CMOS (ODCMOS) buffers: 1.0V tolerant
PCI Express* PCI Express* interface signals. These signals are compatible with PCI Express 3.0
Signalling Environment AC Specifications and are AC coupled. The buffers are not
3.3-V tolerant. Refer to the PCIe specification.
Reference Voltage reference signal.
SSTL Source Series Terminated Logic (JEDEC SSTL_15)
Notes:
1. Qualifier for a buffer type.
Table 7-5. Signal Groups (Sheet 1 of 3)
Differential/Single
Ended
Buffer Type Signals
1
DDR3 Reference Clocks
2
Differential SSTL Output DDR{1/2/3}_CLK_D[N/P][3:0]
DDR3 Command Signals
2
Single ended SSTL Output DDR{1/2/3}_BA[2:0]
DDR{1/2/3}_CAS_N
DDR{1/2/3}_MA[15:00]
DDR{1/2/3}_MA_PAR
DDR{1/2/3}_RAS_N
DDR{1/2/3}_WE_N
CMOS1.5v Output DDR_RESET_C{1/23}_N
DDR3 Control Signals
2