Datasheet

Intel® Xeon® Processor E5-2400 v2 Product Family 140
Datasheet Volume One
14. For Power State Functions see Section 7.1.9.3.5.
15. V
SA_VID
does not have a loadline, the output voltage is expected to be the VID value.
16. V
CCD
tolerance at processor pins. Tolerance for VR at remote sense is ±3.3%*V
CCD
.
17. The V
CCPLL
, V
CCD
voltage specification requirements are measured across vias on the platform. Choose V
CCPLL
, V
CCD
vias close
to the socket and measure with a DC to 100MHz bandwidth oscilloscope limit (or DC to 20 MHz for older model oscilloscopes),
using 1.5 pF maximum probe capacitance, and 1M Ω minimum impedance. The maximum length of the ground wire on the
probe should be less than 5 mm to ensure external noise from the system is not coupled in the scope probe.
18. V
CC
has a Vboot setting of 0.0V and is not included in the PWRGOOD indication. Refer to the VR12/IMVP7 Pulse Width
Modulation Specification.
19. V
SA
has a Vboot setting of 0.9V. Refer to the VR12/IMVP7 Pulse Width Modulation Specification.
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processors. These specifications are based on silicon
characterization.
2. Launch to FMB, See Section 7.6, “Flexible Motherboard Guidelines (FMB)” for details.
3. TDC (Thermal Design Current) is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely
and should be used for the voltage regulator thermal assessment. The voltage regulator is responsible for monitoring its
temperature and asserting the necessary signal to inform the processor of a thermal excursion. Please refer to the VR12/
IMVP7 Pulse Width Modulation Specification for further details.
4. Specification is at T
CASE
= 50 °C. Characterized by design (not tested).
5. I
CCD
specifications are current draw on V
CCD
of processor only and do not include current consumption by memory devices.
6. Minimum VCC and maximum ICC are specified at the maximum processor case temperature (T
CASE
) shown in Section 5,
“Thermal Management Specifications”. ICC_MAX is specified at the relative VCC_MAX point on the VCC load line. The
processor is capable of drawing ICC_MAX for up to 5 seconds. Refer to Section 7-4, “Load Current Versus Time” for details on
processor current draw over various durations.
Table 7-12. Processor Supply Current Specifications
Parameter and Definition Processor TDP / Core count
TDC
(A)
Max
(A)
Notes
1
I
TT
I/O Termination Supply,
Processor Current on V
TTA
/V
TTD
All Intel® Xeon® Processor E5-2400 v2 Product
Family
16 20
2,3,6
I
SA
System Agent Supply,
Processor Current on V
SA
18 19
I
CCPLL
PLL Supply,
Processor Current on V
CCPLL
22
I
CCD
Memory Controller DDR3 Supply,
Processor Current on V
CCD
57
I
CCD_S3
Memory Controller Supply,
Processor Current on V
CCD
while in System
S3 Standby State
-- 1 4,5
I
CC
Core Processor Supply,
Processor Current on V
CC
95W 10-core / 8-core 106 135
2,3,6
80W 6-core / 4-core 80 85
80W 4-core 1S / 2-core 1S 70 80
LV70W-10C 90 110
60W 10-core / 6-core 75 90
LV60W-8C / LV60W-6C 1S 75 90
LV50W-6C 65 80
LV40W-2C 1S 40 50
Table 7-13. Processor VCC Static and Transient Tolerance (Sheet 1 of 2)
I
CC
[A] V
CC_MAX
[V] V
CC_TYP
[V] V
CC_MIN
[V] Notes
0 VID + 0.015 VID - 0.000 VID - 0.015 1,2,3,4
5 VID + 0.009 VID - 0.006 VID - 0.021 1,2,3,4