Datasheet

Intel® Xeon® Processor E5-2400 v2 Product Family 148
Datasheet Volume One
Notes:
1. V
TT
refers to instantaneous V
TT
.
2. Measured at 0.31*V
TT
3. Vin between 0V and V
TT
4. Refer to the Platform Design Guide (PDG) for routing design guidelines.
5. These are measured between VIL and VIH.
6. The signal edge rate must be met or the signal must transition monotonically to the asserted state.
Notes:
1. This table applies to the processor sideband and miscellaneous signals specified in Table 7-5.
2. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
3. These signals are measured between VIL and VIH.
Input Edge Rate
Signal: SVIDALERT_N
0.05 V/ns 5, 6
Output Edge Rate (50 ohm to V
TT
)0.20 1.5V/ns5
Table 7-21. Processor Asynchronous Sideband DC Specifications
Symbol Parameter Min Max Units Notes
CMOS1.0v Signals
V
IL_CMOS1.0v
Input Low Voltage 0.3*V
TT
V1,2
V
IH_CMOS1.0v
Input High Voltage 0.7*V
TT
V1,2
V
Hysteresis
Hysteresis 0.1*V
TT
V1,2
I
IL_CMOS1.0v
Input Leakage Current 50 200 μA1,2
Open Drain CMOS (ODCMOS) Signals
V
IL_ODCMOS
Input Low Voltage
Signals:
MEM_HOT_C01/23_N,
PROCHOT_N
0.3*V
TT
V1,2
V
IL_ODCMOS
Input Low Voltage
Signals: CAT_ERR_N
0.4*V
TT
V1,2
V
IH_ODCMOS
Input High Voltage 0.7*V
TT
V1,2
V
OL_ODCMOS
Output Low Voltage 0.2*V
TT
V1,2
V
Hysteresis
Hysteresis
Signals:
MEM_HOT_C01/23_N,
PROCHOT_N
0.1*V
TT
V1,2
V
Hysteresis
Hysteresis
Signal: CAT_ERR_N
0.05*V
TT
V1,2
I
Leak
Input Leakage Current 50 200 μA
R
ON
Buffer On Resistance 4 14 Ω 1,2
Output Edge Rate
Signal:MEM_HOT_C{1/23}_N,
ERROR_N[2:0], THERMTRIP,
PROCHOT_N
0.05 0.60 V/ns 3
Output Edge Rate
Signal: CAT_ERR_N
0.2 1.5 V/ns 3
Table 7-22. Miscellaneous Signals DC Specifications (Sheet 1 of 2)
Symbol Parameter Min Typical Max Units Notes
IVT_ID_N Signal
Table 7-20. Serial VID Interface (SVID) DC Specifications (Sheet 2 of 2)
Symbol Parameter Min Typ Max Units Notes