Datasheet

Intel® Xeon® Processor E5-2400 v2 Product Family 153
Datasheet Volume One
7.9.1 DDR3 Signal Quality Specifications
Various scenarios for the DDR3 Signals have been simulated to generate a set of layout
guidelines which are available in the
Platform Design Guide (PDG).
Overshoot (or undershoot) is the absolute value of the maximum voltage above or
below V
SS
. The overshoot/undershoot specifications limit transitions beyond specified
maximum voltages or V
SS
due to the fast signal edge rates. The processor can be
damaged by single and/or repeated overshoot or undershoot events on any input,
output, or I/O buffer if the charge is large enough (i.e., if the over/undershoot is great
enough). Baseboard designs which meet signal integrity and timing requirements and
which do not exceed the maximum overshoot or undershoot limits listed in Table 7-23
will insure reliable IO performance for the lifetime of the processor.
7.9.2 I/O Signal Quality Specifications
Signal Quality specifications for PCIe Signals are included as part of the PCIe DC
specifications and PCIe AC specifications. Various scenarios have been simulated to
generate a set of layout guidelines which are available in the
Platform Design Guide
(PDG).
7.9.3 Intel® QuickPath Interconnect Signal Quality
Specifications
Signal Quality specifications for Differential Intel® QuickPath Interconnect Signals are
included as part of the Intel QuickPath Interconnect defined in the
Intel® QuickPath
Interconnect V1.1 Base Electrical Specification and Validation Methodologies. Various
scenarios have been simulated to generate a set of layout guidelines which are
available in the
Platform Design Guide (PDG).
7.9.4 Input Reference Clock Signal Quality Specifications
Overshoot/Undershoot and Ringback specifications for BCLK{0/1}_D[N/P] are found in
Table 7-23. Overshoot/Undershoot and Ringback specifications for the DDR3 Reference
Clocks are specified by the DIMM.
7.9.5 Overshoot/Undershoot Tolerance
Overshoot (or undershoot) is the absolute value of the maximum voltage above or
below V
SS,
see Figure 7-12. The overshoot/undershoot specifications limit transitions
beyond V
CCD
or V
SS
due to the fast signal edge rates. The processor can be damaged
by single and/or repeated overshoot or undershoot events on any input, output, or I/O
buffer if the charge is large enough (that is, if the over/undershoot is great enough).
Determining the impact of an overshoot/undershoot condition requires knowledge of
the magnitude, the pulse direction, and the activity factor (AF). Permanent damage to
the processor is the likely result of excessive overshoot/undershoot.
Baseboard designs which meet signal integrity and timing requirements and which do
not exceed the maximum overshoot or undershoot limits listed in Table 7-23 will insure
reliable IO performance for the lifetime of the processor.