Datasheet

Intel® Xeon® Processor E5-2400 v2 Product Family 18
Datasheet Volume One
Overview
• Supports only x4 link width when in DMI2 mode
• Operates at PCI Express* 1.0 or 2.0 speeds
• Transparent to software
• Processor and peer-to-peer writes and reads with 64-bit address support
• APIC and Message Signaled Interrupt (MSI) support. Will send Intel-defined “End of
Interrupt” broadcast message when initiated by the processor.
• Downstream System Management Interrupt (SMI), SCI, and SERR error indication
• Static lane numbering reversal support
• Supports DMI2 virtual channels VC0, VC1, VCm, and VCp
1.2.4 Intel® QuickPath Interconnect (Intel® QPI)
• Compliant with Intel QuickPath Interconnect v1.1 standard packet formats
• Implements a full width Intel QuickPath Interconnect port
• Full width port includes 20 data lanes and 1 clock lane
• 64 byte cache-lines
• Isochronous access support for Quality of Service (QoS), native 2-socket platforms
only
• Home snoop based coherency
•4-bit Node ID
• 46-bit physical addressing support
• No Intel QuickPath Interconnect bifurcation support
• Differential signaling
• Forwarded clocking
• Up to 8.0 GT/s data rate (up to 16 GB/s direction peak bandwidth per port)
— All ports run at same operational frequency
— Reference Clock is 100 MHz
— Slow boot speed initialization at 50 MT/s
• Common reference clocking (same clock generator for both sender and receiver)
• Intel® Interconnect Built-In-Self-Test (Intel® IBIST) for high-speed testability
• Polarity Inversion and Lane reversal (Rx side only)
1.2.5 Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between a
PECI client (the processor) and a PECI master (the PCH). The PECI interface is based
on revision 3.0 of the RS - Platform Environment Control Interface (PECI) Specification.
Refer to Section 2.5, “Platform Environment Control Interface (PECI)” for additional
details on PECI services available in the processor.
• Supports operation at up to 2 Mbps data transfers
• Link layer improvements to support additional services and higher efficiency over
PECI 2.0 generation
• Services include CPU thermal and estimated power information, control functions
for power limiting, P-state and T-state control, and access for Machine Check