Datasheet

Intel® Xeon® Processor E5-2400 v2 Product Family 24
Datasheet Volume One
Interfaces
2 Interfaces
This chapter describes the interfaces supported by the processor. For functional
descriptions and additional details of these interfaces see Intel® Xeon® Processor E5
v2 Product Family Datasheet, Volume Two: Registers.
2.1 System Memory Interface
2.1.1 System Memory Technology Support
The Integrated Memory Controller (IMC) supports DDR3 protocols with
threeindependent 64-bit memory channels with 8 bits of ECC for each channel (total of
72-bits) and supports 2 DIMMs per channel. The type of memory supported by the
processor is dependent on the target platform:
• Intel® Xeon® processor E5-2400 v2 product family-based platforms support:
— ECC registered DIMMs: with a maximum of two DIMMs per channel allowing up
to eight device ranks per channel.
— ECC and non-ECC unbuffered DIMMs: with a maximum of two DIMMs per
channel thus allowing up to four device ranks per channel. Support for mixed
non-ECC with ECC un-buffered DIMM configurations.
2.1.2 System Memory Timing Support
The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and
command signal mode timings on the main memory interface:
• tCL = CAS Latency
• tRCD = Activate Command to READ or WRITE Command delay
• tRP = PRECHARGE Command Period
• CWL = CAS Write Latency
• Command Signal modes = 1n indicates a new command may be issued every clock
and 2n indicates a new command may be issued every 2 clocks. Command launch
mode programming depends on the transfer rate and memory configuration.