Datasheet

Intel® Xeon® Processor E5-2400 v2 Product Family 5
Datasheet Volume One
4.2.4.4 Core C6 State...........................................................................91
4.2.4.5 Delayed Deep C-States..............................................................91
4.2.5 Package C-States...................................................................................91
4.2.5.1 Package C0.............................................................................. 93
4.2.5.2 Package C1/C1E .......................................................................93
4.2.5.3 Package C2 State...................................................................... 94
4.2.5.4 Package C3 State...................................................................... 94
4.2.5.5 Package C6 State...................................................................... 94
4.2.6 Package C-State Power Specifications .......................................................95
4.2.7 Processor Pmax Power Specifications ........................................................95
4.3 System Memory Power Management....................................................................96
4.3.1 CKE Power-Down ...................................................................................96
4.3.2 Self Refresh...........................................................................................96
4.3.2.1 Self Refresh Entry.....................................................................97
4.3.2.2 Self Refresh Exit.......................................................................97
4.3.2.3 DLL and PLL Shutdown ..............................................................97
4.3.3 DRAM I/O Power Management ................................................................. 97
4.4 DMI2/PCI Express* Power Management ...............................................................97
5 Thermal Management Specifications........................................................................ 98
5.1 Package Thermal Specifications........................................................................... 98
5.1.1 Thermal Specifications............................................................................98
5.1.2 TCASE and DTS Based Thermal Specifications.......................................... 100
5.1.3 Processor Operational Thermal Specifications........................................... 101
5.1.3.1 Minimum operating case temperature........................................ 101
5.1.3.2 Maximum operating case temperature thermal profiles ................ 101
5.1.3.3 Digital Thermal Sensor (DTS) thermal profiles ............................ 102
5.1.3.4 Processor Digital Thermal Sensor (DTS) Specifications................. 103
5.1.4 Embedded Server Thermal Profiles ......................................................... 104
5.1.4.1 Embedded operating case temperature thermal profiles ............... 104
5.1.4.2 Embedded Digital Thermal Sensor (DTS) thermal profiles............. 105
5.1.5 Thermal Metrology ............................................................................... 107
5.2 Processor Core Thermal Features....................................................................... 109
5.2.1 Processor Temperature ......................................................................... 109
5.2.2 Adaptive Thermal Monitor...................................................................... 109
5.2.2.1 Frequency/SVID Control .......................................................... 110
5.2.2.2 Clock Modulation .................................................................... 111
5.2.3 On-Demand Mode ................................................................................ 111
5.2.4 PROCHOT_N Signal .............................................................................. 112
5.2.5 THERMTRIP_N Signal............................................................................ 112
5.2.6 Integrated Memory Controller (IMC) Thermal Features .............................. 113
5.2.6.1 DRAM Throttling Options.......................................................... 113
5.2.6.2 Hybrid Closed Loop Thermal Throttling (CLTT_Hybrid) ................. 113
5.2.6.3 MEM_HOT_C1_N and MEM_HOT_C23_N Signal........................... 113
5.2.6.4 Integrated SMBus Master Controllers for Memory Interface........... 114
6 Signal Descriptions................................................................................................ 115
6.1 System Memory Interface Signals...................................................................... 115
6.2 PCI Express* Based Interface Signals................................................................. 116
6.3 DMI2/PCI Express* Port 0 Signals ..................................................................... 117
6.4 Intel® QuickPath Interconnect Signals ............................................................... 118
6.5 PECI Signal .................................................................................................... 118
6.6 System Reference Clock Signals........................................................................ 118
6.7 JTAG and TAP Signals ...................................................................................... 119
6.8 Serial VID Interface (SVID) Signals.................................................................... 119
6.9 Processor Asynchronous Sideband and Miscellaneous Signals ................................ 119
6.10 Processor Power and Ground Supplies................................................................ 123
7 Electrical Specifications......................................................................................... 124