Electronics America Network Cables User Manual

APPENDIX A MIPS III INSTRUCTION SET DETAILS
468
Preliminary User’s Manual S15543EJ1V0UM
CACHE
Cache (4/4)
CACHE
Operation:
32, 64 T:
vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR [base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
CacheOp (op, vAddr, pAddr)
Exceptions:
Coprocessor unusable exception
TLB Refill exception
TLB Invalid exception
Bus Error exception
Address Error exception
Cache Error exception