DATA SHEET MOS INTEGRATED CIRCUIT µPD17062 4-BIT SINGLE-CHIP MICROCONTROLLER CONTAINING PLL FREQUENCY SYNTHESIZER AND IMAGE DISPLAY CONTROLLER The µPD17062 is a 4-bit CMOS microcontroller for digital tuning systems. The single-chip device incorporates an image display controller enabling a range of different displays, together with a PLL frequency synthesizer.
µPD17062 ORDERING INFORMATION Part number Package µPD17062CU-××× 48-pin plastic shrink DIP (600 mil) µPD17062GC-××× 64-pin plastic QFP (14 × 14 mm) Remark ××× is the ROM code number.
µPD17062 PIN CONFIGURATION (TOP VIEW) 48-pin plastic shrink DIP (600 mil) 1 48 INTNC P0C2 2 47 P0A0/SDA P0C1 3 46 P0A1/SCL P0C0 4 45 P0A2/SCK P0D3/ADC5 5 44 P0A3/SO P0D2/ADC4 6 43 P0B0/SI P0D1/ADC3 7 42 P0B1 P0D0/ADC2 8 41 P0B2/TMIN PWM3 9 40 P0B3/HSCNT PWM2 10 39 ADC0 PWM1 11 38 P1C1 PWM0 12 37 P1C2 VDD 13 36 P1C3/ADC1 VCO 14 35 VSYNC µ PD17062CU-××× ADC0 to ADC5 P0C3 EO 15 34 HSYNC GND 16 33 BLANK PSC 17 32 BLUE CE 18 31 GREEN XOUT
µPD17062 P0D1/ADC3 P0D2/ADC4 P0D3/ADC5 P0C0 P0C1 P0C2 P0C3 NC NC INTNC P0A0/SDA P0A1/SCL P0A1/SCK P0A3/SO P0B0/SI P0B1 64-pin plastic QFP (14 × 14 mm) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P0D0/ADC2 1 48 POB2/TMIN PWM3 2 47 POB3/HSCNT PWM2 3 46 ADC0 PWM1 4 45 P1C1 NC 5 44 NC PWM0 6 43 P1C2 NC 7 42 NC NC 8 41 NC VDD 9 40 NC NC 10 39 NC VCO 11 38 P1C3/ADC1 NC 12 37 NC EO 13 36 VSYNC NC 14 35 HSYNC GND 15 34
µPD17062 BLOCK DIAGRAM VCO PSC PLL EO HSYNC PWM0 VSYNC PWM1 PWM RED IDC PWM2 PWM3 GREEN RF BLUE P1A0 RAM 336 × 4 bits (Including VRAM) BLANK P1A1 P1A SYSREG P0A0/SDA P1A2 P1A3 P0A1/SCL P0A2/SCK Serial I/O P1B0 P0A3/SO P1B1 P1B ALU P0B0/SI P1B2 P1B3 P0A P0C0 P0C1 P0B1 P0C P0B P0B2/TMIN P0B3/HSCNT Hsync Counter P0C2 P0C3 ROM 3968 × 16 bits (Including CROM) Interrupt Controller Timer Controller INTNC Instruction Decoder P0D0/ADC2 Program Counter P0D1/ADC3 P0D2/ADC4 CPU
µPD17062 CONTENTS 1. 2. PINS ............................................................................................................................................. 11 1.1 PIN FUNCTIONS ............................................................................................................................. 11 1.2 EQUIVALENT CIRCUITS OF THE PINS ........................................................................................ 14 PROGRAM MEMORY (ROM) ...............................
µPD17062 9. 8.5 INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MP) ...................... 57 8.6 GENERAL-PURPOSE REGISTER POINTER (RP) .......................................................................... 66 8.7 PROGRAM STATUS WORD (PSWORD) ...................................................................................... 66 REGISTER FILE (RF) ................................................................................................................... 67 9.
µPD17062 11.5 RETURNING CONTROL FROM INTERRUPT PROCESSING ROUTINE ..................................... 116 11.6 INTERRUPT PROCESSING ROUTINE ........................................................................................... 117 11.7 EXTERNAL INTERRUPTS (INTNC PIN, VSYNC PIN) ....................................................................... 121 11.8 INTERNAL INTERRUPT (TIMER, SERIAL INTERFACE) .............................................................. 123 11.
µPD17062 17. D/A CONVERTER ....................................................................................................................... 217 17.1 PWM PINS ....................................................................................................................................... 217 18. PLL FREQUENCY SYNTHESIZER ............................................................................................. 219 18.1 PLL FREQUENCY SYNTHESIZER CONFIGURATION ...............................
µPD17062 23.5 PERIPHERAL HARDWARE REGISTER .......................................................................................... 286 23.6 OTHERS ........................................................................................................................................... 286 24. ELECTRICAL CHARACTERISTICS ............................................................................................. 287 25. PACKAGE DRAWINGS ................................................................
µPD17062 1. PINS 1.1 PIN FUNCTIONS Pin No. DIP QFP (GC) Description Output type At power-on reset CMOS push-pull Undefined — Input Output of a 6-bit D/A converter. The output type is PWM. Output is done at a frequency of 15.625 kHz. The pin can also be used as a one-bit output port. N-ch open drain Undefined Supplies the power to the device. To enable all functions, 5 V ±10% is supplied. To operate only the CPU, 4 V is required. In the clock-stop state, the voltage can be reduced to 3.5 V.
µPD17062 Pin No. DIP QFP (GC) Symbol Description Output type At power-on reset 4-bit output port. This N-ch open-drain output port has an intermediate withstand voltage. N-ch open-drain Undefined 4-bit I/O port. Each bit can be set for input or output. CMOS push-pull Input Outputs the character data corresponding to R, G, and B of the IDC display. The output is activehigh. CMOS push-pull Low level Outputs the blanking signal for cutting the video signal of the IDC display.
µPD17062 Pin No. DIP QFP (GC) Symbol Description Output type At power-on reset — Input 48 55 INTNC Interrupt input. Contains the noise canceler. An interrupt can be generated at either the rising or falling edge of the input signal. — 5 NC No connection. The pins are not connected to the internal circuit of the device. They can be used as desired.
µPD17062 1.
µPD17062 P0C (P0C3, P0C2, P0C1, P0C0) RED, GREEN, BLUE, BLANK, PSC (Output) PWM (PWM3, PWM2, PWM1, PWM0) P1A (P1A3, P1A2, P1A1, P1A0) (Output) P0D (P0D3/ADC5, P0D2/ADC4, P0D1/ADC3, P0D0/ADC2) A/D Converter (Input) High on-state resistance ADC0 A/D converter selection signal 15
µPD17062 P0B3/HSCNT Port P-ch Horizontal synchronizing signal counter N-ch P0B2/TMIN Port P-ch Timer/counter N-ch 16
µPD17062 HSYNC, VSYNC, INTNC, CE (Hysteresis input) XOUT, XIN XIN XOUT EO VCO (Input) 17
µPD17062 2. PROGRAM MEMORY (ROM) Program memory stores the program to be executed by the CPU, as well as predetermined constant data. 2.1 CONFIGURATION OF PROGRAM MEMORY Fig. 2-1 shows the configuration of program memory. As shown in Fig. 2-1, the capacity of the program memory is 8K bytes (3968 × 16 bits). Locations in program memory are addressed in units of 16 bits. The total address range is from 0000H to 0F7FH. Memory is divided into pages.
µPD17062 2.2 FUNCTIONS OF PROGRAM MEMORY Program memory has two basic functions: (1) Program storage (2) Constant data storage A program is a set of instructions that control the CPU (Central Processing Unit: Device that actually controls the microcontroller). The CPU executes processing sequentially according to the instructions coded in the program. The CPU sequentially reads instructions from the program stored in program memory and executes processing according to each instruction.
µPD17062 2.4 BRANCHING A PROGRAM A program is branched by execution of the branch instruction (BR). Fig. 2-2 illustrates the operation of the branch instruction. Branch instructions (BR) are divided into two types. Direct branch instructions (BR addr) transfer control to a program memory address (addr) directly specified in its operand. Indirect branch instructions (BR @AR) transfer control to a program memory address specified in an address register (AR), described below. See also Chapter 3. 2.4.
µPD17062 Fig.
µPD17062 2.5 SUBROUTINE If a subroutine is executed, the specialized subroutine call instruction (CALL) and subroutine return instruction (RET, RETSK) are used. Fig. 2-3 illustrates the operation of subroutine call. Subroutine call instructions are divided into two types. The direct subroutine call instruction (CALL addr) calls the program memory address (addr) specified in its operand. The indirect subroutine call instruction (CALL @AR) calls the program memory address specified in an address register.
µPD17062 Fig. 2-3 Operation of Subroutine Call Instruction (a) Direct subroutine call (CALL addr) Address Program memory 0000H Label: Instruction CALL SUB1 (b) Indirect subroutine call (CALL @AR) Address 0000H Label: 0010H 0085H 0500H Program memory Instruction SUB2: SUB3: SUB1: RET MOV AR0, #0H MOV AR1, #1H CALL @AR RET Page 0 07FFH 0800H Page 0 07FFH 0800H CALL SUB1 Page 1 0F7FH MOV AR0, #5H MOV AR1, #8H CALL @AR Page 1 0F7FH Fig.
µPD17062 2.6 TABLE REFERENCE The table reference instruction is used to reference the constant data in program memory. If the MOVT DBF, @AR instruction is executed, data at the program memory address specified in an address register is placed in a data buffer (DBF). Because each data item in program memory consists of 16 bits, the constant data placed in the data buffer by the MOVT instruction also consists of 16 bits (four words).
µPD17062 3. PROGRAM COUNTER (PC) The program counter addresses program memory or a program. It is a 12-bit binary counter. Fig. 3-1 PC11 PC10 PC9 PC8 PC7 Program Counter PC6 PC5 PC4 PC3 PC2 PC1 PC0 12 bits Normally, the program counter is incremented by 1 each time an instruction is executed. When a branch instruction or a subroutine call instruction is executed, however, the address specified in the operand field is loaded into the program counter.
µPD17062 4. STACK The stack is a register used to save an address returned by a program or the contents of the system register, described later, when a subroutine call occurs or an interrupt is accepted. 4.1 COMPONENTS The stack consists of a stack pointer (SP), which is a 4-bit binary counter, six 13-bit address stack registers (ASRs), and two 3-bit interrupt stack registers. 4.
µPD17062 4.3 ADDRESS STACK REGISTERS (ASRs) There are six address stack registers, each consisting of 13 bits. After a subroutine call instruction has been executed or an interrupt request accepted, the contents of the address stack register will contain a value that is equal to the contents of the program counter, plus one, or the return address.
µPD17062 Fig. 4-3 Structure of Interrupt Stack Registers MSB 0H BANKSK0 IXESK0 1H BANKSK1 IXESK1 Fig. 4-4 Behavior of Interrupt Stack Registers Not defined A B A Not defined Not defined Not defined A Not defined Not defined VDD is applied.
µPD17062 5. DATA MEMORY (RAM) Data memory is used to store data for operations and control. Simply by executing an appropriate instruction, data can be written to and read from data memory at any time. 5.1 STRUCTURE OF DATA MEMORY Fig. 5-1 shows the structure of data memory. As shown in Fig. 5-1, data memory is divided into three units called banks. These three banks are called BANK0, BANK1, and BANK2. In each bank, data is assigned an address in units of four bits.
µPD17062 Fig.
µPD17062 5.1.1 Structure of the System Register (SYSREG) The system register consists of 12 nibbles, located at addresses 74H to 7FH in data memory. The system register is allocated regardless of the bank. That is, the system register is always located at addresses 74H to 7FH, regardless of the bank. Fig. 5-2 shows the structure. Fig. 5-2 Structure of the System Register System register (SYSREG) Address Register (symbol) 5.1.
µPD17062 5.1.3 Structure of the General-Purpose Register (GR) The general-purpose register consists of 12 nibbles, specified with an arbitrary row address, in data memory. An arbitrary row address is specified using the general-purpose register pointer in the system register. Fig. 5-4 shows the structure. Fig.
µPD17062 5.1.4 Structure of Port Data Registers (port register) The port registers consist of 12 nibbles at addresses 70H to 73H of the banks of data memory. Fig. 5-5 shows the structure of the port registers. As shown in Fig. 5-5, the same port registers are allocated in BANK0 and BANK2. Thus, the port registers actually consist of eight nibbles. Fig. 5-5 Structure of Port Registers Port register Address Symbol BANK0 BANK2 BANK1 5.1.
µPD17062 5.2 FUNCTIONS OF DATA MEMORY Data memory can be used to perform, with one instruction, a four-bit operation, comparison, decision, or transfer of the data in data memory and immediate data (arbitrary data) by executing one of the data memory manipulation instructions listed in Table 5-1. If the general-purpose register is used, a four-bit operation, comparison, or transfer between data memory and the general-purpose register can be performed by a single instruction. Examples are given below.
µPD17062 5.2.1 Function of System Register (SYSREG) The system register is used to control the CPU. For example, the bank register shown in Fig. 5-2 is used to specify a data memory bank, while the generalpurpose register pointer specifies the row address of the general-purpose register. See Chapter 8 for details. 5.2.2 Function of General-Purpose Register (GR) The general-purpose register can be used both to perform operations on the data in data memory and to transfer data to and from data memory.
µPD17062 Table 5-1 Data Memory Manipulation Instructions Function Instruction ADD Addition Operation Subtraction ADDC SUB SUBC Logical operation AND OR XOR SKE SKGE Comparison SKLT SKNE MOV Transfer LD ST Decision SKT SKF 36
µPD17062 Fig.
µPD17062 5.3 5.3.1 NOTES ON USING DATA MEMORY Addressing Data Memory If the 17K series assembler is being used and a numeric representing a data memory address is specified directly in an operand of a data memory manipulation instruction, as shown in example 1, an error will occur. This error occurs to facilitate the maintainability of programs and to reduce the number of causes of bugs when a program is modified.
µPD17062 Example 2. M1 MEM 0.15H ; M2 MEM 1.15H ; M3 MEM 2.15H ; Bank Row address BANK1 5.3.2 Symbol definition pseudo instruction Column address ; Assembler built-in macro instruction BANK ← 1 # for different MOV M1, #0000B ; M1, M2, and M3 are defined symbolically in MOV M2, #0000B ; banks, but are for BANK1 in this program. Thus, all of these MOV M3, #0000B ; three instructions write 0s to data memory address 15H in BANK1.
µPD17062 6. GENERAL-PURPOSE REGISTER (GR) The general-purpose register is allocated in data memory space, and is used to perform direct operations on the data in data memory and to transfer data to and from data memory. 6.1 STRUCTURE OF THE GENERAL-PURPOSE REGISTER Fig. 6-1 shows the structure of the general-purpose register. As shown in Fig. 6-1, 16 words (16 words × 4 bits) having the same row address in data memory space can be used as the general-purpose register.
µPD17062 Fig. 6-1 Structure of General-Purpose Register Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Row addresses 0H to 7H of BANK0 can be freely specified using the generalpurpose register pointer (RP). Row address 1 2 General-purpose register allocated when RP = 010B. General-purpose register (16 words) 3 4 BANK0 5 6 7 System register RP 0 1 2 3 BANK1 4 5 6 7 General-purpose register pointer (RP) Symbol RPH RPL Address 7DH 7EH Bit Function The same system register is viewed.
µPD17062 6.3 ADDRESS GENERATION FOR GENERAL-PURPOSE REGISTER AND DATA MEMORY IN INDIVIDUAL INSTRUCTIONS Table 6-1 lists the operation and transfer instructions that can be executed for the data in the generalpurpose register and data memory. Consider the following instruction: ADD r, m ((r) ← (r) + (m)) Upon executing this instruction, the address of the general-purpose register is generated from the value of the general-purpose register pointer and the value specified in r, as shown in Table 6-2.
µPD17062 Example 1. When BANK0 is selected AND RPL, #0001B ; RP ← 0000000B; The general-purpose register is allocated in row ADD 04H, 56H ; ; address 0H in BANK0. Executing the above instruction adds the contents of address 04H of BANK0, part of the general-purpose register, to the contents of data memory address 56H, then stores the result into address 04H of the generalpurpose register. See Fig. 6-2. Fig.
µPD17062 Example 2. When BANK0 is selected and MPE = 0 is specified MOV 04H, #8 ; 04H ← 8 AND RPL, #0001B ; RP ← 0000000B; The general-purpose register is allocated in row ; address 0H in BANK0. MOV @04H, 52H Executing the above instruction transfers the contents of data memory address 52H to address 58H. The MOV @r, m instruction is called an indirect transfer of the general-purpose register contents.
µPD17062 Example 3 shows a program that transfers eight words of data from BANK2 to BANK0 data memory in units of four words, as shown in Fig. 6-4. If the general-purpose register is allocated in a fixed row address, for example, only in row address 0 of BANK0, instructions are needed to transfer all of the eight words to the register and then store them into data memory.
µPD17062 6.4 NOTES ON USING THE GENERAL-PURPOSE REGISTER This section provides notes on using the general-purpose register, referring to the following example: Example AND RPL, #000B ; RP ← 0000010B OR RPL, #0100B ; MOV BANK, #0000B LD ; BANK0 04H, 32H Executing the above instructions loads the contents of address 32H of BANK0 data memory into address 24H in the general-purpose register of BANK0.
µPD17062 Fig. 6-5 Execution of the Above Example Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Row address 1 2 General-purpose register 3 RP = 0000010B BANK0 4 5 LD 04H, 32H 6 7 System register RP Also, note the following when the general-purpose register is being used. No arithmetic/logical instructions are provided for the general-purpose register and immediate data.
µPD17062 7. ARITHMETIC LOGIC UNIT (ALU) BLOCK 7.1 OVERVIEW Fig. 7-1 is an overview of the ALU block. As shown in Fig. 7-1, the ALU block consists of the ALU, temporary storage registers A and B, program status word, decimal conversion circuit, and data memory address controller. The ALU performs arithmetic and logic operations on the 4-bit data in the data memory and performs discrimination, comparison, rotation, and transfer. Fig.
µPD17062 7.2 7.2.1 CONFIGURATION AND FUNCTIONS OF THE COMPONENTS OF THE ALU BLOCK ALU In response to a programmed instruction, the ALU performs 4-bit arithmetic or logic processing, bit discrimination, comparative discrimination, rotation, or transfer. 7.2.2 Temporary Storage Registers A and B Temporary storage registers A and B temporarily hold the 4-bit data. These registers are automatically used when an instruction is executed. They cannot be controlled by a program. 7.2.
µPD17062 ALU function Table 7-1 Operation difference due to program status word (PSWORD) Instruction Value Value of the of the BCD flag CMP flag Addition r, m ADD m, #n4 0 0 1 r, m SUB 1 0 1 1 m, #n4 r, m SUBC m, #n4 Operation Operation of the CY flag The result is stored. Binary operation The result is not stored. Decimal operation The result is stored. Operation of the Z flag Address modification Index Memory pointer Set if the operation result is 0000B.
µPD17062 Table 7-2 Modification of the Data Memory Address and Indirect Transfer Address by the Index Register and Data Memory Row Address Pointer General-purpose register address specified with r IXE MPE Row address Bank Data memory address specified with m Column address Row address Bank Column address Indirect transfer address specified with @r Row address Bank Column address b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 RP r 0 0 0 1
µPD17062 Table 7-3 Operation Hexadecimal addiresult tion Converted Decimal Data Decimal addition CY Operation result CY Operation result 0 0 0000B 0 0000B 1 0 0001B 0 2 0 0010B 3 0 4 Operation Hexadecimal subtrac- Decimal subtraction result tion CY Operation result CY Operation result 0 0 0000B 0 0000B 0001B 1 0 0001B 0 0001B 0 0010B 2 0 0010B 0 0010B 0011B 0 0011B 3 0 0011B 0 0011B 0 0100B 0 0100B 4 0 0100B 0 0100B 5 0 0101B 0 0101B 5 0 0
µPD17062 7.4 NOTES ON USING THE ALU 7.4.1 Notes on Using the Program Status Word for Operations After an arithmetic operation has been performed on the program status word, the operation result is held in the program status word. The CY and Z flags of the program status word are usually set or reset according to the result of the arithmetic operation.
µPD17062 8. SYSTEM REGISTER (SYSREG) “System register” is the generic name for those registers directly related to CPU control. System registers are allocated at addresses 74H-7FH in data memory and can be referenced regardless of the bank specification. The system register types are as follows: Address register Window register Bank register Memory pointer enable flag Index register Data memory row address pointer General-purpose register pointer Program status word Fig.
µPD17062 8.1 ADDRESS REGISTER (AR) The address register specifies a program memory address. It is located at addresses 74H-77H. The instructions used to manipulate the address register are indirect branch instructions (BR @AR, CALL @AR), the table reference instruction (MOVT), and stack manipulation instructions (PUSH, POP). An indirect branch is a branch to the program memory address specified by the contents of the address register. Indirect branch instructions include BR @AR and CALL @AR.
µPD17062 8.3 BANK REGISTER (BANK) The bank register specifies a data memory bank. The bank register contains BANK0 upon reset. The two high-order bits of address 79H are consistently set to 0. Data memory is classified into three banks by the bank register. When a data memory manipulation instruction is executed, it acts on the data memory in the bank specified by the bank register.
µPD17062 8.5 8.5.1 INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MP) Configuration of Index Register and Data Memory Row Address Pointer As shown in Fig. 8-1, the index register consists of 11 bits, including the three low-order bits, of 7AH (IXH) of the system register, 7BH, and 7CH (IXM, IXL). The index register is used to indirectly specify a data memory address. The data memory row address pointer consists of 7 bits, including the three low-order bits of 7AH (MPH) and 7BH (MPL).
µPD17062 8.5.2 Functions of Index Register and Data Memory Row Address Pointer When a data memory manipulation instruction is executed with the index enable flag (IXE) set to 1, the index register ORs the data memory bank/address specified by the instruction and the contents of the index register. Then, the index register executes the instruction in the data memory address indicated by the operation result (in other words, the real address).
µPD17062 Table 8-2 Modification of Data Memory Address by Index Register and Data Memory Row Address Pointer General-purpose register address specified by r R IXE MPE Bank Row address Column address Data memory address specified by m Indirect transfer address specified by @r M @R Row address Bank Column address Bank Row address Column address b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 0 0 0 1 1 0 (RP) r (BANK) m Same as above
µPD17062 8.5.3 For MPE = 0 and IXE = 0 (Data Memory Not Modified) As shown in Table 8-2, data memory addresses are not affected by the index register or data memory row address pointer. Example 1. When the row address of the general-purpose register is 0 for BANK0 ADD 03H, 11H When the above instruction is executed, the contents of general-purpose register 03H and data memory 11H are added and the result is stored in general-purpose register 03H. (See Example 1 in Fig. 8-3). Example 2.
µPD17062 Fig. 8-3 Indirect Transfer of General-Purpose Register with MPE = 0 and IXE = 0 Column address 0 1 2 3 4 0 Example 1. ADD03H,11H Row address 1 5 6 7 8 9 8 Specifies the destination column address A B C D E E Specifies the source column address Example 2. MOV @05H, 34H F Generalpurpose register 2 3 Example 3.
µPD17062 8.5.4 For MPE = 1 and IXE = 0 (Diagonal Indirect Transfer) As shown in Table 8-2, the bank and row address of the data memory address in the indirect side specified by the general-purpose register are set to the value of the data memory row address pointer only when a general-purpose register indirect transfer instruction is executed. Example 1.
µPD17062 Fig. 8-4 Indirect Transfer of General-Purpose Register with MPE = 1 and IXE = 0 Column address Generalpurpose register 0 1 2 3 4 5 6 8 0 7 8 9 A C D E F E Specifies the destination column address 1 B Specifies the source column address Example 1. MOV @05H, 34H 2 Example 2. MOV 3AH, @0BH 3 4 5 6 7 The bank and row address are set to 000101B, the value of the data memory row address pointer.
µPD17062 8.5.5 For MPE = 0 and IXE = 1 (Index Modification) As shown in Table 8-2, when a data memory manipulation instruction is executed, the bank and row address of the data memory specified directly by the instruction are ORed with the index register. Then, the instruction is executed in the data memory address specified by the operation result (real address). Example 1.
µPD17062 Fig.
µPD17062 8.6 GENERAL-PURPOSE REGISTER POINTER (RP) The general-purpose register pointer points to the bank and row address of the general-purpose register. However, since RPH of the µPD17062 is fixed at 0, only RPL (3 bits) can be specified. This means that 0 to 7 can be specified as a register pointer. Hence, in the µPD17062, the row address of the general-purpose register can be specified anywhere within BANK0. 8.
µPD17062 9. REGISTER FILE (RF) The register file is a group of registers that mainly control the CPU peripheral circuits. The register file has a capacity of 128 words × 4 bits. However, peripheral circuit addresses are actually allocated to the high-order 64 nibbles (00H-3FH) and addresses 40H-7FH of the currently selected bank of data memory to the low-order 64 nibbles (40H-7FH).
µPD17062 Fig.
µPD17062 Fig.
µPD17062 Peripheral hardware Table 9-1 Peripheral Hardware Control Functions of Control Registers (1/5) Control register Register Peripheral hardware control function b3 b2 Symbol AdRead/ dress write b1 b0 Stack 0 Stack pointer (SP) At reset Set value Function outline 0 1 S C T E O P 7 7 7 0 0 * 0 1 1 0 0 0 0 0 0 Fixed at 0 (SP2) 01H P o w e r O n R/W (SP1) Stack pointer (3 bits are valid.
µPD17062 Peripheral hardware Table 9-1 Peripheral Hardware Control Functions of Control Registers (2/5) Control register Register Peripheral hardware control function b3 b2 AdRead/ Symbol dress write b1 b0 0 Interrupt edge select register 1FH IEGVSYN R/W 0 IEGNC Set value Function outline 0 Interrupt IPVSYN 2FH R/W IPBTM0 IPNC Sets the interrupt issue edge (VSYNC) IRQVSYN 3FH R IRQBTM0 IRQNC Rising edge Falling edge Fixed at 0 Sets the interrupt issue edge (INTNC) Rising edge Falling
µPD17062 A/D converter Peripheral hardware Table 9-1 Peripheral Hardware Control Functions of Control Registers (3/5) Control register Register Peripheral hardware control function b3 b2 AdRead/ Symbol dress write b1 b0 Set value Function outline 0 ADCCH2 A/D converter controll register ADCCH1 21H R/W Selects the pin used as an A/D converter ADCCH0 ADCCMP At reset 1 0: AD0 2: AD2 4: AD4 6, 7: Not to be set Detects the comparison result VIN < VREF 1: AD1 3: AD3 5: AD5 VIN > VREF P o w e
µPD17062 Peripheral hardware Table 9-1 Peripheral Hardware Control Functions of Control Registers (4/5) Control register Register Peripheral hardware control function b3 b2 AdRead/ Symbol dress write b1 b0 Serial I/O0 status judge register Detects the contents of clock counter 28H R SIO0SF9 SBSTT Serial interface SBBSY Detects the number of clocks (I2C bus method) Detects the start condition (I2C bus method) P o w e r O n Set value Function outline SIO0SF8 At reset 0 1 Resets when the
µPD17062 Peripheral hardware Table 9-1 Peripheral Hardware Control Functions of Control Registers (5/5) Control register Register Peripheral hardware control function b3 b2 AdRead/ Symbol dress write b1 b0 At reset Set value Function outline 0 1 P o w e r O n S C T E O P 0 0 0 0 0 0 0 0 0 0 Fixed at 0 IDC DMA enable register 0 00H R/W IDCDMAEN 0 Sets the DMA mode permission Not permitted Permitted BANK0 (0800H-0BFFH) BANK1 (0C00H-0F7FH) Fixed at 0 IDC 0 0 IDC CROM bank regi
µPD17062 9.1 IDCDMAEN (00H, b1) This flag must be set to enable the operation of IDC. When the IDCDMAEN flag is set, the mode changes to DMA mode and IDC is enabled. In DMA mode, the instruction cycle is seen as 12 µs. For details, see Chapter 20. 00H 9.2 b3 b2 b1 b0 0 0 IDCDMAEN 0 0 DMA prohibited mode (instruction cycle = 2 µ s) 1 DMA mode (instruction cycle = 12 µ s) SP (01H) SP is a pointer that addresses the stack register.
µPD17062 9.3 CE (07H, b0) CE is a flag for reading the CE pin level. The flag indicates 1 when a high level signal is input to the CE pin, or 0 when a low level signal is input. 07H 9.
µPD17062 9.5 BTM0MD (09H) 09H b3 b2 b1 b0 BTM0ZX BTM0CK2 BTM0CK1 BTM0CK0 Time base setting TIMER INT TIMER CARRY 0 0 0 5 ms Internal 100 ms Internal 0 0 1 100 ms Internal 5 ms Internal 0 1 0 20 ms Internal 100 ms Internal 0 1 1 20 ms Internal 5 ms Internal 1 0 0 5 ms Internal 5/fTMR s External 1 0 1 5/fTMR s External 5 ms Internal 1 1 0 5 ms Internal 6/fTMR s External 1 1 1 6/fTMR s External 5 ms Internal Zerocross setting 9.
µPD17062 9.7 INTNC (0FH, b0) The INTNC flag is used for reading the INTNC pin state. The flag indicates 1 when a high level signal is input to the INTNC pin, and 0 when a low level signal is input to the INTNC pin. 0FH 9.8 b3 b2 b1 b0 0 INTVSYN 0 INTNC 0 The INTNC pin is low level. 1 The INTNC pin is high level. 0 The VSYNC pin is low level. 1 The VSYNC pin is in the high level period.
µPD17062 9.9 PLL REFERENCE MODE SELECTION REGISTER (13H) 13H b3 b2 b1 b0 PLLRFCK3 PLLRFCK2 PLLRFCK1 PLLRFCK0 Reference frequency fr setting 0 0 1 0 6.25 kHz 0 0 1 1 12.5 kHz 0 1 1 0 25 kHz 1 1 1 1 PLL disabled 0 1 1 1 1 0 1 0 1 0 1 1 1 1 1 0 Not to be set Fixed at 1 9.
µPD17062 9.11 TIMER CARRY (17H) 17H b3 b2 b1 b0 0 0 0 BTM0CY Exclusive flag for reading timer carry This flag is set according to the selected time base, and reset when the timer carry is read. 9.
µPD17062 9.14 A/D CONVERTOR CONTROL (21H) 21H b3 b2 b1 b0 ADCCH2 ADCCH1 ADCCH0 ADCCMP A/D converter input channel select 9.
µPD17062 9.16 PORT1C I/O SETTING (27H) 27H b3 b2 b1 b0 0 0 0 P1CGIO P1C port I/O setting 9.
µPD17062 9.18 INTERRUPT PERMISSION FLAG (2FH) This flag is used to enable interrupt for each interrupt cause. When the flag is set to 1, interrupt is enabled. When the flag is set to 0, interrupt is disabled. 2FH 9.
µPD17062 9.20 IDCEN (31H) 31H 9.21 b3 b2 b1 b0 0 0 0 IDCEN 0 IDC operation prohibited (display off) 1 IDC operation start (display on) PLL UNLOCK FLIP-FLOP DELAY CONTROL REGISTER (32H) 32H b3 b2 b1 b0 PLULSEN3 PLULSEN2 PLULSEN1 PLULSEN0 Setting of the delay time of the reference frequency fr and divided frequency fN required for setting the unlock flip-flop 0 0 1.25 to 1.5 µ s or more 0 1 3.5 to 3.75 µ s or more 1 0 0.25 to 0.
µPD17062 9.22 P1BBIOn (35H) P1BBIOn specifies the PORT1B I/O. When P1BBIOn is set to 0, PORT1B becomes an input port. When P1BBIOn is set to 1, PORT1B becomes an output port. 35H b3 b2 b1 b0 P1BBIO3 P1BBIO2 P1BBIO1 P1BBIO0 P1B0 I/O setting 0 P1B0 input port 1 P1B0 output port P1B1 I/O setting 0 P1B1 input port 1 P1B1 output port P1B2 I/O setting 0 P1B2 input port 1 P1B2 output port P1B3 I/O setting 9.
µPD17062 9.24 P0ABIOn (37H) P0ABIOn specifies the PORT0A I/O. When P0ABIOn is set to 0, PORT0A becomes an input port. When P0ABIOn is set to 1, PORT0A becomes an output port. 37H b3 b2 b1 b0 P0ABIO3 P0ABIO2 P0ABIO1 P0ABIO0 P0A0 I/O setting 0 P0A0 input port 1 P0A0 output port P0A1 I/O setting 0 P0A1 input port 1 P0A1 output port P0A2 I/O setting 0 P0A2 input port 1 P0A2 output port P0A3 I/O setting 9.
µPD17062 9.26 SHIFT CLOCK FREQUENCY SETTING (39H) 39H b3 b2 b1 b0 SIO0CK3 SIO0CK2 SIO0CK1 SIO0CK0 Internal clock frequency 0 0 100 kHz 0 1 200 kHz 1 0 500 kHz 1 1 1 MHz Fixed at 0 9.27 IRQNC (3FH) IRQNC is an interrupt request flag that indicates the interrupt request state. When an interrupt request is generated, the flag is set to 1. When the request is accepted (interrupt is made), the flag is reset to 0. The interrupt request flag can be read and written by the program.
µPD17062 10. DATA BUFFER (DBF) The data buffer is used to transfer data to and from peripheral hardware and to reference tables. 10.1 10.1.1 DATA BUFFER STRUCTURE Mapping of Data Buffer to Data Memory Fig. 10-1 shows how the data buffer is mapped to data memory. As shown in Fig. 10-1, the data buffer is allocated to addresses 0CH to 0FH of data memory BANK0 and consists of 16 bits in a 4-word × 4-bit configuration.
µPD17062 10.1.2 Data Buffer Structure Fig. 10-2 shows the data buffer structure. As shown in Fig. 10-2, the data buffer consists of 16 bits. Bit b0 of data memory address 0FH is the LSB, and bit b3 of data memory address 0CH bit 3 is the MSB. Fig.
µPD17062 10.2 FUNCTIONS OF DATA BUFFER The data buffer provides the following two functions: (1) Read constant data in program memory (to reference tables) (2) Transfer data to and from peripheral hardware Fig. 10-3 shows the relationship between the data buffer, peripheral hardware, and memory. Table referencing is described in Section 10.3, and the peripheral hardware is described in Sections 10.4 to 10.6. Fig.
µPD17062 10.3 DATA BUFFER AND TABLE REFERENCING 10.3.1 Table Referencing Tables are referenced by reading the constant data from program memory into the data buffer. This is done using the MOVT DBF, @AR instruction. Therefore, if display data or other constant data is written to program memory in advance and a table reference instruction is executed, writing of a complex data conversion program is unnecessary. The MOVT instruction is described below. A example program is given in Section 10.3.2.
µPD17062 10.3.2 Example Table Referencing Program This section shows an example table referencing program. Example P0A MEM 0.70H ; P0B MEM 0.71H ; P0C MEM 0.
µPD17062 This program sequentially reads the constant data stored at program memory addresses 0001H to 000CH into the data buffer ( #) and outputs the data to Port0A, Port0B, and Port0C ($). The constant data is left-shifted one bit. As a result, a high-level data is sequentially output to the Port0A, Port0B, and Port0C pins. 10.4 DATA BUFFER AND PERIPHERAL HARDWARE 10.4.
µPD17062 Table 10-1 Peripheral Hardware and Data Buffer Functions Data buffer and data transfer peripheral register Peripheral hardware Name Symbol Function PeriPUT pheral instruction/ address GET instruction Data buffer I/O bits Valid bits Explanation Image display controller IDC start posi- IDCORG tion setting register 01H PUT/GET 8 7 Sets the image display controller display start position.
µPD17062 10.4.2 Precautions When Transferring Data With Peripheral Registers Data is transferred between the data buffer and peripheral registers in 8-bit or 16-bit units. A PUT or GET instruction is executed for one instruction cycle (2 µs) even if the data is 16 bits long. When 8-bit data transfer is performed but the peripheral register execution data is seven bits, for example, long one extra bit is added. At data write, the status of this extra data is “Don’t care” as shown in Example 1.
µPD17062 Example 2. GET instruction Data buffer DBF3 b15 b14 b13 Don't care DBF2 b12 b11 b10 DBF1 b9 b8 b7 b6 DBF0 b5 b4 b3 b2 b1 b0 Don't care GET 8 0 or unpredictable The value of the peripheral register is read without alteration. Peripheral register b7 b6 b5 b4 b3 b2 b1 b0 Valid bits 0 or unpredictable When the 8-bit data of a peripheral register is read, the value of the eight high-order bits (DBF3 and DBF2) of the data register does not change.
µPD17062 10.5 Data Buffer and Peripheral Registers Sections 10.5.1 to 10.5.7 describe the data buffer and the peripheral registers. 10.5.1 IDC Start Position Setting Register Fig. 10-4 shows the functions of the IDC start position setting register. The IDC start position setting register sets the IDC display start position. Fig.
µPD17062 10.5.2 A/D Converter Data Register Fig. 10-5 shows the functions of the A/D converter data register. The A/D converter data register sets the A/D converter comparison voltage. Because the A/D converter is a 4-bit converter, the four low-order bits of the A/D converter data register are valid. Fig.
µPD17062 10.5.3 Presettable Shift Register Fig. 10.6 shows the functions of the presettable shift register. The presettable shift register writes the serial interface serial out data and reads the serial interface serial in data. Fig.
µPD17062 10.5.4 HSYNC Counter Data Register Fig. 10.7 shows how the HSYNC counter data register functions . The HSYNC counter data register reads the horizontal synchronizing signal count. When the HSYNC counter data register reaches 3FH, it returns to 00H at the next input. Fig.
µPD17062 10.5.5 PWM Data Register Fig. 10-8 shows how the PWM data register functions. The PWM data register sets the duty cycle of the 6-bit D/A converter (PWM output) output. The 6-bit D/A converter has four channels (pins PWM3, PWM2, PWM1, and PWM0). Because the duty cycle can be set independently for each channel, four independent PWM duty cycle registers are also provided. Fig.
µPD17062 10.5.6 Address Registers The address registers are mapped to addresses 74H to 77H in the system register (at data memory addresses 74H to 7FH). They are used for program memory address operations. See Chapter 8. The address registers can be used to manipulate data directly with data memory operation instructions. They can also be used to transfer data via the data buffer as part of the peripheral hardware.
µPD17062 10.5.7 PLL Data Register Fig. 10-10 shows how the PLL data register functions. The PLL data register sets the frequency division ratio of the PLL frequency synthesizer. For the pulse swallow method, all 16 bits are valid, the 12 high-order bits are set in the program counter, and the remaining four low-order bits are set in the swallow counter. Fig.
µPD17062 10.6 10.6.1 PRECAUTIONS WHEN USING DATA BUFFERS Write Only, Read Only, and Unused Address Data Buffer Precautions When the 17K series assembler and emulator are used for data transfer with peripheral hardware via the data buffer, note the following regarding unused peripheral addresses and write only (PUT only) and read only (GET only) peripheral registers. (1) Device operation Reading from a write only peripheral register returns an unpredictable value.
µPD17062 10.6.2 Peripheral Register Addresses and Reserved Words When a 17K series assembler is used, no error is generated when peripheral address “p” is specified directly (with a numerical value) in PUT p, DBF or GET DBF, p as shown in Example 1. However, to reduce program bugs, this method should be avoided. Therefore, the peripheral addresses should be symbolically defined with symbol definition instructions (an assembler pseudo instructions), as shown in Example 2.
µPD17062 11. INTERRUPT An interrupt temporarily stops the program being executed in response to a request from the peripheral hardware (INTNC pin, timer, VSYNC pin or serial interface). The interrupt then branches the program flow to a predetermined address (vector address). 11.1 INTERRUPT BLOCK CONFIGURATION Fig. 11-1 shows the interrupt block configuration.
µPD17062 Fig.
µPD17062 11.2 INTERRUPT FUNCTION The following peripheral hardware can use the interrupt function: the INTNC pin, timer, V SYNC pin, and serial interface. If the peripheral hardware satisfies the specified condition (e.g., a falling edge is input to the INTNC pin), the interrupt function temporarily stops the program being executed and starts the exclusive processing program. The interrupt signal sent from the peripheral hardware at this time is called an interrupt request.
µPD17062 11.2.4 Interrupt Permission Flags (IP×××) The interrupt permission flags set interrupt permissions for various types of peripheral hardware. If these flags are set to 1 and the corresponding interrupt request flags are also set, the corresponding interrupt requests are output. Because these flags correspond one-to-one to the flags in the interrupt permission register of the control register, they are read and written via the window register.
µPD17062 11.2.6 Interrupt Enable Flip-Flop (INTE) The interrupt enable flip-flop sets the interrupt permissions of all four types of interrupts. If each interrupt request processing block outputs a 1 while this flip-flop is set to 1, a 1 is output from this flip-flop and an interrupt is accepted. Even if a 1 is output from each interrupt request processing block while this flip-flop is reset to 0, an interrupt is not accepted.
µPD17062 11.3 INTERRUPT ACCEPTANCE 11.3.1 Interrupt Acceptance and Priority An interrupt is accepted as follows: (1) When the interrupt conditions are satisfied (e.g., a rising edge is input to the INTNC pin), each type of peripheral hardware outputs the interrupt request signal to the interrupt request blocks. (2) When an interrupt request block accepts an interrupt request signal from the peripheral hardware, it sets the corresponding IRQ××× flag to 1 (e.g., sets IRQNC for the INTNC pin).
µPD17062 Fig.
µPD17062 11.3.2 Timing Chart at Interrupt Acceptance Fig. 11-3 shows the timing chart at interrupt acceptance. Fig. 11-3 (1) shows the timing chart of one interrupt. The timing chart when an interrupt request flag is set to 1 is shown in (a) of (1). The timing chart when an interrupt permission flag is set to 1 is shown in (b) of (1). In both cases, the interrupt is accepted when the interrupt request flag, interrupt enable flip-flop, and interrupt permission flag are all set.
µPD17062 Fig. 11-3 Interrupt Reception Timing Chart (1/2) (1) When one interrupt (e.g.
µPD17062 Fig. 11-3 Interrupt Acceptance Timing Chart (2) When two or more interrupts (e.g.
µPD17062 11.4 OPERATIONS AFTER INTERRUPT ACCEPTANCE When an interrupt is accepted, the following processing sequence is executed: (1) The interrupt enable flip-flop or interrupt request flag corresponding to the accepted interrupt is reset. In other words, a write protected state is set. (2) The stack pointer value is decreased by 1. (3) The contents of the program counter are saved in the address stack register indicated by the stack pointer.
µPD17062 11.6 INTERRUPT PROCESSING ROUTINE An interrupt is accepted in a program area that permits interrupts regardless of the program being executed. Therefore, to return control to the original program after interrupt processing, return the program to the state it is in when it is not processing an interrupt. For example, if an arithmetic operation is performed during interrupt processing, the contents of the carry flag may differ from those before interrupt acceptance.
µPD17062 11.6.3 Notes on Interrupt Processing Routine Note the following regarding the interrupt processing routine: (1) Data saved by hardware All bank registers and index enable flags are reset to 0 after being saved in the interrupt stack. (2) Data saved by software Data saved by software is not reset after being saved. Program status words such as the BCD flag, compare flag, carry flag, zero flag, and memory pointer enable flags keep their preacceptance values.
µPD17062 Example Saving the status in an interrupt processing routine Main routine Program example Interrupt processing routine (enters a DI state) BANK and IXE saving by hardware Saving contents of required system register using software EI M046 MEM 0.46H M047 MEM 0.47H M048 MEM 0.48H M04D MEM 0.4DH M04E MEM 0.4EH M05F MEM 0.5FH BTM0CK MEM 0.89H # POKE $ PEEK % POKE & MOV ( ST ) ST * PEEK + ST Interrupt reception M048, WR ; Saves the contents of the window register in M048.
µPD17062 Fig. 11-4 Saving the System or Control Register Using the Window Register Numbers # to + correspond to the numbers in the program example. Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F Row address 0 1 Data memory 2 BANK0 3 4 5 ( ) # Save area POKE M048, WR 6 7 AR1 AR0 WR Control register 2 3 Register file 120 $ BTM0CK 1 + RPL * 0 % & Specify the generalpurpose register.
µPD17062 11.7 EXTERNAL INTERRUPTS (INTNC PIN, VSYNC PIN) There are two external interrupt sources: INTNC and VSYNC. An interrupt request is issued when a rising or falling edge is input to the INTNC or V SYNC pin. 11.7.1 Configuration Fig. 11-5 shows the configurations of the INTNC and VSYNC interrupts. As shown in Fig. 11-5, the INTNC and VSYNC signals are input to the INTNC or INTVSYN latch and to edge detectors.
µPD17062 11.7.2 Functions An interrupt can be issued when either a rising or falling edge is input to the INTNC or VSYNC pin. Use the IEGNC or IEGVSYN flag in the interrupt edge select register of the control register to select the rising or falling edge. Table 12-2 shows the relationship between the IEGNC and IEGVSYN flags and the active edges of interrupt requests.
µPD17062 Table 11-3 Interrupt Request Issuance by IEGNC Flag Change IEGNC or IEGVSYN flag change INTNC or VSYNC pin Whether interrupt request is issued IRQNC flag → 0 Low Not issued No change (Rise) High Issued Set 0 Low Issued Set (Fall) High Not issued No change 1 (Fall) 1 (Rise) 11.8 → INTERNAL INTERRUPT (TIMER, SERIAL INTERFACE) There are two types of internal interrupts: the timer interrupt and the serial interface interrupt. 11.8.
µPD17062 11.9 MULTIPLE INTERRUPTS The multiple interrupt function is used to process interrupt C or D while another interrupt from source A or B is being processed as shown in Fig. 11-6. The interrupt depth at this time is called the interrupt level. Note the following regarding the multiple interrupt function.
µPD17062 11.9.1 Interrupt Source Priorities When using the multiple interrupt function, the priorities of interrupt sources must be determined. For example, if the interrupt sources are A, B, C, and D, the following priorities can be specified: A = B = C = D or A < B < C < D. If A = B = C = D, the main routine always accepts interrupts A, B, C, and D. However, if interrupt C is accepted, interrupts A, B, and D are inhibited, making the multiple interrupt function unusable.
µPD17062 For multiple interrupts of more than two levels, operations of the device and emulator differ as shown in Figs. 11-8 and 11-9. At interrupt stack, the device operation is the sweep-off type and the emulator operation is the rotation type. Use the RET instruction as the last restoration instruction when using multiple interrupts of more than two levels. RETI and RET instructions operate in the same manner except when restoring the contents of the interrupt stack.
µPD17062 Fig.
µPD17062 Fig. 11-8 Example of Using Multiple Level-3 Interrupts Undefined MAIN A B Undefined Undefined MAIN A Main routine Interrupt A Interrupt B Interrupt C MAIN A B C BANK0 CLR1 IXE DI BANK0 CLR1 IXE EI RET RETI RETI A A A B A A A A To interrupt A, be sure to set a lower priority than interrupts B and C. Fix the bank register and index enable flag (BANK0 and IXE = 0 in this example) in the main routine that permits interrupt A.
µPD17062 Fig. 11-9 Interrupt Stack Operation when 17K Series Emulator is Used Undefined MAIN MAIN B Undefined Undefined A A Main routine Interrupt A Interrupt B Interrupt C MAIN A B C RET RETI RETI B B B B A A A A If the RETI instruction is used on the emulator, the contents of the bank register and index enable flag of interrupt B are restored.
µPD17062 11.9.3 Interrupt Level Restriction by Address Stack Register The return address at control return from interrupt processing is automatically saved in the address stack register. The address stack register can use the six levels from ASR0 to ASR5 as described in Chapter 4. Because the interrupt sources are the INTNC pin, timer, VSYNC pin, and serial interface, the multiple interrupt level is unlimited when the address stack register is used only for interrupts.
µPD17062 11.9.4 Saving the Contents of System and Control Registers The contents of system and control registers must be saved before using the multiple interrupt function. The contents of these registers change during interrupt processing. An area must be obtained for these contents for each interrupt source. An interrupt being accepted and interrupts with lower priorities must be inhibited, and interrupts with higher priorities must be permitted.
µPD17062 In #, specify the data memory bank containing the contents of the system register. Because the bank becomes BANK0 when an interrupt is accepted, if the data is saved in BANK0, this instruction is not necessary. In $, save the contents of the window register in data memory M1. Because the POKE instruction is used, the address of data memory M1 should be 40H or more. Because the window register is used as a work area for subsequent data saving, its contents must be saved first.
µPD17062 12. TIMER The timer functions are used to manage the time in creating programs. 12.1 TIMER CONFIGURATION Fig. 12-1 shows the configuration of the timer. The timer consists of two blocks, timer carry flip-flop (timer carry FF) block and timer interrupt block, as shown in Fig. 12-1.
µPD17062 12.2 TIMER FUNCTIONS There are two timer functions, timer carry FF check and timer interrupt. The timer carry FF check function performs time management by checking, by program, the state of the timer carry FF, which is set at constant intervals. The timer interrupt function performs time management by requesting an interrupt at constant intervals.
µPD17062 Fig.
µPD17062 12.3 TIMER CARRY FLIP-FLOP (TIMER CARRY FF) The timer carry FF is set to 1 by the positive-going edge of the timer carry FF set pulse specified by the timer mode select register. The content of the timer carry FF corresponds to the lowest bit (BTM0CY flag) of the timer carry FF judge register on a one-to-one basis, and when the timer carry FF is set to 1, the BTM0CY flag is also set to 1 at the same time.
µPD17062 12.3.1 Example of Using the Timer Based on the BTM0CY Flag An example of a program follows. Example INITFLG NOT BTM0ZX, NOT BTM0CK2, NOT BTM0CK1, NOT BTM0CK0 ; Built-in macro ; Specifies that the timer carry FF be set at intervals of 100 ms. LOOP1: MOV M1, #0110B LOOP2: SKT1 BTM0CY ; Built-in macro ; Tests the BTM0CY flag. Branches to NEXT if the flag is 0. BR NEXT ADD M1, #0100B ; Adds 4 to data memory M1. SKT1 CY ; Built-in macro ; Tests the CY flag.
µPD17062 12.3.2 Timer Error Caused by the BTM0CY Flag There are two types of timer error that can occur because of the BTM0CY flag. One type depends on the timing when the BTM0CY flag is checked, and the other type occurs when the timer carry FF setting interval is changed. These types of timer error are detailed below. (1) Timer error by BTM0CY flag check timing As described in Section 12.3.
µPD17062 (2) Timer error that occurs when the timer carry FF setting time interval is changed The timer carry FF setting time interval is specified by the BTM0CK2, BTM0CK1, and BTM0CK0 flags in the timer mode select register. As shown in Fig. 12-1 and 12-2, the timer interval set pulse can be selected from 200 Hz, 10 Hz, and an external timer. These three pulses operate independently.
µPD17062 As shown in Fig. 12-5, if the timer carry FF setting time interval is switched, the timer error that occurs before the BTM0CY flag is set for the first time is as follows: -tSET < error < tCHECK where tSET : Newly selected timer carry FF setting time interval tCHECK : Time interval at which the BTM0CY flag is checked The internal pulses, 4 Hz, 10 Hz, 200 Hz, and 1 kHz, have a phase difference.
µPD17062 12.4 CAUTIONS IN USING THE TIMER CARRY FF The timer carry FF is used not only as a timer function but also as a reset sync signal at a CE reset. A CE rest occurs when the timer carry FF set pulse rises after the CE pin goes from a low to a high. Note the following points: (1) The sum of the time used to update the timer and the time interval at which the BTM0CY flag is checked must be less than the timer carry FF setting time interval.
µPD17062 12.4.1 Timer Update Time and BTM0CY Flag Check Time Interval As described in Section 12.3.1, the time interval tSET at which the BTM0CY flag is checked must be less than the time interval at which the timer carry FF is set. Even when the above requirement is satisfied, if the timer update process takes long, the timer process may not be performed correctly when a CE reset occurs. To solve this problem, it is necessary to satisfy the following condition.
µPD17062 12.4.2 Correcting the Timer Carry FF at a CE reset This section describes an example of correcting the timer at a CE reset. If the timer carry FF is used both to check for power failure and as a timer, it is necessary to correct the timer at a CE reset, as explained in the following example. The timer carry FF is reset to 0 at a power-on reset, and it is kept from being set until the BTM0CY flag is read-accessed using a PEEK instruction.
µPD17062 Fig.
µPD17062 12.4.3 If the BTM0CY flag is checked at the same time with a CE reset As described in Section 12.4.2, a CE reset occurs at the same time the BTM0CY flag is set to 1. If the BTM0CY flag read instruction happens to occur at the same time a CE reset occurs, the BTM0CY flag read instruction takes precedence.
µPD17062 The program shown below is an example of a program that meets the above condition. Do not creates such a program. Example Process A INITFLG NOT BTM0ZX, NOT BTM0CK2, NOT BTM0CK1, BTM0CK0 ; Built-in macro ; Specifies the timer carry FF set pulse as 5 ms. LOOP: ; # SKT1 BTM0CY ; Built-in macro BR BBB AAA: 496 steps BR LOOP BBB: 496 steps BR LOOP Because the BTM0CY flag read instruction at # in this program is executed at every 500 instructions, once #, a CE reset will not occur forever.
µPD17062 12.5 TIMER INTERRUPT The timer interrupt function issues an interrupt request at the negative-going edge of the timer interrupt pulse specified in the timer mode select register. The timer interrupt request corresponds to the IRQBTM0 flag in the interrupt request register on a one-toone basis. When an interrupt is requested, the corresponding IRQBTM0 flag is set to 1. In other words, when a timer interrupt request pulse falls, the IRQBTM0 flag is set to 1.
µPD17062 12.5.1 Example of Using a Timer Based on a Timer Interrupt An example follows. Example BR AAA TIMER: ; Branches to AAA. ; Program address 0003H ADD M1, #0001B ; Add 1 to M1. SKT1 CY ; Tests the CY flag. BR BBB ; Returns if no carry is generated. Process A BBB: EI RETI AAA: INITFLG NOT BTM0ZX, NOT BTM0CK2, NOT BTM0CK1, NOT BTM0CK0 ; Built-in macro ; Specifies the timer interrupt pulse as 5 ms. MOV M1, #0000B ; Clears the content of M1 to 0.
µPD17062 12.5.2 Timer Interrupt Error As explained in Section 12.4, an interrupt request is accepted each time the timer interrupt pulse goes low, provided that the interrupt is enabled. A timer error due to use of a timer interrupt occurs when: (1) An interrupt request is accepted for the first time after the timer interrupt is enabled. (2) An interrupt request is accepted for the first time after the timer interrupt pulse interval is switched. (3) Writing to the IRQBTM0 flag occurs.
µPD17062 Fig. 12-9 Timer Interrupt Error (2/2) (b) When the timer interrupt pulse is switched Internal pulse A Internal pulse B Timer interrupt pulse IRQBTM0 IPBTM0 INTE EI FF DI EI Interrupt accepted # Timer interrupt pulse switched EI EI $Interrupt accepted % Timer interrupt pulse switched EI Interrupt accepted #, no interrupt occurs because the timer interrupt $.
µPD17062 12.6 CAUTIONS IN USING THE TIMER INTERRUPT In a program using a timer that operates at constant intervals once a power-on reset occurs, it is necessary to have the timer interrupt handling routine finish within that constant interval. This is explained using an example. Example BR AAA TIMER: ; Program address 0003H ADD M1, #0100B ; Adds 0100B to the content of M1. SKT1 CY BR AAA ; ; Branches to AAA after reset. # ; Performs clock processing if a carry occurs.
µPD17062 In reality, however, to avoid skipping the timer process in the above example, a delay is provided between the negative-going edge of the timer carry FF set pulse and the negative-going edge of the timer interrupt pulse, as shown in Fig. 12-10 (b). As shown at (2) in Fig. 12-10, restricting the clock process to within 10 ms can eliminate skipping of a timer interrupt that would otherwise be caused by a CE reset. Fig.
µPD17062 13. STANDBY The standby function is intended to reduce the current drain of the device at backup. 13.1 STANDBY BLOCK CONFIGURATION Fig. 13-1 shows the configuration of the standby block. As shown in Fig. 13-1, the standby block is further divided into halt control and clock stop control blocks. The halt control block consists of the halt control circuit, interrupt control block, timer carry FF, and the P0D0/ ADC2 to P0D3/ADC5 pins.
µPD17062 13.2 STANDBY FUNCTION The standby function stops the whole or part of the operation of the device to reduce its current drain. The standby function is divided into halt and clock stop functions. The halt function uses a dedicated instruction (HALT h instruction) to stop the CPU in order to reduce the required current drain. The clock stop function uses a dedicated instruction (STOP s instruction) to stop the 8 MHz crystal oscillator in order to reduce the current drain in the device.
µPD17062 13.3 DEVICE OPERATION MODE SPECIFIED AT THE CE PIN The CE pin controls the following items according to the level and positive-going edge of its input signal. (1) Whether to enable or disable the clock stop instruction (2) Whether to reset the device Sections 13.3.1 and 13.3.2 explain the above items, respectively. 13.3.1 Controlling Whether to Enable or Disable the Clock Stop Instruction The clock stop instruction, STOP s, is effective only when the CE pin is at a low level.
µPD17062 13.4 HALT FUNCTION The halt function stops the operation of the CPU clock by executing the HALT h instruction. When the HALT h instruction is executed, the program stops at this instruction and rests there until the halt state is released. In the halt state, the current drain in the device is reduced by the amount required by the CPU to operate. The halt state can be released using the timer carry FF, interrupt, and key entry.
µPD17062 13.4.2 Halt Release Conditions Fig. 13-3 summarizes the release conditions. As shown in Fig. 13-3, the halt release condition is 4-bit data specified in the operand h of the HALT h instruction. The halt state is released when a condition specified as 1 in the operand h is satisfied. Upon release of the halt state, the subsequent instructions after the HALT h instruction are executed sequentially.
µPD17062 13.4.3 Halt Release by Key Entry The HALT 0001B instruction specifies a key entry as a halt release condition. If this condition is specified, the halt state is released when a high level is applied to one of the P0D0/ADC2 to P0D3/ADC5 pins. Items (1) to (3) describe cautions to be taken in using a general-purpose output port as a key source signal and the P0D0/ADC2 to P0D3/ADC5 pins for an A/D converter.
µPD17062 (2) Cautions in using the P0D0/ADC2 to P0D3/ADC5 pins for an A/D converter A/D input P0D3/ADC5 A/D input Latch P0D2/ADC4 P0D1/ADC3 P0D0/ADC2 General-purpose port If one of the P0D0/ADC2 to P0D3/ADC5 pins is selected for an A/D converter (only one pin can be selected at one time), it is disconnected from the input latch and connected to the internal A/D converter input. If a pin happens to be at a high level when it is selected for an A/D converter, the latch circuit is held at a high.
µPD17062 (3) Alternative method to release the halt state P0D3/ADC5 Latch Output port P0D2/ADC4 Microprocessor or the like P0D1/ADC3 P0D0/ADC2 General-purpose output port The P0D0/ADC2 to P0D3/ADC5 pins can be used a general-purpose input port with a built-in pull-down resistor. This configuration of the P0D0/ADC2 to P0D 3/ADC5 pins enables a microprocessor to be used to release the halt state as shown above.
µPD17062 13.4.4 Releasing the Halt State by the Timer Carry FF The HALT 0010B instruction specifies the timer carry FF as a halt release condition. If it is specified that the halt state is to be released according to the timer carry FF, the halt state is released immediately when the timer carry FF is set to 1. The timer carry FF corresponds to the BTM0CY flag (bit b0 at address 17H) in the control register on a oneto-one basis, and is set to 1 at constant intervals (5 or 100 ms).
µPD17062 13.4.5 Releasing the Halt State by an Interrupt The HALT 1000B instruction specifies an interrupt as halt release condition. If it is specified that the halt state is to be released according to an interrupt, the halt state is released immediately when an interrupt request is accepted. Four interrupt sources, INTNC pin, timer, VSYNC, and serial interface, can be used as a condition to release the halt state.
µPD17062 Example HLTINT DAT 1000B ; Defines a symbol. START: ; Address 0000H BR MAIN ; INTTIMER ; Branches to INTTIMER (interrupt handling). NOP INTTM: ; Timer interrupt vector address (0003H) BR ; INTNC pin interrupt vector address (0004H) INT0: ; Interrupt requested at the INTNC pin Process A EI RETI INTTIMER: Process B ; Timer interrupt handling EI RETI MAIN: SET2 IPBTM0, IPNC ; Built-in macro SET1 BTM0CK2 ; Built-in macro ; Enables INTNC pin and timer interrupts.
µPD17062 13.5 CLOCK STOP FUNCTION The clock stop function stops the operation of the 8 MHz crystal oscillator by executing the STOP s instruction. The clock stop function can reduce the current drain of the µPD17062 by 10 µA (maximum). The operand s of the STOP s instruction is 0000B. This instruction is effective only when the CE pin is at a low level. If executed when the CE pin is at a high, the STOP s instruction is regarded as a no-operation instruction (NOP).
µPD17062 Fig. 13-4 Releasing the Clock Stop State by a CE Reset 5V VDD 0V CE pin Crystal oscillation (XOUT pin) Approx. 50 ms STOP 0 instruction 5V Program starts at address 0 (CE reset) If a clock-stop instruction is not used, operation is as follows: VDD 0V CE pin Clock oscillation (XOUT pin) 0-tSET Program starts at address 0 (CE reset) CE reset is applied in synchronization with the setting of the timer carry FF after the CE pin has been raised to high level. Fig.
µPD17062 13.5.3 Cautions in Using the Clock Stop Instruction The clock stop instruction (STOP s) is effective only when the CE pin is at a low level. To enable the clock stop state to be released, the program must therefore have a provision to handle when the CE pin happens to be at a high. Such a provision is explained using the example below. Example XTAL DAT 0000B ; Defines a symbol for the clock stop condition.
µPD17062 13.6 13.6.1 OPERATION OF THE DEVICE AT A HALT OR CLOCK STOP State of Each Pin at a Halt and Clock Stop Table 13-1 summarizes how the CPU and peripheral hardware behave during the halt or clock stop state. During the halt state, execution of the CPU instructions is suspended, but the peripheral hardware operates normally, as described in Table 13-1. During the clock stop state, on the other hand, all peripheral hardware is at a stop.
µPD17062 If the STOP instruction at set up at ( is executed in place of the HALT instruction at &, all flags in the control register #, $, and % are initialized, and therefore, the serial communication is suspended and all pins of port 0A are specified as general-purpose input/output ports.
µPD17062 13.6.2 Cautions in Processing of Each Pin During Halt or Clock Stop State The halt function is intended to reduce the required current drain, for example, by allowing only the clock to operate. Meanwhile, the clock stop function is intended to reduce the required current drain by suspending all operations except preservation of data in memory. During the halt or clock stop state, therefore, it is necessary to reduce the required current drain as much as possible.
µPD17062 Table 13-2 State of Each Pin During the Halt or Clock Stop State and Cautions to Be Taken (2/2) State of each pin and cautions in processing Pin function Pin symbol Halt state Clock stop state Interrupt INTNC If the pin is floating, external noise causes the current drain to increase. IDC RED The output pins remain in the state in which they were when the HALT instruction was executed. If the IDCEN flag is set, the current drain increases. The IDC is disabled.
µPD17062 14. RESET The reset function is used to initialize device operation. 14.1 RESET BLOCK CONFIGURATION Fig. 14-1 shows the configuration of the reset block. Device reset is divided into reset by turning on VDD (power-on reset or VDD reset), and reset by CE pin (CE reset). The power-on reset block consists of a voltage detection circuit that detects the voltage applied to the VDD pin, a power failure detection circuit, and a reset control circuit.
µPD17062 14.2 RESET FUNCTION Power-on reset is applied when VDD rises from a certain voltage, CE reset is applied when the CE pin rises from low level to high level. Power-on reset initializes the program counter, stack, system register and control registers, and executes the program from address 0000H. CE reset initializes the program counter, stack, system register and some control registers, and executes the program from address 0000H.
µPD17062 14.3 CE RESET CE reset is executed by raising the CE pin from low level to high level. When the CE pin rises to high level, the RESET signal is output and the device is reset in synchronization with the rising edge of the pulse used for the next setting of the timer carry FF. When CE reset is applied, the RESET signal initializes the program counter, stack, system register, and some control registers to their initial value and executes the program from address 0000H.
µPD17062 14.3.2 CE Reset When Clock-Stop (STOP Instruction) Used Fig. 14-3 shows the reset operation. When clock-stop is used, the IRES, RES and RESET signals are output at the time the STOP instruction is executed. At this time, the RES signal initializes the timer mode selection register of the control registers to 0000B and sets the timer carry FF set signal to 100 ms. Since the IRES signal is output continuously while the CE pin is low level, release by timer carry FF is forcibly halted.
µPD17062 14.3.3 Cautions at CE Reset When CE reset is used, careful attention must be given to points (1) and (2) below regardless of the instruction being executed. (1) Time required for clock and other timer processing When writing a clock program by using timer carry FF and timer interrupts, the program must end processing within a certain time. For details, see Sections 12.4 and 12.6. (2) Processing of data, flags, etc.
µPD17062 Example 2. ; ; & # SKT1 FLG1 BR LCTUNE ST M1, R1 ST M2, R2 CLR1 FLG1 ; If FLG1 is set to 1, ; data is rewritten to M1 and M2 again. LCTUNE : Initial reception ; The last channel is received. The channel indicated by the contents of M1 and M2 is received. MAIN : ; Main processing Channel change ( SET1 ;$ ST ;% ; The changed channel is assigned to general-purpose ; registers R1 and R2. ; ST FLG1 ; FLG1 is set while rewriting the last channel.
µPD17062 14.4 POWER-ON RESET Power-on reset is executed by raising VDD from a certain voltage (called the power-on clear voltage) or less. When VDD is less than the power-on clear voltage, the power-on clear signal (POC) is output from the voltage detection circuit shown in Fig. 14-1. When the power-on clear signal is output, the crystal oscillation circuit stops and the device stops operating. While the power-on clear signal is being output, the IRES, RES and RESET signals are output.
µPD17062 14.4.1 Power-on Reset at Normal Operation Fig. 14-5 (a) shows power-on reset at normal operation. As shown in Fig. 14-5 (a), when the VDD drops below 3.5 V, the power-on clear signal is output and operation of the device stops regardless of the input level of the CE pin. When VDD then rises to 3.5 V or greater, after a 50 ms halt, the program starts from address 0000H. Normal operation refers to the state in which the clock-stop instruction is not used.
µPD17062 Fig. 14-5 Power-on Reset and VDD (a) During normal operation (including halt state) 5V 3.5 V Power-on clear voltage VDD 0V “H” CE XOUT Power-on clear signal Device operation stopped Normal operation Halt state 50 ms Power-on clear release Oscillation start Power-on reset Program starts from address 0 (b) At clock-stop 5V 3.5 V VDD Power-on clear voltage 2.
µPD17062 14.5 RELATIONSHIP BETWEEN CE RESET AND POWER-ON RESET When supply voltage is first turned on, power-on reset and CE reset may be applied simultaneously. Sections 14.5.1 through 14.5.3 describe this reset operation. Section 14.5.4 describes the cautions when supply voltage rises. 14.5.1 When VDD Pin and CE Pin Rise Simultaneously Fig. 14-6 (a) shows the reset operation. Power-on reset starts the program from address 0000H. 14.5.2 When CE Pin Raised in Forced Halt State Caused by Power-on Reset.
µPD17062 Fig. 14-6 Relationship Between Power-on Reset and CE Reset (a) When VDD and CE pin raised simultaneously 5V 3.5 V Power-on clear voltage VDD 0V CE Timer carry FF set pulse Operation stopped Halt state 50ms Normal operation Power-on reset Program start (b) When CE pin raised in halt state 5V 3.
µPD17062 14.5.4 Cautions When Supply Voltage Raised When supply voltage is raised, careful attention must be given to points (1) and (2) below. (1) When VDD raised from power-on clear voltage When VDD is raised, it must be raised to 3.5 V or greater, once. This is shown in Fig. 14-7. As shown in Fig. 14-7, when a voltage under 3.5 V is applied when VDD is turned on in a program that uses clock-stop to back up VDD at 2.
µPD17062 (2) At return from clock-stop state When returning from the back-up state when clock-stop is used to back-up supply voltage at 2.2 V, VDD must be raised to 3.5 V or greater within 50 ms after the CE pin becomes high level. As shown in Fig. 14-8, return from the clock-stop state is performed by CE reset. Since the power-on clear voltage is switched to 3.5 V 50 ms after the CE pin is raised, if VDD is not 3.5 V or greater at this time, poweron reset is applied.
µPD17062 14.6 POWER FAILURE DETECTION Power failure detection is used to judge whether the device is reset by turning on VDD or by the CE pin, as shown in Fig. 14-9. Since the contents of the data memory, output ports, etc. become “undefined” when VDD is turned on, they are initialized by power failure detection. Fig. 14-9 Power Failure Detection Flowchart Program start No power failure Power failure detection Power failure Data memory, output port, etc. initialization 14.6.
µPD17062 Fig. 14-10 BTM0CY Flag State Transition CE = low # $ BTM0CY flag setting disabled state & Clock-stop STOP 0 ( CE = optional VDD = low Operation stopped VDD = L→3.5 V Clock oscillation start Forced halt (approx. 50 ms) % Power-on reset CE = L Normal operation CE = H ) CE = H→L CE = L→H CE = L→H - SKT1 BTM0CY or SKF1 BTM0CY / Clock-stop BTM0CY flag setting enable state STOP 0 0 CE = high Normal operation Normal operation + , .
µPD17062 Fig. 14-11 BTM0CY Flag Operation (a) When BTM0CY flag not detected even once (neither SKT1 BTM0CY nor SKF1 BTM0CY executed) 5V VDD 0V CE Timer carry FF set pulse BTM0CY Fig. 14-12 operation # $ ) % ( + ) ( * Timer time switching & , ) # 1 # * STOP 0000B (b) When power failure detected with BTM0CY flag 5V VDD 0V CE Timer carry FF set pulse BTM0CY SKT1 BTM0CY instruction Fig. 14-12 operation # $ )1 %.
µPD17062 14.6.2 Cautions at Power Failure Detection with BTM0CY Flag When clock counting, etc. is performed with the BTM0CY flag, careful attention must be given to the following points. (1) Clock updating When writing a clock program by using the timer carry FF, the clock must be updated after a power failure. This is because the BTM0CY flag is reset to 0 and one clock count is lost by BTM0CY flag reading when a power failure is detected.
µPD17062 Example Sample program START: ; ; Program address 0000H # Reset processing ; $ SKT1 BTM0CY BR INITIAL ; ; Power failure detection BACKUP: ; % Clock updating BR MAIN INITIAL: ; ; & ( Initialization INITFLG NOT BTM0ZX, NOT BTM0CK2, NOT BTM0CK1, BTM0CK0 ; Built-in macro ; Sets timer carry FF set time to 5 ms.
µPD17062 15. GENERAL-PURPOSE PORT A general-purpose port outputs a high level, low level, or floating signal to an external circuit and reads a high level or low level signal from an external circuit. 15.1 CONFIGURATION AND CLASSIFICATION OF GENERAL-PURPOSE PORT Fig. 15-1 shows a block diagram of the general-purpose port. Table 15-1 lists the classifications of general-purpose ports. As shown in Fig.
µPD17062 Table 15-1 Classification of General-Purpose Ports General-purpose ports Classification of general-purpose ports 190 I/O shared port Target ports Data setting method Bit I/O Port0A Port0B Port1B Port register Group I/O Port1C Port register Input-only port Port0D Port register Output-only port Port0C Port1A Port register
µPD17062 15.2 FUNCTIONS OF GENERAL-PURPOSE PORTS A general-purpose I/O port, set up either as a general-purpose output port or output port, outputs high level or low level signals from each corresponding pin by setting data in the port register accordingly. A general-purpose I/O port, set up either as a general-purpose input port or input port, detects the level of the input signal applied to each corresponding pin by reading the contents of the port register.
µPD17062 15.2.2 General-Purpose I/O Ports (P0A, P0B, P1B, P1C) The I/O of P0A is switched by the P0A bit I/O selection register (RF address 37H). The I/O of P0B is switched by the P0B bit I/O selection register (RF address 36H). The I/O of P1B is switched by the P1B bit I/O selection register (RF address 35H). And, the I/O of P1C is switched by the P1C group I/O selection register (RF address 27H). The I/O data of P0A is set by P0A (data memory address: 70H of BANK0 or BANK2) of the port register.
µPD17062 Table 15-2 Relationship between Each Port (Pin) and Port Register Pin Data setting method Port register (data memory) Port Symbol I/O Bank Address Symbol P0A3 Port0A (P0A) b3 P0A3 b2 P0A2 b1 P0A1 P0A0 b0 P0A0 P0B3 b3 P0B3 b2 P0B2 b1 P0B1 P0A2 P0A1 Port0B P0B2 (P0B) P0B1 Port0C (P0C) Bit symbol (reserved word) I/O (bit I/O) 70H I/O (bit I/O) 71H P0A P0B P0B0 BANK0 b0 P0B0 P0C3 BANK2 b3 P0C3 b2 P0C2 b1 P0C1 P0C0 b0 P0C0 P0D3 b3 P0D3 b2 P0D2 P0
µPD17062 15.3 GENERAL-PURPOSE I/O PORTS (P0A, P0B, P1B, P1C) 15.3.1 Configuration of I/O Ports In the following, (1) to (3) explain the configuration of the I/O ports.
µPD17062 15.3.3 Port0A Bit I/O Selection Register (P0ABIO) Port0B Bit I/O Selection Register (P0BBIO) Port1B Bit I/O Selection Register (P1BBIO) Port1C Group I/O Selection Register (P1CGPIO) The Port0A bit I/O selection register sets I/O for each pin of P0A. The Port0B bit I/O selection register sets I/O for each pin of P0B. The Port1B bit I/O selection register sets I/O for each pin of P1B. The Port1C group I/O selection register sets I/O for each pin of P1C.
µPD17062 15.3.4 To Use an I/O Port (P0A, P0B, P1B, P1C) as an Input Port Select the pin to be used as an input port by using the I/O selection register of each port. P1C can be set to I/O in 3-bit (3-pin) units only. The pin specified as an input port enters floating (Hi-Z) status and waits for the input of an external signal. Input data can be read by executing an instruction to read the contents of the port register for each pin, for example, the SKT instruction.
µPD17062 15.3.6 Notes on Using I/O Ports (P0A1 and P0A0) As shown in the example below, when pins P0A1 and P0A0 pins are used as output pins, the contents of the output latch may be overwritten. Example: INITFLG NOT P0ABIO3, NOT P0ABIO2, P0ABIO1, P0ABIO0 INITFLG NOT P0A3, NOT P0A2, P0A1, P0A0 ; Set the P0A1, P0A0 pins as output pins ; # CLR1 ; Output a high level signal to the P0A1 and P0A0 pins P0A1 ; Output a low level signal to the P0A1 pin ; Macro expansion AND .MF.P0A1 SHR 4, #.DF.
µPD17062 15.4 GENERAL-PURPOSE INPUT PORT (P0D) 15.4.1 Configuration The following explains the configuration of the input port. (1) P0D (P0D3, P0D2, P0D1, P0D0 pins) Write instruction To A/D converter Port register (1 bit) VDD Input latch Read instruction RESET ADC selection signal High on-state resistor 15.4.2 Example of Using Input Port (P0D) Input data can be read by executing an instruction, such as the SKT instruction, to read the contents of the port register for each pin.
µPD17062 15.5 15.5.1 GENERAL-PURPOSE OUTPUT PORTS (P0C, P1A) Configuration of Output Ports (P0C, P1A) (1) and (2), below, show the configuration of the output ports.
µPD17062 15.5.2 Example of Using Output Ports (P0C, P1A) The output ports output the contents of the output latch from each pin. Output data can be set by executing an instruction, such as the MOV instruction, to write the contents of the port register for each pin. To output a high level signal to each pin, write 1. To output a low level signal to each pin, write 0.
µPD17062 16. SERIAL INTERFACE The µPD17062 has two sets of serial interface pins, channel 0 (CH0) and channel 1 (CH1), for exchanging data with an external unit. The CH0 pin, which consists of two wires, SDA and SCL, can be operated in any of three modes, clock synchronous two-wire serial input, clock synchronous two-wire serial output, and two-wire busNote. The SDA and SCL pins can be used as general-purpose ports when not being used as a serial interface.
µPD17062 Table 16-2 Serial interface mode register SB Port 0A I/O specification SIO0MS SIO0TX P0ABIO1 SDA pin SCL pin Operation mode 0 0 0 0 0 SD-IN CK-IN 0 0 0 0 1 SD-IN OUT-PORT 0 0 0 1 0 OUT-PORT IN-PORT 0 0 0 1 1 OUT-PORT OUT-PORT 0 0 1 × 0 SD-OUT CK-IN 0 0 1 × 1 SD-OUT OUT-PORT 0 1 0 0 × SD-IN CK-OUT Serial I/O-SI, INT-CLK 0 1 0 1 × OUT-PORT CK-OUT CLK-OUT+1OUT-PORT 0 1 1 × × SD-OUT CK-OUT Serial I/O-SO, INT-CLK 1 0 0 0 0 SD-
µPD17062 Table 16-3 Serial interface mode register SB Port 0A I/O specification CH1 Operation Modes SI pin SCK pin SO pin Operation mode IN-PORT Serial I/O-SI, EXT-CLK, 1IN-PORT SIO0MS SIO0TX P0ABIO2 P0ABIO3 P0BBIO0 0 0 0 0 0 0 SD-IN CK-IN 0 0 0 0 0 1 SD-IN CK-IN 0 0 0 0 1 0 OUT-PORT IN-PORT 0 0 0 0 1 1 OUT-PORT IN-PORT OUT-PORT 2OUT-PORT+1IN-PORT 0 0 0 1 0 0 SD-IN OUT-PORT IN-PORT 0 0 0 1 0 1 SD-IN OUT-PORT OUT-PORT Serial I/O-SI, INT-CLK (SOFT-CLK),
µPD17062 16.1.1 SIO0CH The SIO0CH flag is used to select the channel of the serial interface. When the SIO0CH flag is set to 0, the serial interface hardware is connected to CH0. When the SIO0CH flag is set to 1, the serial interface hardware is connected to CH1. The external pin of the unselected channels is used as a general-purpose port. Table 16-4 16.1.2 Channel Setting of Serial Interface SIO0CH Channel to be selected 0 CH0 1 CH1 SB The SB flag specifies the serial interface protocol.
µPD17062 16.1.3 SIO0MS The SIO0MS flag specifies the serial interface clock to be used. When the SIO0MS flag is set to 0, the external clock is selected. When the SIO0MS flag is set to 1, the internal clock is selected. When the internal clock is selected, its frequency is set by the shift clock frequency register (RF: 39H). When the SIO0MS flag is set to 0 in two-wire bus mode, slave operation is specified. When the SIO0MS flag is set to 1 in two-wire bus mode, master operation is specified.
µPD17062 16.2 CLOCK COUNTER The clock counter is a wrap around counter that counts the clock of the shift clock pin (P0A1/SCL pin for CH0, P0A2/SCK pin for CH1) of the currently selected serial interface. The clock counter counts the shift clock from 1 to 9 repeatedly. The initial value of the counter is 0. The counter is incremented by 1 each time the clock rising edge is detected. Once the counter has been incremented to 9, the counter is reset to 1, after which it is again incremented in the same way.
µPD17062 16.3 STATUS REGISTER The status register is a four-bit read-only register that retains the start and stop states in two-wire bus mode and the contents of the current clock counter. Fig. 16-2 16.3.1 Configuration of Status Register Bit position b3 b2 b1 b0 Flag name SIO0SF8 SIO0SF9 SBSTT SBBSY SBBSY (Serial Bus Busy) Flag The SBBSY flag, mapped to b0 (LSB) of the status register (RF: 28H), detects the busy signal in two-wire bus mode.
µPD17062 16.3.4 SIO0SF8 (Serial I/O Shift 8 Clock) Flag The SIO0SF8 flag, mapped to b3 of the status register, is set to 1 when the contents of the clock counter become 8. When the contents of the clock counter become 0 or 1, the SIO0SF8 flag is reset to 0. An operation to read the presettable shift register must be performed while the SIO0SF8 flag is set to 1. The SIO0SF8 flag is not influenced by the contents of the serial mode register. Fig.
µPD17062 16.4 WAIT REGISTER The µPD17062 can set a state in which the serial interface hardware does not operate, even if a shift clock is input. This state is called wait mode and is set by the wait register.
µPD17062 Table 16-8 Wait mode Wait Timings SIO0WRQ1 SIO0WRQ0 Two-wire bus mode Serial I/O mode 0 0 No-wait Does not wait. Does not wait. 0 1 Data wait Waits when the shift clock falls with the clock counter set to 8. Waits with the shift clock in the high level state when the contents of the clock counter become 8. 1 0 Acknowledge wait Waits when the shift clock falls with the clock counter set to 9.
µPD17062 (2) Master operation wait in two-wire bus mode Master operation wait in two-wire bus mode incurs the interruption of transmission. In this mode, when the timing specified by SIO0WRQ1 and SIO0WRQ0 is set, the shift clock is fixed to the low level.
µPD17062 16.4.2 SIO0NWT (Serial I/O No-Wait) Flag Writing appropriate data into the SIO0NWT flag can both release wait and execute forced wait. (1) Writing 0 into SIO0NWT In this case, forced wait is executed. In other words, the clock being supplied to the clock counter and presettable shift register is disabled. If the SIO0MS flag of the serial interface mode register is set to 1 at this time, shift clock operation stops in the current state. (2) Writing 1 into SIO0NWT In this case, wait is released.
µPD17062 (2) For transmission in two-wire bus mode (SIO0TX = 1) In this case, the contents of an acknowledgement received from the receiver side are set in the SBACK flag. This means that the acknowledge state of the receiver side can be determined simply by reading the contents of the SBACK flag. This examining of the SBACK flag must be done after the 9th bit of 1-byte is set but before the 9th bit of the next data is set. Normally, waiting is instigated at the falling edge of the 9th bit.
µPD17062 16.5 PRESETTABLE SHIFT REGISTER (PSR) The presettable shift register is an 8-bit register.
µPD17062 16.6 SERIAL INTERFACE INTERRUPT SOURCE REGISTER (SIO0IMD) The interrupt source register (SIO0IMD) is a four-bit register that specifies when an interrupt is generated in the CPU during serial interface communication. The SIO0IMD register is mapped to address 38H of the register file. Fig. 16-6 shows the configuration of the SIO0IMD register. The register is not mapped to the two high-order bits of the SIO0IMD. If the two high-order bits of the SIO0IMD are read, 0 is read from each bit. Fig.
µPD17062 16.7 SHIFT CLOCK FREQUENCY REGISTER (SIO0CK) The shift clock frequency register is a four-bit register for setting the frequency of the internal clock of the serial interface. The shift clock frequency register is mapped to address 39H of the register file. Fig. 16-7 shows the configuration of the shift clock frequency register. The register is not mapped to the two high-order bits of the shift clock frequency register.
µPD17062 17. D/A CONVERTER 17.1 PWM PINS The µPD17062 has 4 output pins for 6-bit PWM, which enables varying the duty cycle of the 15.625 kHz pulse signal in 64 steps. With this capability, attaching an external lowpass filter to the µPD17062 makes it function as a D/A converter. The PWM pins can also be used as 1-bit output ports. When used as a D/A converter, the µPD17062 sets the D/A outputs in the output data latches, PWMRs.
µPD17062 Fig. 17-1 PWMR Structure and the Corresponding DBF Bits DBF1 (0EH) b3 DBF0 (0FH) b2 b1 b0 b3 b2 b1 b0 b6 b5 b4 b3 b2 b1 b0 PWMR 0 The PWM pin is used as a D/A converter. 1 The PWM pin is used as a one-bit output port (through mode), which outputs the content of b5. Fig. 17-2 Waveform Output from the PWM Pin t 64 µ s t = n + 0.
µPD17062 18. PLL FREQUENCY SYNTHESIZER 18.1 PLL FREQUENCY SYNTHESIZER CONFIGURATION Fig. 18-1 is a block diagram of the PLL frequency synthesizer. As shown in Fig. 18-1, the PLL frequency synthesizer consists of a programmable divider (PD), phase comparator (φ-DET), reference frequency generator (RFG), and charge pump. Strictly speaking, a PLL frequency synthesizer is configured by connecting these blocks with an external lowpass filter (LPF) and voltage-controlled oscillator (VCO). See Sections 18.
µPD17062 18.2 OVERVIEW OF EACH PLL FREQUENCY SYNTHESIZER BLOCK The PLL frequency synthesizer receives an input signal at the VCO pin, divides its frequency in the programmable divider, and outputs the difference in phase between the divider output and the reference frequency from the EO pin. The PLL frequency synthesizer works only when the CE pin is at a high level. It is disabled when the CE pin is at a low level. See Section 18.6 for the disable mode of the PLL frequency synthesizer.
µPD17062 18.3 18.3.1 PROGRAMMABLE DIVIDER (PD) AND PLL MODE SELECT REGISTER Programmable Divider Configuration Fig. 18-2 shows the configuration of the programmable divider (PD). As shown in Fig. 18-2, the programmable divider consists of a swallow counter and programmable counter. Fig.
µPD17062 18.3.2 Programmable Divider (PD) and Data Buffer (DBF) The programmable divider divides the frequency of an input signal at the VCO pin by the values specified in the swallow counter and programmable counter. The swallow and programmable counters consist of a 4- and 12-bit binary downcounter, respectively. The swallow and programmable counters are loaded with a division value by setting it in the PLL data register (PLLR, at address 41H) through the data buffer (DBF).
µPD17062 18.4 18.4.1 REFERENCE FREQUENCY GENERATOR (RFG) Reference Frequency Generator (RFG) Configuration and Functions Fig. 18-3 shows the configuration of the reference frequency generator. As shown in Fig. 18-3, the reference frequency generator divides the frequency of the clock oscillator (8 MHz) to generate the reference frequency “fr” for the PLL frequency synthesizer. The reference frequency fr can be selected from 6.25, 12.5, and 25 kHz.
µPD17062 18.4.2 PLL Reference Mode Select Register Configuration and Functions Fig. 18-4 shows the configuration and functions of the PLL reference mode select register. When the PLL reference mode select register selects the PLL disable mode, the VCO pin is pulled down internally, and the EO pin floats. See Section 18.6 for the PLL disable mode. Fig.
µPD17062 18.5 18.5.1 PHASE COMPARATOR (φ-DET), CHARGE PUMP, AND UNLOCK DETECTION BLOCK Configuration of the Phase Comparator (φ-DET), Charge Pump, and Unlock Detection Block Fig. 18-5 shows the configuration of the phase comparator (φ-DET), charge pump, and unlock detection block.
µPD17062 18.5.2 Functions of the Phase Comparator (φ-DET) As shown in Fig. 18-5, the phase comparator compares the phase of the output frequency “fN” of the programmable divider (PD) and the phase of the reference frequency “fr”, and outputs the up request signal (UP) or down request signal (DW). If the divider output frequency fN is lower than the reference frequency fr, the phase comparator outputs an up request. If fN is higher than fr, the phase comparator outputs a down request. Fig.
µPD17062 Fig.
µPD17062 18.5.3 Charge Pump As shown in Fig. 18-5, the charge pump directs the up request signal (UP) or down request signal (DW) from the phase comparator (φ-DET) to the error output pin (EO) pin.
µPD17062 (1) PLL unlock FF judge register (PLLULJDG) This register is a read-only register. It is reset when its content is read into a window register (WR) with a PEEK instruction. Because the unlock FF is set at intervals of the period (1/fr) of the reference frequency fr, the content of this register must be read into the window register at intervals larger than the period of the reference frequency. Fig.
µPD17062 (2) PLL unlock FF delay control register (PLULSEN) When the unlock FF disable mode is selected, the unlock FF remains set. So, note that if the PLL unlock FF judge register checks the unlock FF in the unlock FF disable mode, it always appears to be unlocked (PLLUL flag = 1). Fig.
µPD17062 18.6 PLL DISABLE MODE The PLL frequency synthesizer is disabled when the CE pin is at a low level. It is also disabled when the PLL reference mode select register (PLRFMODE, at address 13H) selects the PLL disable mode. Table 18-1 summarizes how each block operates during the PLL disable mode.
µPD17062 18.7 SETTING DATA FOR THE PLL FREQUENCY SYNTHESIZER The following data is necessary to control the PLL frequency synthesizer. (1) Reference frequency : fr (2) Division value : N The following paragraphs explain how to set the PLL data. (1) Setting reference frequency fr The reference frequency is specified according to the PLL reference mode select register.
µPD17062 19. A/D CONVERTER The µPD17062 contains a 4-bit program-controlled A/D converter that operates with a successive comparison method. 19.1 PRINCIPLE OF OPERATION The A/D converter in the µPD17062 consists of a 4-bit resistor string-based D/A converter and comparator. The D/A converter is set with data using a 4-bit register (ADCR) mapped at peripheral address 02H. The result of comparison is judged according to the ADCCMP flag in the register file. Fig.
µPD17062 19.2 D/A CONVERTER CONFIGURATION The D/A converter used in the A/D converter of the µ PD17062 is a resistor string D/A converter consisting of 16 resistors connected in series between the VDD and GND pins in which a voltage at each resistor connection point is selected. The configuration of the D/A converter is shown in Fig. 19-2. Fig.
µPD17062 19.3 REFERENCE VOLTAGE SETTING REGISTER (ADCR) The ADCR is a 4-bit register to specify a reference voltage for the A/D converter. It is mapped at peripheral address 02H. Data is written to and read from the ADCR register through the data buffer using the “PUT” and “GET” instructions respectively. The data transfer between the ADCR and DBF is performed in 8-bit units although the ADCR is a 4-bit register. In other words, 8-bit data is transferred through the DBF1 (0EH) and DBF0 (0FH).
µPD17062 19.5 ADC PIN SELECT REGISTER (ADCCHn) The ADCCHn register selects an A/D converter input pin. It is mapped at the upper 3 bits of the register file at address 21H. Table 19-2 lists the relationships between the ADCCHn and the actually selected pins.
µPD17062 19.6 EXAMPLE OF A/D CONVERSION PROGRAM The following example shows an A/D conversion program based on the successive comparison method. The result of conversion is held in the DBF0. Sample program DBF0B3 FLG 0.0FH.3 DBF0B2 FLG 0.0FH.2 DBF0B1 FLG 0.0FH.1 DBF0B0 FLG 0.0FH.0 START: BANK0 INITFLG DBF0B3, NOT DBF0B2, NOT DBF0B1, NOT DBF0B0 ; Sets DBF data. PUT ADCR, DBF ; Sets reference voltage. SKT1 ADCCMP ; Judges comparison result.
µPD17062 Flowchart START Sets DBF data. DBF←1000B Begins AD conversion. ADCR←DBF ADCCMP Sets reference voltage. 1 Judges comparison result. 0 DBF0B3←0 DBF0B3←0 DBF0B2←1 DBF0B2←1 ADCR←DBF Sets reference voltage. ADCCMP 1 Judges comparison result.
µPD17062 1 ADCR←DBF ADCCMP Sets reference voltage. 1 Judges comparison result. 0 DBF0B1←0 DBF0B1←0 DBF0B0←1 DBF0B0←1 ADCR←DBF Sets reference voltage. ADCCMP 1 Judges comparison result.
µPD17062 20. IMAGE DISPLAY CONTROLLER The image display controller (IDC) function indicates a channel number, volume of sound, time, and other information on a TV screen. The pattern of a display is user-programmable, and the display pattern definition is stored in the CROM area. The pattern to be actually displayed is stored in VRAM, which is mapped at BANK1 and BANK2 in data memory. 20.
µPD17062 (4) Rounding, rimming, and reverse video can be specified for individual characters. No rimming Rimming Rounding Reverse video Color specification by R, G, and B Blank (black) Background (TV screen) (5) Number of fonts: 120 (user-programmable) The number of fonts that can be displayed on one screen simultaneously is limited to within 64.
µPD17062 (6) Up to 4 different character sizes, both vertical and horizontal, are available. The same vertical character size is specified for all characters in a row, while the horizontal character size is specified for individual characters (according to the control dataNote 1). (7) The character bit configuration is 10 × 15 dots. There is no gap between character positions.Note 2 (8) Character pattern data is allocated in program memory.
µPD17062 20.2 DIRECT MEMORY ACCESS The direct memory access (DMA) function transfers memory contents directly to peripheral equipment, without using the CPU. In the µPD17062, the DMA mode is used to run the IDC. The instruction cycle of the µPD17062 is 2 µs, but its apparent instruction cycle becomes 12 µs during the DMA mode.
µPD17062 Sample program Instruction cycle: 2 µ s *1 SET1 CLR1 *2 IDCDMAEN PEEK WR, 80H OR WR, #0010B POKE 80H, WR PEEK WR, 80H AND WR, #1101B POKE 80H, WR Instruction cycle: 12 µs IDCDMAEN Instruction cycle: 2 µ s Remark The “SET1” or “CLR1” is not included in the µPD17062 instruction set. They are a built-in macro instruction of the 17K series assembler. They set or reset a one-bit flag.
µPD17062 20.3 IDC ENABLE FLAG The IDCEN (IDC enable) flag is manipulated to start IDC operations (turn on the display). The flag is mapped at the lowest bit (#0) of the register file at 31H. Table 20-2 b3 b2 b1 b0 0 0 0 IDCEN IDCEN Flag (RF 31H) 0 Turns off the display. 1 Turns on the display.
µPD17062 20.4 VRAM VRAM is the memory that holds data used to select a picture pattern that the IDC displays on a screen such as a TV screen. In the µPD17062, the VRAM data is allocated at BANK1 and BANK2 in data memory. One VRAM data item (8 bits) is held at two adjoining addresses (even and odd address). BANK1 and BANK2 are each mapped at 112 nibbles of data memory (total of 224 nibbles, or 224 × 4 bits). That is, up to 112 VRAM data items can be specified. Fig.
µPD17062 Fig. 20-2 VRAM Data Configuration Even address b7 b6 b5 b4 b3 b2 b1 b0 (b3) (b2) (b1) (b0) (b3) (b2) (b1) (b0) ID field 20.4.1 Odd address Data field ID Field The ID field indicates the type of data in the data field. The data field can hold the following three types of data. (1) Character pattern select data (2) Carriage return data (3) Control data select data Table 20-3 ID Field ID field 20.4.
µPD17062 Table 20-4 VRAM Data (Character Pattern Select Data) versus CROM Addresses CROM address VRAM data (8 bits) BANK0 00H 248 CROM address BANK1 VRAM data (8 bits) BANK0 BANK1 0800H-080EH 0C00H-0C0EH 20H 0A00H-0A0EH 0E00H-0E0EH 01H 0810H-081EH 0C10H-0C1EH 21H 0A10H-0A1EH 0E10H-0E1EH 02H 0820H-082EH 0C20H-0C2EH 22H 0A20H-0A2EH 0E20H-0E2EH 03H 0830H-083EH 0C30H-0C3EH 23H 0A30H-0A3EH 0E30H-0E3EH 04H 0840H-084EH 0C40H-0C4EH 24H 0A40H-0A4EH 0E40H-0E4EH 05H 0850H-085E
µPD17062 Sample program VRAM data 0 0 1 2 3 4 5 6 7 8 0 0 0 0 1 4 0 8 9 A B 1 CROM data 0800H “C” ; Control data 1 080FH 0810H “H” ; Control data 2 081FH 0C00H “V” ; Control data 1 0C0FH 0C10H “O” 0C1FH ; Control data 2 If the CROM data and VRAM data are specified as shown above, the display on the screen varies depending on the CROM bank. The CROM bank is specified by CROMBNK (b0 at 30H). The following description applies to the above example.
µPD17062 20.4.3 Carriage Return Data The term carriage return data refers to the data pointing to the address of the VRAM data that specifies the first character in a row on the screen. The carriage return data specifies the end of a display row. When carriage return data appears two times consecutively, it specifies the end of a screen. There are two types of carriage return data; one type is a carriage return to BANK1, and the other is a carriage return to BANK2.
µPD17062 Fig.
µPD17062 20.4.4 Control Data Select Data The term control data refers to the data that specifies the character size, display position, and color of a character pattern on the screen. This data is held in CROM (at ×××FH). The control data select data is held in VRAM and selects control data in CROM. The 6 bits of the data field correspond to b9 to b4 of the CROM address. Similarly to the pattern select data, the control data select data also requires that a CROM bank be specified.
µPD17062 Table 20-5 VRAM Data (Control Data Select Data) versus CROM Addresses CROM address VRAM data (8 bits) BANK0 80H 81H CROM address BANK1 VRAM data (8 bits) BANK0 BANK1 080FH 0C0FH A0H 0A0FH 0E0FH 081FH 0C1FH A1H 0A1FH 0E1FH 82H 082FH 0C2FH A2H 0A2FH 0E2FH 83H 083FH 0C3FH A3H 0A3FH 0E3FH 84H 084FH 0C4FH A4H 0A4FH 0E4FH 85H 085FH 0C5FH A5H 0A5FH 0E5FH 86H 086FH 0C6FH A6H 0A6FH 0E6FH 87H 087FH 0C7FH A7H 0A7FH 0E7FH 88H 088FH 0C8FH A8H 0A8FH 0
µPD17062 20.4.5 Cautions in Specifying VRAM Data (1) Reset the IDCEN flag to 0 before specifying VRAM data. (2) The VRAM data must begin at 00H in BANK1. (3) Do not set VRAM data at 7×H in BANK1 or BANK2. (4) Always set control data at the beginning of a screen. To prevent a program error, control data should be set at the beginning of each row. Otherwise, the previous control data remains effective.
µPD17062 20.5 CHARACTER ROM The CROM (character ROM) consists of the IDC pattern data and control data. The CROM data shares the program memory with programs. The CROM area has a capacity of 2 Ksteps (1920 × 16 bits). An area not used as CROM is used as an ordinary program area. The CROM area in ROM is at 0800H to 0F7FH. The CROM area is divided into BANK0 and BANK1. A concept of bank applies only to CROM. It does not apply to a program area.
µPD17062 Fig. 20-6 Character Pattern Data Configuration (a) Data for a character with no rimming b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 Undefined b5 b4 b3 b2 b1 b0 b2 b1 b0 Character pattern data 0 (b) Data for a character with rimming b15 b14 b13 b12 b11 b10 b9 b8 b7 Character pattern data b6 b5 b4 b3 Rim data 1 If 2 is to be displayed, the character pattern is set as shown in Fig. 20-7. 0 and 1 in the pattern data correspond to ■ and ■, respectively.
µPD17062 Fig.
µPD17062 20.5.2 Control Data The control data specifies the display position, size, and color of a character pattern. It is stored at ×××FH in the CROM area. One control data item consists of 16 bits. The highest bit is always 0. Fig. 20-9 shows the configuration of the control data. Fig.
µPD17062 (2) Vertical size data (b12 and b11 of the control data) The vertical size data determines the vertical size of each image of a character. Up to four sizes can be specified on each row. Table 20-8 lists details of the vertical size data. The vertical size data specified at the beginning of a row is effective throughout that row. The vertical size data in any other control data for the same row is ignored.
µPD17062 (4) Vertical position data (b6 to b3 of the control data) The vertical position data specifies which of the 12 rows (vertical positions) shown in Fig. 20-10 the display is to begin at. The vertical position data consists of four bits of the control data, with b6 corresponding to the MSB and b3 corresponding to the LSB, and it takes a value from 0H to DH. Value 0H corresponds to row 0, and value DH to column 13.
µPD17062 (5) Color data (b2 to b0 of the control data) The color data specifies the color of a display character. It is output from a specified output pin (R, G, or B pin). Table 20-9 lists the correspondence between the color data and the output pins. Table 20-10 summarizes the relationships between the color data setting and output colors.
µPD17062 20.5.3 Defining Display Patterns with an Assembler With the 17K series assembler, the DCP pseudo instruction can be used to define display patterns easily. How to use the DCP pseudo instruction is described below. (1) Instruction format Symbol field Mnemonic field Operand field Comment field [Label:] DCP expression, ‘display pattern’ [; comment] (2) Explanation (a) The expression takes value 0 or 1.
µPD17062 20.6 BLANK, R, G, AND B PINS All these pins are CMOS push-pull output pins. They output an active-high signal. The BLANK pin outputs a signal to turn off a broadcasting picture. The R, G, and B pins output character pattern data. If rimming is not specified, the BLANK signal is the same as the character pattern signal (generated by ORing the R, G, and B signals). If rimming is specified, the BLANK signal output from the BLANK pin is a waveform enveloping the character pattern signal. Fig.
µPD17062 20.7 SPECIFYING THE DISPLAY START POSITION IDC display start positions (upper left of the screen) can be specified by setting data in the IDC start position setting register. Up to 16 horizontal and vertical positions can be specified. In other words, the display position of the entire screen can be shifted. The IDC start position setting register consists of a 4-bit vertical start position setting register and a 4-bit horizontal start position setting register.
µPD17062 20.7.1 Horizontal Start Position Setting Register If the horizontal start position setting register contains 0H, the horizontal start position is set 4.25 µs after the trailing edge of the horizontal sync signal. Each time the horizontal start position setting register is incremented by one, the horizontal start position shifts to the right by 250 ns; namely the following expression applies. Horizontal start position = 4.25 µs + 250 ns × (horizontal start position setting data) In Fig.
µPD17062 20.7.2 Vertical Start Position Setting Register If the vertical start position setting register contains 0H, the vertical start position is set 17 H (interlace) after the trailing edge of the vertical sync signal. Each time the vertical start position setting register is incremented by one, the vertical start position shifts down by 1 H; namely the following expression applies. Vertical start position = 17 H + 1 H × (vertical start position setting data) In Fig.
µPD17062 The vertical start position of the display character is determined by the vertical start position register. At this point, the vertical start position (number of horizontal scan lines) depends on the state of the VSYNC and HSYNC signals supplied to the µPD17062, as shown in Fig. 20-15. In other words, the first HSYNC signal that comes after the VSYNC signal rises is counted as 1 H. Fig.
µPD17062 20.8 SAMPLE PROGRAMS The following sample program generates a display shown below. Column 0 1 2 3 4 5 6 7 8 9 10 11 12 C H 13 14 Column 15 0 2 Row 0 1 2 3 4 CH 02 Row 5 NEC ....... Display on the TV screen The RAM names of VRAM are defined as follows (tentative): ; * * RAM SET * * VRAM0 MEM 2.00H VRAM1 MEM 2.01H VRAM2 MEM 2.02H VRAM3 MEM 2.03H VRAM4 MEM 2.04H VRAM5 MEM 2.05H VRAM6 MEM 2.06H VRAM7 MEM 2.07H VRAM8 MEM 2.08H VRAM9 MEM 2.
µPD17062 The sample program follows: Program start ; Performs initialization such as clearing RAM. Initialization SET1 IDCDMAEN ; Selects the DMA mode. CLR1 IDCEN ; Turns off the display. ; ; ** Channel display routine ** ; CLR1 CROMBNK ; Sets the CROM bank to 0. MOV VRAM0, #1000B ; Specifies control code 1.
µPD17062 At point #, the contents of VRAM (BANK2) are as follows: 0 0 1 2 3 4 5 6 7 8 9 A B C D E F 8 0 0 C 0 D 8 1 0 0 0 2 4 0 4 0 1 For this example, the contents of CROM are as follows: CROM DATA ; * * * * * * * * * * * * * * * * * * * * * * * * Image Display Controller data set ; * * * ROM ADDRESS * * * ; * * * * * * * * * * * * * * * * * * * * * * * * ORG 0 8 0 0 0800H ; * * * * * * * * ; * * * *0 * * * * ; * * * * * * * * 0 8 0 0 0 0 0 0 DCP 0, ' ' 0 8 0 1
µPD17062 ; * * * * * * * * ; * * * *1 * * * * ; * * * * * * * * ' 0 8 1 0 0 0 0 0 DCP 0 , ' 0 8 1 1 0 0 0 6 DCP 0 , ' OO ' 0 8 1 2 0 0 0 E DCP 0 , ' OO ' 0 8 1 3 0 0 1 E DCP 0 , ' OOOO ' 0 8 1 4 0 0 7 6 DCP 0 , ' OOOO ' 0 8 1 5 0 0 C 6 DCP 0 , ' OO ' 0 8 1 6 0 1 8 6 DCP 0 , ' OO ' 0 8 1 7 0 0 0 6 DCP 0 , ' OO ' 0 8 1 8 0 0 0 6 DCP 0 , ' OO ' 0 8 1 9 0 0 0 6 DCP 0 , ' OO ' 0 8 1 A 0 0 0 6 DCP 0 , ' OO ' 0 8 1 B 0 0 0 6 DCP 0 , ' OO ' 0 8 1 C 0 0 0 6
µPD17062 ; * * * * * * * * ; * * * *3 * * * * ; * * * * * * * * 0 8 3 0 0 0 0 0 DCP 0, ' 0 8 3 1 0 0 7 C DCP 0, ' OOOOO ' 0 8 3 2 0 0 F E DCP 0, ' OOOOOOO ' 0 8 3 3 0 1 C 7 DCP 0, ' OOO OOO ' 0 8 3 4 0 1 8 3 DCP 0, ' OOO OO ' 0 8 3 5 0 0 0 3 DCP 0, ' ' ; “3” OO ' ; * * * * * * * * ; * * * *C * * * * ; * * * * * * * * 0 8 C 0 0 0 0 0 DCP 0, ' 0 8 C 1 0 0 7 F DCP 0, ' OOOOO ' 0 8 C 2 0 0 F F DCP 0, ' OOOOOOO ' 0 8 C 3 0 1 C 0 DCP 0, ' OOO OOO ' 0 8 C 4 0 1 8 0
µPD17062 ; * * * * * * * * ; * * * *H * * * * ; * * * * * * * * RO M ADDRESS 0 8 D 0 0 0 0 0 DCP 0, ' 0 8 D 1 0 1 8 3 DCP 0, ' OO OO ' 0 8 D 2 0 1 8 3 DCP 0, ' OO OO ' 0 8 D 3 0 1 8 3 DCP 0, ' OO OO ' 0 8 D 4 0 1 8 3 DCP 0, ' OO OO ' 0 8 D 5 0 1 8 3 DCP 0, ' OO OO ' 0 8 D 6 0 1 8 3 DCP 0, ' OO OO ' 0 8 D 7 0 1 F F DCP 0, ' OOOOOOOOO ' 0 8 D 8 0 1 F F DCP 0, ' OOOOOOOOO ' 0 8 D 9 0 1 8 3 DCP 0, ' OO OO ' 0 8 D A 0 1 8 3 DCP 0, ' OO OO ' 0 8 D B 0 1 8 3 DC
µPD17062 21. HORIZONTAL SYNC SIGNAL COUNTER 21.1 HORIZONTAL SYNC SIGNAL COUNTER CONFIGURATION The horizontal sync signal counter counts the frequency of a horizontal sync signal for TV or similar equipment. When a TV broadcasting signal is received, a prescribed horizontal sync signal is output. Using this fact, the horizontal sync signal counter checks whether there is a broadcast station at a particular frequency.
µPD17062 21.2 GATE CONTROL REGISTER (HSCGT) The gate control register is a 2-bit register consisting of the HSCGT1 and HSCGT0 flags used to control the gate. It is mapped in the register file at 11H. The gate control register can be read- and write-accessed through the window register (system register) using the PEEK and POKE instructions, respectively. The following modes can be set up using the gate control register.
µPD17062 21.3 HSYNC COUNTER (HSC) The HSYNC counter is mapped at peripheral address 04H. It is a 6-bit read-only binary counter. It can be read-accessed through the data buffer using the GET instruction. When it overflows, the 6-bit HSYNC counter goes back to 00H. The HSYNC counter is reset to 00H at a power-on reset and clock stop. (1) Gate open bit (HSCGOSTT) The HSCGOSTT is mapped at the MSB (b3) of the register file at 12H. It is always high when the gate with the Hsync input is open.
µPD17062 22. INSTRUCTION SETS 22.
µPD17062 22.
µPD17062 22.
µPD17062 Instruction code Instruction set Mnemonic Transfer PUSH AR SP ← SP – 1, ASR ← AR 00111 000 1101 0000 POP AR AR ← ASR, SP ← SP + 1 00111 000 1100 0000 PEEK WR, rf WR ← (rf) 00111 rfR 0011 rfC POKE rf, WR (rf) ← WR 00111 rfR 0010 rfC GET DBF, p DBF ← (p) 00111 pH 1011 pL PUT p, DBF (p) ← DBF 00111 pH 1010 pL BR addr PC10-0 ← addr, PAGE ← 0 01100 PC10-0 ← addr, PAGE ← 1 01101 @AR PC ← AR 00111 addr SP ← SP – 1, ASR ← PC, PC11 ← 0, PC10-0 ← addr
µPD17062 22.4 BUILT-IN MACRO INSTRUCTIONS The following macro instructions are built in the 17K series assembler (AS17K). For details, refer to the assembler user’s guide. Legend flag n : FLG-type symbol <> : An operand enclosed in < > is optional.
µPD17062 23. RESERVED SYMBOLS FOR ASSEMBLER The reserved µPD17062 symbols for the assembler are listed below. 23.1 SYSTEM REGISTER Attribute Value Read/ write AR3 MEM 0.74H R Bits 15 to 12 of the address register AR2 MEM 0.75H R Bits 11 to 8 of the address register AR1 MEM 0.76H R/W Bits 7 to 4 of the address register AR0 MEM 0.77H R/W Bits 3 to 0 of the address register WR MEM 0.78H R/W Window register BANK MEM 0.79H R/W Bank register IXH MEM 0.
µPD17062 23.3 PORT REGISTER Symbol Attribute Value Read/ write Description P0A3 FLG 0.70H.3 R/W Bit 3 of port 0A P0A2 FLG 0.70H.2 R/W Bit 2 of port 0A P0A1 FLG 0.70H.1 R/W Bit 1 of port 0A P0A0 FLG 0.70H.0 R/W Bit 0 of port 0A P0B3 FLG 0.71H.3 R/W Bit 3 of port 0B P0B2 FLG 0.71H.2 R/W Bit 2 of port 0B P0B1 FLG 0.71H.1 R/W Bit 1 of port 0B P0B0 FLG 0.71H.0 R/W Bit 0 of port 0B P0C3 FLG 0.72H.3 R/W Bit 3 of port 0C P0C2 FLG 0.72H.
µPD17062 23.4 REGISTER FILES Symbol Attribute IDCDMAEN FLG Value Read/ write 0.80H.1 R/W DMA enable flag 0.81H R/W Stack pointer Description SP MEM CE FLG 0.87H.0 R SIO0CH FLG 0.88H.3 R/W SIO0 channel selection flag SB FLG 0.88H.2 R/W SIO0 mode selection flag SIO0MS FLG 0.88H.1 R/W SIO0 clock mode selection flag SIO0TX FLG 0.88H.0 R/W SIO0 TX/RX selection mode BTM0ZX FLG 0.89H.3 R/W Timer 0 interrupt mode selection flag BTM0CK2 FLG 0.89H.
µPD17062 Attribute Value Read/ write SIO0SF8 FLG 0.0A8H.3 R SIO0 shift 8 clock flag SIO0SF9 FLG 0.0A8H.2 R SIO0 shift 9 clock flag SBSTT FLG 0.0A8H.1 R Serial bus start test flag SBBSY FLG 0.0A8H.0 R Serial bus busy flag IPSIO0 FLG 0.0AFH.3 R/W SIO0 interrupt permission flag IPVSYN FLG 0.0AFH.2 R/W Vsync interrupt permission flag IPBTM0 FLG 0.0AFH.1 R/W Timer 0 interrupt permission flag IPNC FLG 0.0AFH.0 R/W INTNC interrupt permission flag CROMBNK FLG 0.0B0H.
µPD17062 23.
µPD17062 24. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (Ta = 25 ±2 °C) Parameter Symbol Rated value Unit Supply voltage VDD –0.3 to +6.0 V Input voltage VI –0.3 to VDD + 0.3 V Output voltage VO –0.3 to VDD + 0.
µPD17062 AC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 5 V ±10 %, RH ≤ 70 %) Parameter Operating frequency Symbol Conditions Min. Sine wave input Vin = 0.7 VP-P Typ. Max. Unit 0.7 20 MHz fin1 VCO fin2 TMIN 45 65 Hz fin3 HSCNT 10 20 kHz 8.0 ns IDC jitter IDCG 4.0 IDC horizontal start position IDCHP From trailing edge of HSYNC 4.
µPD17062 25. PACKAGE DRAWINGS 48PIN PLASTIC SHRINK DIP (600 mil) 48 25 1 24 A K L I J H G F D C N M NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) ltem "K" to center of leads when formed parallel. M R B ITEM MILLIMETERS INCHES A B 44.46 MAX. 1.78 MAX. 1.751 MAX. 0.070 MAX. C 1.778 (T.P.) 0.070 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 0.85 MIN. 0.033 MIN. G H 3.2±0.3 0.51 MIN. 0.126±0.012 0.
µPD17062 64 PIN PLASTIC QFP ( 14) A B 48 49 33 32 F 64 1 G R Q S D C detail of lead end 17 16 H I M J M P K N L NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 17.2±0.2 0.677±0.008 B 14.0±0.2 0.551 +0.009 –0.008 C 14.0±0.2 0.551 +0.009 –0.008 D 17.2±0.2 0.677±0.008 F 1.0 0.039 G 1.0 0.039 H 0.35±0.10 0.014 +0.004 –0.005 I 0.13 0.005 J 0.8 (T.P.) 0.031 (T.
µPD17062 26. RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering the µPD17062. For details of the recommended soldering conditions, refer to our document SMD Surface Mount Technology Manual (IEI-1207). Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions.
µPD17062 APPENDIX DEVELOPMENT TOOLS The following support tools are available for developing programs for the µPD17062. Hardware Name Description In-circuit emulator IE-17K IE-17K-ETNote 1 EMU-17KNote 2 The IE-17K, IE-17K-ET, and EMU-17K are in-circuit emulators applicable to the 17K series. The IE-17K and IE-17K-ET are connected to the PC-9800 series (host machine) or IBM PC/ATTM through the RS-232-C interface. The EMU-17K is inserted into the extension slot of the PC-9800 series (host machine).
µPD17062 Software Description Name 17K series assembler (AS17K) AS17K is an assembler applicable to the 17K series. In developing µPD17062 programs, AS17K is used in combination with a device file (AS17062). Device file (AS17062) AS17062 is a device file for the µPD17062 . It is used together with the assembler (AS17K), which is applicable to the 17K series.
µPD17062 [MEMO] 294
µPD17062 Cautions on CMOS Devices # Countermeasures against static electricity for all MOSs Caution When handling MOS devices, take care so that they are not electrostatically charged. Strong static electricity may cause dielectric breakdown in gates. When transporting or storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during assembling.
µPD17062 Caution This product contains an I2C bus interface circuit. When using the I2C bus interface, notify its use to NEC when ordering custom code. NEC can guarantee the following only when the customer informs NEC of the use of the interface: Purchase of NEC I2 C components conveys a license under the Philips I2 C Patent Rights to use these components in an I2 C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
