MOS Integrated Circuit Data Sheet

163
µ PD17062
Example
HLTINT DAT 1000B ; Defines a symbol.
START: ; Address 0000H
BR MAIN ;
NOP
INTTM: ; Timer interrupt vector address (0003H)
BR INTTIMER ; Branches to INTTIMER (interrupt handling).
INT0: ; INT
NC pin interrupt vector address (0004H)
Process A ; Interrupt requested at the INT
NC pin
EI
RETI
INTTIMER:
Process B ; Timer interrupt handling
EI
RETI
MAIN:
SET2 IPBTM0, IPNC ; Built-in macro
; Enables INT
NC pin and timer interrupts.
SET1 BTM0CK2 ; Built-in macro
LOOP: ; Specifies the timer interrupt time interval as 5 ms.
Process C ; Main routine processing
EI ; Enables all interrupts.
HALT HLTINT ; Specifies an interrupt as a halt release condition.
;
BR LOOP
This sample program releases the halt state and performs process B when a timer interrupt request is
accepted. When an interrupt request at the INT
NC pin is issued, the program performs process A. It also
performs process C each time the halt state is released.
If an INTNC pin interrupt is requested exactly at the same time with a timer interrupt during the halt state,
the program performs process A for the INT
NC pin interrupt, which has a higher hardware priority than the
timer interrupt. When a RETI instruction is executed upon completion of process A, program control is
returned to the BR LOOP instruction at , but this instruction will not be executed. Instead, the timer interrupt
request is accepted immediately. The BR LOOP instruction is executed only after a RETI is executed upon
completion of process B (timer interrupt handling).