MOS Integrated Circuit Data Sheet

169
µ PD17062
13.6.2 Cautions in Processing of Each Pin During Halt or Clock Stop State
The halt function is intended to reduce the required current drain, for example, by allowing only the clock
to operate. Meanwhile, the clock stop function is intended to reduce the required current drain by suspending
all operations except preservation of data in memory. During the halt or clock stop state, therefore, it is
necessary to reduce the required current drain as much as possible. Because the current drain varies with
the state of each pin, it is necessary to take cautions listed in Table 13-2.
Table 13-2 State of Each Pin During the Halt or Clock Stop State and Cautions to Be Taken (1/2)
These pins are specified as general-
purpose input ports. All input ports
except the P0A1/SCL and P0A0/SDA
pins are designed so that even if
they are floating externally, the
current drain will not increase due to
noise. For the P0A1/SCL and P0A0/
SDA pins, an external pull-down
resistor or pull-up resistor must be
connected to keep the current drain
from increasing.
Port 0D (P0D3/ADC5 to P0D0/ADC2)
are pulled down internally.
These pins are specified as general-
purpose ports.
The outputs are preserved.
Therefore, if they are pulled down
externally during high-level output
or pulled up during low-level output,
the current drain will increase.
The state that exists before the execution
of the halt instruction continues.
(1) When the port is specified as output
If the pin pulled down externally during
high-level output or pulled up externally
during low-level output, the current drain
increases.
Be careful especially for N-channel
open-drain outputs (P0A1, P0A0, P1A3 to
P1A0).
(2) When the port is specified as input
When the pin is floating, the current
drain increases due to noise.
(3) Port 0D (P0D3/ADC7 to P0D0/ADC4)
Because the pin is already pulled down
internally, the current drain will increase if
it is pulled up externally. If the pin is
selected for A/D converter, however, the
internal pull-down resistor is disconnected.
(4) Port0B (P0B3/HSCNT to P0B0/SI) and
port1B (P1B3/P1B0)
When the P0B3/HSCNT pin operates as
the HSYNC counter or when the P1B3 pin
operates as an external timer input, the
built-in self-bias circuit operates, resulting
in an increase in the current drain.
P0A3/SO
P0A2/SCK
P0A1/SCL
P0A0/SDA
P0B3/HSCNT
P0B2/TMIN
P0B1
P0B0/SI
P1B3
P1B2
P1B1
P1B0
P1C3/ADC1
P1C2
P1C1
P0D3/ADC5
P0D2/ADC4
P0D1/ADC3
P0D0/ADC2
P0C3
P0C2
P0C1
P0C0
General-purpose
output port
General-purpose
input port
General-purpose input/output port
Port0A
Port0B
Port1B
Port1C
Port0D
Port0C
Clock stop state
State of each pin and cautions in processing
Halt state
Pin symbol
Pin function