MOS Integrated Circuit Data Sheet

78
µ PD17062
9.7 INTNC (0FH, b0)
The INT
NC flag is used for reading the INTNC pin state.
The flag indicates 1 when a high level signal is input to the INT
NC pin, and 0 when a low level signal is input
to the INT
NC pin.
9.8 HORIZONTAL SYNCHRONIZING SIGNAL COUNTER CONTROL (11H, 12H)
b3 b2 b1 b0
0 INTVSYN INTNC
0FH
0
0
1
0
1
The VSYNC pin is low level.
The VSYNC pin is in the high level period.
The INTNC pin is low level.
The INTNC pin is high level.
b3 b1 b0
HSCGOSTT 0
12H
0
0
1
b3 b2 b1 b0
HSCGT3 HSCGT2 HSCGT0
11H
HSCGT1
0
0
1
1
0
1
0
1
0
b
2
Input confirmation of gate open/close of
horizontal synchronizing signal counter
Both bits are fixed at 0.
Gate close
Gate open
Gate open (1.69 ms interval)
Not to be set
Gate close
Gate open
Setting of horizontal synchronizing signal counter