User's Manual
112
µPD750008 USER'S MANUAL
Figure 5-30. Timer/Event Counter Mode Register (Channel 0) Format
When f
X
= 4.19 MHz
TM05
0
0
0
0
1
1
TM06
0
0
1
1
1
1
TM04
0
1
0
1
0
1
TI0 rising edge
TI0 falling edge
f
X
/2
10
(4.09 kHz)
f
X
/2
8
(16.4 kHz)
f
X
/2
6
(65.5 kHz)
f
X
/2
4
(262 kHz)
Not to be set
Count pulse (CP)
Other than above
Address
FA0H
76
TM06
5
TM05
4
TM04
3
TM03
2
TM02
1 0 Symbol
TM0
TM03
Timer start indication bit
When 1 is written into the bit, the counter and IRQT0 flag are cleared.
If bit 2 is set to 1, count operation is started.
TM02
0
1
Operation mode
Stop (retention of count contents)
Count operation
Count operation
Count pulse (CP) selection bit
When f
X
= 6.00 MHz
TM05
0
0
0
0
1
1
TM06
0
0
1
1
1
1
TM04
0
1
0
1
0
1
TI0 rising edge
TI0 falling edge
f
X
/2
10
(5.86 kHz)
f
X
/2
8
(23.4 kHz)
f
X
/2
6
(93.8 kHz)
f
X
/2
4
(375 kHz)
Not to be set
Count pulse (CP)
Other than above