DATA SHEET MOS INTEGRATED CIRCUIT µPD75P308 4-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION The µPD75P308 is a model of the µPD75308 equipped with a one-time PROM or EPROM instead of an internal mask ROM. Two types are available as the µ PD75P308. The one-time PROM type is ideal for production of a small quantity of many different types of application systems as data can only be written once to the one-time PROM of this type.
µPD75P308 P71/KR5 P72/KR6 P73/KR7 RESET S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 P70/KR4 S13 2 63 P63/KR3 S14 3 62 P62/KR2 S15 4 61 P61/KR1 S16 5 60 P60/KR0 S17 6 59 X2 S18 7 58 X1 S19 8 57 VPP S20 9 56 XT2 S21 10 55 XT1 S22 11 54 VDD S23 12 53 P33 (MD3) S24/BP0 13 52 P32 (MD2) S25/BP1 14 51 P31/SYNC (MD1) S26/BP2 15 50 P30/LCDCL (MD0) S27/BP3 16 49 P23/BUS S28/BP4 17 48 P22/PCL S29/BP
PROGRAM COUNTER(13) INTBT TI0/P13 SP(8) ALU TIMER/EVENT COUNTER #0 PTO0/P20 BANK WATCH TIMER INTW SI/SBI/P03 fLCD PROGRAM MEMORY (PROM) GENERAL REG.
µ PD75P308 CONTENTS 1. ★ PIN FUNCTIONS ................................................................................................................................. 5 1.1 PORT PINS ................................................................................................................................................. 5 1.2 NON PORT PINS ....................................................................................................................................... 6 1.
µPD75P308 1. PIN FUNCTIONS 1.1 PORT PINS Pin Name Input/Output P00 Also Served As Input Input/Output SCK P02 Input/Output SO/SB0 P03 Input/Output SI/SBI P12 INT1 Input TI0 P20 PTO0 Input/Output P22 P23 P30*2 P31*2 P32*2 P33*2 P40-43*2 P50-P53*2 P61 — PCL KR0 Input/Output KR1 P62 KR2 P63 KR3 P70 KR4 P71 P72 Input/Output KR5 KR6 P73 KR7 BP0 S24 BP1 BP2 X Input F -A F -B M -C 4-bit input port (PORT1) Internal pull-up resistors can be specified in 4-bit units by software.
µ PD75P308 1.
µPD75P308 1.3 PIN INPUT/OUTPUT CIRCUITS The following shows a simplified input/output circuit diagram for each pin of the µ PD75P308. TYPE D (for TYPE E–B, F-A) TYPE A (for TYPE E–B) VDD data P–ch P–ch OUT IN output disable N–ch Input buffer of CMOS standard N–ch Push–pull output that can be set in a output high–impedance state (both P–ch and N–ch are off) TYPE E–B TYPE B VDD P.U.R. P.U.R.
µ PD75P308 TYPE F–A TYPE G–B VDD V LC0 P-ch P.U.R. enable P–ch V LC1 data P-ch N-ch IN/OUT Type D output disable OUT COM data N-ch P-ch Type B V LC2 P.U.R. : Pull–Up Resistor N-ch TYPE F–B TYPE G– C VDD V DD P.U.R. P-ch P.U.R. enable output disable (P) P–ch V LC0 VDD V LC1 P-ch data output disable IN/OUT P-ch SEG data/Bit Port data N-ch OUT N-ch output disable (N) V LC2 N-ch P.U.R.
µPD75P308 TYPE M-C VDD P.U.R. P.U.R. enable P–ch IN/OUT data N-ch output disable P.U.R. : Pull–Up Resistor 1.4 NOTES ON USING P00/INT4 AND RESET PINS In addition to the functions shown in sections 1.1 and 1.2, the P00/INT4 and RESET pins also have a function to set a test mode (for IC testing) in which the internal operations of the µPD75P308 are tested. When a voltage higher than VDD is applied to either of these pins, the test mode is set.
µPD75P308 2. DIFFERENCES BETWEEN µPD75P308 AND µPD75308 The µ PD75P308 is a model of the µ PD75308 and is equipped with a PROM instead of a mask ROM. Programs can be rewritten to the PROM of the µ PD75P308. Table 2-1 shows the differences between the µ PD75P308 and µPD75308. You should fully consider these differences when you debug or produce your application system on an experimental basis by using the PROM model, and then proceed to mass-produce the system by using the mask ROM model.
µPD75P308 3. WRITING AND VERIFYING PROM (PROGRAM MEMORY) The program memory of the µPD75P308 is a PROM of 8064 x 8 bits. To write data to or verify the contents of this PROM, the pins listed in the table below are used. Note that no address input pins are provided because the address is updated by the clock input through the X1 pin.
µ PD75P308 3.2 PROGRAM MEMORY WRITE PROCEDURE The program memory write procedure is as follows. High-speed program memory write is possible. (1) Ground the unused pins through pull-down resistors. The X1 pin must be low. (2) Supply 5 V to the VDD and VPP pins. (3) Wait for 10 microseconds. (4) Set program memory address 0 clear mode. (5) Supply 6 V to the VDD pin and 12.5 V to the VPP pin. (6) Set program inhibit mode. (7) Write data in 1-millisecond write mode. (8) Set program inhibit mode.
µPD75P308 3.3 PROGRAM MEMORY READ PROCEDURE The contents of the program memory can be read in the following procedure. (1) Ground the unused pins through pull-down resistors. The X1 pin must be low. (2) Supply 5 V to the VDD and V PP pins. (3) Wait for 10 microseconds. (4) Set program memory address 0 clear mode. (5) Supply 6 V to the VDD pin and 12.5 V to the V PP pin. (6) Set program inhibit mode. (7) Set verify mode.
µPD75P308 3.4 ERASURE (µPD75P308K ONLY) The contents of the data programmed to the µ PD75P308 can be erased by exposing the window of the program memory to ultraviolet rays. The wavelength of the ultraviolet rays used to erase the contents is about 250 nm, and the quantity of the ultraviolet rays necessary for complete erasure is 15 W.s/cm2 (= ultraviolet ray intensity x erasure time).
µPD75P308 4. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (T a = 25°C) Parameter Symbol Conditions Rating Unit Supply Voltage VDD -0.3 to +7.0 V Supply Voltage VPP -0.3 to +13.5 V -0.3 to VDD+0.3 V -0.3 to +11 V -0.3 to VDD+0.
µPD75P308 MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (T a = -10 to +70°C, VDD = 5 to ±5 V) Recommended Oscillator Item Constants Ceramic*3 Conditions MIN. TYP. MAX. Unit 5.0*4 MHz 4 ms 5.0*4 MHz 10 ms 1.0 5.0*4 MHz 100 500 ns Oscillation X1 X2 1.0 frequency (fXX)*1 C2 Oscillation stabilization C1 *2 time VDD Crystal After VDD came to MIN. of oscillation voltage range Oscilaltion X1 X2 1.0 frequency (fXX)*1 4.
µPD75P308 SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -10 to +70°C, VDD = 5 V ±5%) Recommended Oscillator Item Constants Crystal Conditions MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.
µPD75P308 DC CHARACTERISTICS (Ta = -10 to +70°C, V DD = 5V ±5%) Parameter Symbol High-Level Input Voltage Low-Level Input Voltage Conditions MIN. TYP. Ports 2, 3 0.7 VDD VDD V VIH2 Ports 0, 1, 6, 7, RESET 0.8 VDD VDD V VIH3 Ports 4, 5 0.7 VDD 10 V VIH4 X1, X2, XT1 VDD-0.5 VDD V VIL1 Ports 2, 3, 4, 5 0 0.3 VDD V VIL2 Ports 0, 1, 6, 7, RESET 0 0.2 VDD V VIL3 X1, X2, XT1 Ports 0, 2, 3, 6, 7 BIAS 0 0.4 V VOH1 Open-drain IOH = -1mA VDD-1.
µPD75P308 AC CHARACTERISTICS (Ta = -10 to + 70°C, VDD = 5V ±5%) Operation Other Than Serial Transfer Parameter Symbol Conditions MIN. TYP. MAX. Unit 64 µs 125 µs 1 MHz CPU Clock Cycle Time*1 (Minimum Instruction Execution Time 0.95 w/subsystem clock 114 tCY = 1 Machine Cycle) TI0 Input Frequency w/main system clock 122 fTI 0 tTIH, tTIL 0.
µPD75P308 SERIAL TRANSFER OPERATION TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: internal clock output) Parameter SCK Cycle Time SCK High-, Low-Level Widths ★ Symbol Conditions MIN. TYP. MAX. Unit tKCY1 Output 1600 ns tKH1, tKL1 Output tKCY1/2-50 ns SI Set-Up Time (vs. SCK↑ ) tSIK1 150 ns SI Hold Time (vs. SCK↑ ) tKSI1 400 ns SCK ↓ → SO Output Delay Time tKSO1 RL = 1kΩ, CL = 100pF* 250 ns MAX. Unit *: RL and C L are load resistance and load capacitance of the SO output line.
µPD75P308 SBI MODE (SCK: internal clock output (master)) Parameter SCK Cycle Time Symbol Conditions MIN. TYP. MAX. Unit 1600 ns t KH3 tKCY/2 -50 ns SB0, 1 Set-Up Time (vs. SCK ↑ ) tSIK3 150 ns SB0, 1 Hold Time (vs.
µ PD75P308 AC TIMING TEST POINT (excluding X1 and XT1 inputs) 0.8 VDD 0.8 VDD Test points 0.2 VDD 0.2 VDD CLOCK TIMING 1/fX tXL tXH X1 input VDD –0.5V 0.4 V 1/fXT tXTL tXTH XT1 input VDD –0.5V 0.
µPD75P308 SERIAL TRANSFER TIMING THREE-LINE SERIAL I/O MODE: tKCY1 tKL1 tKH1 SCK tSIK1 SI tKSI1 Input data tKSO1 Output data SO TWO-LINE SERIAL I/O MODE: tKCY tKH tKL SCK tKSO tSIK tKSI SB0,1 23
µPD75P308 SERIAL TRANSFER TIMING BUS RELEASE SIGNAL TRANSFER t KCY3,4 tKL3,4 tKH3,4 SCK tKSB tSBL tSBH tSIK3,4 tSBK SB0,1 tKSO3,4 COMMAND SIGNAL TRANSFER tKCY3,4 tKL3,4 tKH3,4 SCK tKSB tSIK3,4 tSBK SB0,1 tKSO3,4 INTERRUPT INPUT TIMING tINTL INT0, 1, 2, 4 KR0-7 RESET INPUT TIMING tRSL RESET 24 tINTH tKSI3,4 tKSI3,4
µPD75P308 LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE (T a = -10 to +70°C) Parameter Symbol Conditions MIN. TYP. MAX. Unit 6.0 V 10 µA Data Retention Supply VDDDR Voltage 2.0 Data Retention Supply IDDDR Current* 1 VDDDR = 2.0V 0.
µPD75P308 DC PROGRAMMING CHARACTERISTICS (Ta = 25 ±5°C, VDD = 6.0±0.25V, V PP = 12.5±0.3V, VSS = 0V) Parameter Symbol High-Level Input Voltage Low-Level Input Voltage MAX. Unit VIH1 Other than X1 or X2 Conditions 0.7 VDD VDD V VIH2 X1 and X2 VDD –0.5 VDD V VIL1 Other than X1 or X2 0 0.3 V DD V 0 0.4 V 10 µA VIL2 X1 and X2 Input Leakage Current ILI VIN = V IL or VIH High-Level Output Voltage VOH IOH = –1 mA Low-Level Output Voltage VOL IOL = 1.
µPD75P308 PROGRAM MEMORY WRITE TIMING tVPS VPP VPP VDD VDD VDD+1 VDD tVDS tXH X1 P40-P43 P50-P53 Data output Data input tDS t OH tI tDV Data input tDF tXL tDH tAH tDS Data input tAS MD0 tMOS tM1R tPW tOPW MD1 tPCR tM1S tM1H MD2 tM3H tM3S MD3 PROGRAM MEMORY READ TIMING tVPS VPP VPP VDD VDD VDD+1 VDD tVDS tXH X1 tXL P40-P43 P50-P53 tHAD Data output tDV tI tDAD Data output tM3HR tDFR MD0 MD1 tPCR MD2 tM3SR MD3 27
µPD75P308 5. PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14×20) A B 41 40 64 65 F Q 5°±5° S C D detail of lead end 25 24 80 1 G H I M J M P K N L P80GF-80-3B9-2 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. 28 ITEM MILLIMETERS INCHES A 23.6 ± 0.4 0.929 ± 0.016 B 20.0 ± 0.2 0.795 +0.009 –0.008 C 14.0 ± 0.2 0.551+0.009 –0.008 D 17.6 ± 0.4 0.693 ± 0.016 F 1.0 0.039 G 0.8 0.031 H 0.35 ± 0.10 0.
µPD75P308 80 PIN CERAMIC WQFN A Q K C D B T W S 80 H U I 1 M R E F G J X80KW-80A-1 NOTE Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 20.0 ± 0.4 0.787+0.017 –0.016 B 19.0 0.748 C 13.2 0.520 D 14.2 ± 0.4 0.559 ± 0.016 E 1.64 0.065 F 2.14 0.084 G 4.064 MAX. 0.160 MAX. H 0.51 ± 0.10 0.020 ± 0.004 I 0.08 0.003 J 0.8 (T.P.) 0.031 (T.P.) K 1.0 ± 0.2 0.039 –0.
µ PD75P308 ★ 6. RECOMMENDED SOLDERING CONDITIONS It is recommended that µ PD75P308 be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document "Semiconductor Devices Mounting Manual" (IEI-616). The soldering methods and conditions are not listed here, consult NEC.
µPD75P308 APPENDIX A. DEVELOPMENT TOOLS The following development support tools are readily available to support development of systems using µPD75P308: PROM writing tools Hardare IE-75000-R*1 In-circuit emulator for 75K series IE-75001-R IE-75000-R-EM *2 Emulation board for IE-75000-R and IE-75001-R EP-75308GF-R Emulation prove for µPD75P308GF, provided with 80-pin conversion socket, EV-9200G-80 PG-1500 PA-75P308GF EV-9200G-80. PROM programmer PROM programmer adapter solely used for µ PD75P308GF.
µ PD75P308 ★ APPENDIX B.
µPD75P308 GENERAL NOTES ON CMOS DEVICES 1 STATIC ELECTRICITY (ALL MOS DEVICES) Exercise care so that MOS devices are not adversely influenced by static electricity while being handled. The insulation of the gates of the MOS device may be destroyed by a strong static charge.
µ PD75P308 [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device.