Electronics America 4-Bit Single-Chip Microcomputer User's Manual

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CHAPTER 9. INSTRUCTION SET
A, #n 4 1 1 A ← n 4 Stack A
XA, #n 8 2 2 XA ← n 8 Stack A
HL, #n 8 2 2 HL ← n 8 Stack B
A, @HL 1 1 A ← (HL) *1
MOV @HL, A 1 1 (HL) ← A*1
A, mem 2 2 A ← (mem) *2
XA, mem 2 2 XA ← (mem) *2
mem, A 2 2 (mem) ← A*2
mem, XA 2 2 (mem) ← XA *2
A, @HL 1 1 A ↔ (HL) *1
A, mem 2 2 A ↔ (mem) *2
XA, mem 2 2 XA ↔ (mem) *2
A, reg1 1 1 A ↔ reg1
MOVT XA, @PCXA 1 3 XA ← (PC10 – 8 + XA) ROM
A, #n 4 1 1 + S A ← A + n 4 carry
A, @HL 1 1 + S A ← A + (HL) *1 carry
ADDC A, @HL 1 1 A, CY ← A + (HL) + CY *1
AND A. @HL 1 1 A ← A ∧ (HL) *1
OR A, @HL 1 1 A ← A ∨ (HL) *1
XOR A, @HL 1 1 A ← A ∨ (HL) *1
RORC A 1 1 CY ← A0, A3 ← CY, An–1 ← An
NOT A 2 2 A ← A
reg 1 1 + S reg ← reg + 1 reg = 0
mem 2 2 + S (mem) ← (mem) + 1 *2 (mem) = 0
DECS reg 1 1 + S reg ← reg – 1 reg = FH
reg, #n 4 2 2 + S Skip if reg = n 4 reg = n4
A, @HL 1 1 + S Skip if A = (HL) *1 A = (HL)
SET 1 CY 1 1 CY ← 1
CLR 1 CY 1 1 CY ← 0
SKT CY 1 1 + S Skip if CY = 1 CY = 1
NOT 1 CY 1 1 CY ← CY
Operation
Skip
Condition
Addressing
Area
XCH
Note 1. Instruction Group
2. Accumulator operation instructions
3. Increment/decrement instructions
4. Compare instructions
Note 1
Mnemonic Operand
ADDS
Move instructions
Arithmetic and logic instructions
Note 2
Note 4
Note 3
Carry flag operation instructions
Machine
Cycle
Bytes
INCS
SKE