Electronics America 8-Bit Single-Chip Microcontrollers User's Manual

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PD78054, 78054Y SUBSERIES

8-BIT SINGLE-CHIP MICROCONTROLLERS

PD78052

PD78052Y

PD78053

PD78053Y

PD78054

PD78054Y

PD78P054

PD78055Y

PD78055

PD78056Y

PD78056

PD78058Y

PD78058

PD78P058Y

PD78P058

PD78052(A)

PD78053(A)

PD78054(A)

Document No. U11747EJ5V0UM00 (5th edition)

Date Published April 1998 N CP (K)

1992

User’s Manual

Printed in Japan

Summary of content (603 pages)

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User’s Manual µPD78054, 78054Y SUBSERIES 8-BIT SINGLE-CHIP MICROCONTROLLERS µPD78052 µPD78053 µPD78054 µPD78P054 µPD78055 µPD78056 µPD78058 µPD78P058 µPD78052(A) µPD78053(A) µPD78054(A) µPD78052Y µPD78053Y µPD78054Y µPD78055Y µPD78056Y µPD78058Y µPD78P058Y Document No.
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity.
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FIP, EEPROM, IEBus, QTOP are trademarks of NEC Corporation. MS-DOS, Windows, and Widows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT and PC DOS are trademarks of International Business Machines Corporation. HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Sun OS is a trademark of Sun Microsystems, Inc.
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The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I 2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. The information in this document is subject to change without notice.
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Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors.
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Major Revisions in This Edition Page Description Throughout Addition of µPD78052(A),78053(A), 78054(A) to the applicable types Deletion of µPD78P054Y from the applicable types Deletion of the following package from the µPD78052, 78053, 78054, 78055, 78056, 78058, 78P058, 78054Y Subseries: • 80-pin plastic QFP (14 × 14 mm, resin thickness 2.7 mm) p. 233 Addition of Figure 9-10. Square-Wave Output Operation Timing p. 238 Addition of Figure 9-13. Square-Wave Output Operation Timing p.
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PREFACE Readers This manual has been prepared for user engineers who want to understand the functions of the µPD78054 and 78054Y Subseries and design and develop its application systems and programs. The target products are the products of the following subseries.
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How to Read This Manual Before reading this manual, you should have general knowledge of electric and logic circuits and microcontrollers. For users who use this document as the manual for the µPD78052(A), 78053(A), and 78054(A): → The only differences between the µPD78052, 78053, and 78054 and the µPD78052(A), 78053(A), 78054(A) are the quality grades and packages. (refer to 1.9 Differences between Standard Quality Grade Products and (A) Products).
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Chapter Organization: This manual divides the descriptions for the µPD78054 and 78054Y Subseries into different chapters as shown below. Read only the chapters related to the device you use.
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Differences between µPD78054 and µPD78054Y Subseries: The µPD78054 and µPD78054Y Subseries are different in the following functions of the serial interface channel 0.
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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Related documents for µPD78054 Subseries Document No.
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Development Tool Documents (User’s Manuals) Document No.
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Documents for Embedded Software (User’s Manual) Document No. Document name Japanese 78K/0 Series Real-Time OS OS for 78K/0 Series MX78K0 English Basics U11537J U11537E Installation U11536J U11536E Basics U12257J U12257E Other Documents Document No.
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[MEMO] 16
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TABLE OF CONTENTS CHAPTER 1 GENERAL (µPD78054 Subseries) ............................................................................ 1.1 Features ............................................................................................................................. 1.2 Applications ...................................................................................................................... 1.3 Ordering Information .............................................................................
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3.2.18 VDD ....................................................................................................................................... 70 3.2.19 VSS ....................................................................................................................................... 70 3.2.20 VPP (PROM versions only) ................................................................................................... 70 3.2.21 IC (Mask ROM version only) .................................
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5.3.3 Table indirect addressing ..................................................................................................... 5.3.4 120 Register addressing ............................................................................................................. 120 Operand Address Addressing ......................................................................................... 121 5.4.1 Implied addressing ...............................................................................
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER ............................................................................. 8.1 Outline of Timers Incorporated in the µPD78054, 78054Y Subseries .......................... 8.2 16-Bit Timer/Event Counter Functions ........................................................................... 8.3 16-Bit Timer/Event Counter Configuration ..................................................................... 8.4 16-Bit Timer/Event Counter Control Registers ....................
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CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT .................................................................... 261 13.1 Buzzer Output Control Circuit Functions ............................................................................. 261 13.2 Buzzer Output Control Circuit Configuration ....................................................................... 261 13.3 Buzzer Output Function Control Registers ..........................................................................
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 ............................................................................ 18.1 Serial Interface Channel 1 Functions .............................................................................. 18.2 Serial Interface Channel 1 Configuration ....................................................................... 18.3 Serial Interface Channel 1 Control Registers ................................................................. 18.
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.2 Standby Function Operations .......................................................................................... 527 23.2.1 HALT mode .......................................................................................................................... 527 23.2.2 STOP mode ......................................................................................................................... 530 CHAPTER 24 RESET FUNCTION ...............................................................
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B.4 B.5 OS for IBM PC ................................................................................................................... Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A .................. 589 589 APPENDIX C EMBEDDED SOFTWARE .......................................................................................... 593 APPENDIX D REGISTER INDEX ...................................................................................................... D.
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LIST OF FIGURES (1/8) Figure No. Title Page 3-1. Pin Input/Output Circuit of List ....................................................................................................... 73 4-1. Pin Input/Output Circuit of List ....................................................................................................... 89 5-1. Memory Map (µPD78052, 78052Y) ............................................................................................... 91 5-2.
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LIST OF FIGURES (2/8) Figure No. Title 6-18. P130 and P131 Block Diagram ..................................................................................................... 6-19. Port Mode Register Format ........................................................................................................... 152 6-20. Pull-Up Resistor Option Register Format ...................................................................................... 153 6-21.
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LIST OF FIGURES (3/8) Figure No. 8-23. 8-24. 8-25. Title Page Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) .................................................................... 202 Control Register Settings for Pulse Width Measurement by Means of Restart ............................. 203 Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified) .............................................
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LIST OF FIGURES (4/8) Figure No. 28 Title Page 12-1. Remote Controlled Output Application Example ........................................................................... 255 12-2. Clock Output Control Circuit Block Diagram ................................................................................. 256 12-3. Timer Clock Select Register 0 Format ........................................................................................... 258 12-4. Port Mode Register 3 Format ...........
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LIST OF FIGURES (5/8) Figure No. Title Page 16-17. Data ............................................................................................................................................... 16-18. Acknowledge Signal ...................................................................................................................... 313 16-19. BUSY and READY Signals ............................................................................................................ 314 16-20.
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LIST OF FIGURES (6/8) Figure No. Title 17-26. Slave Wait Release (Reception) .................................................................................................... 387 17-27. SCK0/SCL/P27 Pin Configuration ................................................................................................. 390 17-28. SCK0/SCL/P27 Pin Configuration ................................................................................................. 390 17-29. Logic Circuit of SCL Signal ..
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LIST OF FIGURES (7/8) Figure No. Title Page 19-12. 3-Wire Serial I/O Mode Timing ...................................................................................................... 472 19-13. Circuit of Switching in Transfer Bit Order ...................................................................................... 473 19-14. Reception Completion Interrupt Request Generation Timing (when ISRM = 1) ............................ 474 19-15. Receive Buffer Register Read Disable Period .....
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LIST OF FIGURES (8/8) Figure No. 32 Title Page 23-3. HALT Mode Release by RESET Input ........................................................................................... 529 23-4. STOP Mode Release by Interrupt Request Generation ................................................................ 531 23-5. Release by STOP Mode RESET Input .......................................................................................... 532 24-1. Block Diagram of Reset Function ..................
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LIST OF TABLES (1/3) Table No. Title Page 1-1. Differences between Standard Quality Grade Products and (A) Products .................................... 48 1-2. Mask Options of Mask ROM Versions ........................................................................................... 48 2-1. Mask Options of Mask ROM Versions ........................................................................................... 58 3-1. Pin Input/Output Circuit Types ......................................
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LIST OF TABLES (2/3) Table No. 9-8. 9-9. Title 8-Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges .............................................. 235 Square-Wave Output Ranges when 2-Channel 8-Bit Timer/ Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter ....................................................................................... 237 10-1. Interval Timer Interval Time .................................................................................................
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LIST OF TABLES (3/3) Table No. Title Page 19-7. Receive Error Causes ................................................................................................................... 465 20-1. Real-time Output Port Configuration ............................................................................................. 478 20-2. Operation in Real-time Output Buffer Register Manipulation ........................................................ 479 20-3.
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[MEMO] 36
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CHAPTER 1 GENERAL (µPD78054 Subseries) 1.1 Features On-chip high-capacity ROM and RAM Type Data Memory Program Memory (ROM) Internal High-Speed RAM µPD78052 16 Kbytes 512 bytes µPD78053 24 Kbytes 1024 bytes µPD78054 32 Kbytes µPD78P054 32 KbytesNote1 1024 bytesNote1 µPD78055 40 Kbytes 1024 bytes µPD78056 48 Kbytes µPD78058 60 Kbytes Part Number µPD78P058 Notes 60 KbytesNote1 Internal Buffer RAM 32 bytes Internal Expansion RAM None 1024 bytes 1024 bytesNote1 1024 bytesNote2 1.
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CHAPTER 1 OUTLINE (µPD78054 Subseries) 1.2 Applications µPD78052, 78053, 78054, 78P054, 78055, 78056, 78058, 78P058: Cellular phones, pagers, printers, AV equipment, air conditioners, cameras, PPCs, fuzzy home appliances, vending machines, etc. µPD78052(A), 78053(A), 78054(A): Control unit for automobile electronics, gas detector/breaker, various safety unit, etc. 1.3 Ordering Information Part number Package Internal ROM µPD78052GC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.
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CHAPTER 1 OUTLINE (µPD78054 Subseries) 1.4 Quality Grade Part number Package Quality grade µPD78052GC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard µPD78052GK-×××-BE9 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) Standard µPD78053GC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard µPD78053GK-×××-BE9 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) Standard µPD78054GC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.
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CHAPTER 1 OUTLINE (µPD78054 Subseries) 1.5 Pin Configuration (Top View) (1) Normal operating mode • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) µPD78P054GC-3B9 • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.
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CHAPTER 1 OUTLINE (µPD78054 Subseries) Pin Identifications A8 to A15 : Address Bus P130, P131 : Port13 AD0 to AD7 : Address/Data Bus PCL : Programmable Clock ANI0 to ANI7 : Analog Input RD : Read Strobe : ANO0, ANO1 : Analog Output RESET ASCK : Asynchronous Serial Clock RTP0 to RTP7 : Real-Time Output Port Reset ASTB : Address Strobe RxD : Receive Data AVDD : Analog Power Supply SB0, SB1 : Serial Bus AVREF0, AVREF1 : Analog Reference Voltage SCK0 to SCK2 : Seri
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CHAPTER 1 OUTLINE (µPD78054 Subseries) (2) PROM programming mode • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) µPD78P054GC-3B9 • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.
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CHAPTER 1 OUTLINE (µPD78054 Subseries) 1.6 78K/0 Series Expansion The products in the 78K/0 Series are listed below. The names in boxes are subseries names. Mass-produced products Products under development The subseries whose name ends with Y support the I2C bus specifications.
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CHAPTER 1 OUTLINE (µPD78054 Subseries) The following shows the major differences between subseries products. Function ROM Timer 8-bit 10-bit 8-bit VDD Serial Interface Subseries Name Control Capacity 8-bit 16-bit Watch WDT A/D µPD78075B 32 K to 40 K 4 ch 1 ch 1 ch 1 ch 8 ch µPD78078 48 K to 60 K µPD78070A A/D – D/A 2 ch 3 ch (UART: 1 ch) 88 1.8 V 61 2.7 V µPD780058 24 K to 60 K 2 ch 3 ch (Time division UART: 1 ch) 68 1.8 V µPD78058F 48 K to 60 K 3 ch (UART: 1 ch) 69 2.
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CHAPTER 1 OUTLINE (µPD78054 Subseries) 1.
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CHAPTER 1 OUTLINE (µPD78054 Subseries) 1.
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CHAPTER 1 Part Number OUTLINE (µPD78054 Subseries) µPD78052 µPD78053 µPD78054 µPD78P054 µPD78055 µPD78056 µPD78058 µPD78P058 Item Note 1 Vectored Maskable Internal: 13 External: 7 interrupt Non-maskable Internal: 1 source Software 1 Test input Internal: 1 External: 1 Supply voltage VDD = 2.0 to 6.0 V Note2 Operating ambient temperature TA = –40 to +85°C Package • 80-pin plastic QFP (14 × 14 mm, Resin thickness : 2.
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CHAPTER 1 OUTLINE (µPD78054 Subseries) 1.9 Differences between Standard Quality Grade Products and (A) Products Table 1-1 shows the differences between the standard quality grade products (µPD78052, 78053, 78054) and (A) products (µPD78052(A), 78053(A), 78054(A)). Table 1-1. Differences between Standard Quality Grade Products and (A) Products Part Number Standard Quality Grade Products (A) Products Quality grade Standard Special Package • 80-pin plastic QFPNote 3 (14 × 14 mm, Resin thickness : 1.
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CHAPTER 2 GENERAL (µPD78054Y Subseries) 2.1 Features On-chip high-capacity ROM and RAM Type Part Number Program Memory (ROM) Data Memory Internal High-Speed RAM Internal Buffer RAM Internal Expansion RAM 32 bytes None µPD78052Y 16 Kbytes 512 bytes µPD78053Y 24 Kbytes 1024 bytes µPD78054Y 32 Kbytes µPD78055Y 40 Kbytes µPD78056Y 48 Kbytes µPD78058Y 60 Kbytes µPD78P058Y Notes 60 KbytesNote 1 1024 bytes 1024 bytesNote 1 1024 bytesNote 2 1.
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CHAPTER 2 OUTLINE (µPD78054Y Subseries) 2.2 Applications Cellular phones, pagers, printers, AV equipment, air conditioners, cameras, PPCs, fuzzy home appliances, vending machines, etc. 2.3 Ordering Information Part number Package Internal ROM µPD78052YGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Mask ROM µPD78053YGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Mask ROM µPD78054YGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.
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CHAPTER 2 OUTLINE (µPD78054Y Subseries) 2.5 Pin Configuration (Top View) (1) Normal operating mode • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.
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CHAPTER 2 OUTLINE (µPD78054Y Subseries) Pin Identifications 52 A8 to A15 : Address Bus PCL : Programmable Clock AD0 to AD7 : Address/Data Bus RESET : Reset ANI0 to ANI7 : Analog Input RD : Read Strobe ANO0 to ANO7 : Analog Output RTP0 to RTP7 : Real-Time Output Port ASCK : Asynchronous Serial Clock RxD : Receive Data ASTB : Address Strobe SB0, SB1 : AVDD : Analog Power Supply SCK0 to SCK1 : Serial Clock AVREF0, AVREF1 : Analog Reference Voltage SCL : Serial Cl
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CHAPTER 2 OUTLINE (µPD78054Y Subseries) (2) PROM programming mode • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) µPD78P058YGC-8BT • 80-pin ceramic WQFN (14 × 14 mm) VDD (L) A2 A3 A4 A5 A6 A7 A8 A16 A10 A11 A12 A13 VSS A14 A15 A0 A1 2.
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CHAPTER 2 OUTLINE (µPD78054Y Subseries) 2.6 78K/0 Series Expansion The products in the 78K/0 Series are listed below. The names in boxes are subseries names. Mass-produced products Products under development The subseries whose name ends with Y support the I2C bus specifications.
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CHAPTER 2 OUTLINE (µPD78054Y Subseries) Major differences among Y subseries are tabulated below. Function Subseries Control µPD78078Y ROM Capacity VDD MIN. 1.8 V : 1 ch : 1 ch : 1 ch 88 µPD780018AY 48K to 60K 3-wire with automatic transmit/receive function Time division 3-wire I2C bus (supports multi-master) : 1 ch : 1 ch : 1 ch 88 µPD780058Y 24K to 60K 3-wire/2-wire/I2C 3-wire with automatic transmit/receive function 3-wire/time division UART : 1 ch : 1 ch : 1 ch 68 1.
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CHAPTER 2 OUTLINE (µPD78054Y Subseries) 2.
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CHAPTER 2 OUTLINE (µPD78054Y Subseries) 2.
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CHAPTER 2 Part Number Item Maskable µPD78052Y µPD78053Y µPD78054Y µPD78055Y µPD78056Y µPD78058Y µPD78P058Y Internal: 13 Vectored interrupt OUTLINE (µPD78054Y Subseries) External: 7 Non-maskable Internal: 1 Software 1 source Test input Internal: 1 External: 1 Supply voltage VDD = 2.0 to 6.0 V Operating ambient temperature TA = –40 to +85 °C Package • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.
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CHAPTER 3 PIN FUNCTION (µPD78054 Subseries) 3.1 Pin Function List 3.1.1 Normal operating mode pins (1) Port pins (1/3) Pin Name Input/Output P00 Function Input Input only P01 Input/output mode can be specified P02 in 1-bit units. After Reset Alternate Function Input INTP0/TI00 INTP1/TI01 INTP2 P03 Input/ Port 0. When used as an input port, an P04 output 8-bit input/output port. on-chip pull-up resistor can be used INTP4 by software.
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CHAPTER 3 PIN FUNCTION (µPD78054 Subseries) (1) Port pins (2/3) Pin Name Input/Output Function After Reset Alternate Function P30 TO0 P31 TO1 P32 Port 3. TO2 P33 Input/ 8-bit input/output port. P34 output Input/output mode can be specified in 1-bit units. TI2 P35 When used as an input port, an on-chip pull-up resistor can be used by PCL P36 software. BUZ Input P37 TI1 — Port 4. 8-bit input/output port. P40 to P47 Input/ Input/output mode can be specified in 8-bit units.
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CHAPTER 3 PIN FUNCTION (µPD78054 Subseries) (1) Port pins (3/3) Pin Name Input/Output P120 to P127 Function Input/ Port 12. output 8-bit input/output port. After Reset Alternate Function Input RTP0 to RTP7 Input/output mode can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be used by software. P130 to P131 Input/ Port 13. output 2-bit input/output port. Input ANO0 to ANO1 Input/output mode can be specified in 1-bit units.
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CHAPTER 3 PIN FUNCTION (µPD78054 Subseries) (2) Pins other than port pins (1/2) Pin Name Input/Output Function After Reset Alternate Function INTP0 P00/TI00 INTP1 P01/TI01 INTP2 INTP3 External interrupt request inputs with specifiable valid edges (rising Input edge, falling edge, both rising and falling edges).
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CHAPTER 3 PIN FUNCTION (µPD78054 Subseries) (2) Pins other than port pins (2/2) Pin Name Input/Output Function AD0 to AD7 Input/Output Low-order address/data bus when expanding external memory A8 to A15 RD Output Output WR High-order address bus when expanding external memory Strobe signal output for read operation from external memory After Reset Alternate Function Input P40 to P47 Input P50 to P57 Input Strobe signal output for write operation to external memory WAIT Input ASTB Output P6
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CHAPTER 3 PIN FUNCTION (µPD78054 Subseries) 3.2 Description of Pin Functions 3.2.1 P00 to P07 (Port 0) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem oscillation. The following operating modes can be specified in 1-bit units.
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CHAPTER 3 PIN FUNCTION (µPD78054 Subseries) 3.2.2 P10 to P17 (Port 1) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog input. The following operating modes can be specified in 1-bit units. (1) Port mode These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input or output ports with a port mode register 1 (PM1).
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CHAPTER 3 PIN FUNCTION (µPD78054 Subseries) (d) BUSY Serial interface automatic transmit/receive busy input pins (e) STB Serial interface automatic transmit/receive strobe output pins Caution When this port is used as a serial interface, the I/O and output latches must be set according to the function the user requires. For the setting, refer to Figure 16-4 “Serial Operation Mode Register 0 Format” and Figure 18-3 “Serial Operation Mode Register 1 Format.” 3.2.
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CHAPTER 3 PIN FUNCTION (µPD78054 Subseries) 3.2.5 P40 to P47 (Port 4) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address/data bus. The test input flag (KRIF) can be set to 1 by detecting a falling edge. The following operating mode can be specified in 8-bit units. (1) Port mode These ports function as 8-bit input/output ports. They can be specified in 8-bit units for input or output ports by using the memory expansion mode register (MM).
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CHAPTER 3 PIN FUNCTION (µPD78054 Subseries) 3.2.8 P70 to P72 (Port 7) This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/ output and clock input/output functions. The following operating modes can be specified in 1-bit units. (1) Port mode Port 7 functions as a 3-bit input/output port. 1-bit-units specification as an input port or output port is possible by means of port mode register 7 (PM7).
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CHAPTER 3 PIN FUNCTION (µPD78054 Subseries) 3.2.9 P120 to P127 (Port 12) These are 8-bit input/output ports. Besides serving as input/output ports, they function as a real-time output port. The following operating modes can be specified in 1-bit units. (1) Port mode These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input or output ports with port mode register 12 (PM12).
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CHAPTER 3 PIN FUNCTION (µPD78054 Subseries) 3.2.13 AVDD Analog power supply pin of A/D converter. Always use the same voltage as that of the V DD pin even when A/D converter is not used. 3.2.14 AVSS This is a ground voltage pin of A/D converter and D/A converter. Always use the same voltage as that of the VSS pin even when neither A/D nor D/A converter is used. 3.2.15 RESET This is a low-level active system reset input pin. 3.2.16 X1 and X2 Crystal resonator connect pins for main system clock oscillation.
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CHAPTER 3 PIN FUNCTION (µPD78054 Subseries) 3.3 Input/output Circuits and Recommended Connection of Unused Pins Table 3-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. Refer to Figure 3-1 for the configuration of the input/output circuit of each type. Table 3-1. Pin Input/Output Circuit Types (1/2) Pin Name P00/INTP0/TI00 Input/Output Circuit Type 2 Input/Output Recommended Connection of Unused Pins Input Connect to VSS.
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CHAPTER 3 PIN FUNCTION (µPD78054 Subseries) Table 3-1. Pin Input/Output Circuit Types (2/2) Pin Name Input/Output Circuit Type P60 to P63 (Mask ROM version) 13-B P60 to P63 (PROM version) 13-D P64/RD P65/WR Input/Output Recommended Connection of Unused Pins Input/output Individually connect to VDD via a resistor. Input/output Individually connect to VDD or VSS via a resistor. Input/output Individually connect to VSS via a resistor.
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CHAPTER 3 PIN FUNCTION (µPD78054 Subseries) Figure 3-1.
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CHAPTER 3 PIN FUNCTION (µPD78054 Subseries) Figure 3-1.
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CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries) 4.1 Pin Function List 4.1.1 Normal operating mode pins (1) Port pins (1/3) Pin Name Input/Output P00 Function Input Input only P01 Input/output mode can be specified P02 in 1-bit units. After Reset Alternate Function Input INTP0/TI00 INTP1/TI01 INTP2 P03 Input/ Port 0. When used as an input port, an P04 output 8-bit input/output port. on-chip pull-up resistor can be used INTP4 by software.
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CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries) (1) Port pins (2/3) Pin Name Input/Output Function After Reset Alternate Function P30 TO0 P31 TO1 P32 Port 3. TO2 P33 Input/ 8-bit input/output port. P34 output Input/output mode can be specified in 1-bit units. TI2 P35 When used as an input port, an on-chip pull-up resistor can be used by PCL P36 software. BUZ Input P37 TI1 — Port 4. 8-bit input/output port. P40 to P47 Input/ Input/output mode can be specified in 8-bit units.
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CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries) (1) Port pins (3/3) Pin Name Input/Output P120 to P127 Function Input/ Port 12. output 8-bit input/output port. After Reset Alternate Function Input RTP0 to RTP7 Input/output mode can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be used by software. P130 to P131 Input/ Port 13. output 2-bit input/output port. Input ANO0 to ANO1 Input/output mode can be specified in 1-bit units.
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CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries) (2) Pins other than port pins (1/2) Pin Name Input/Output Function After Reset Alternate Function INTP0 P00/TI00 INTP1 P01/TI01 INTP2 INTP3 External interrupt request inputs with specifiable valid edges (rising Input edge, falling edge, both rising and falling edges).
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CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries) (2) Pins other than port pins (2/2) Pin Name Input/Output Function AD0 to AD7 Input/Output Low-order address/data bus when expanding external memory After Reset Alternate Function Input P40 to P47 A8 to A15 Output High-order address bus when expanding external memory Input P50 to P57 RD Output Strobe signal output for read operation from external memory Input P64 WR Strobe signal output for write operation to external memory WAIT Input ASTB
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CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries) 4.2 Description of Pin Functions 4.2.1 P00 to P07 (Port 0) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem oscillation. The following operating modes can be specified in 1-bit units.
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CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries) 4.2.2 P10 to P17 (Port 1) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog input. The following operating modes can be specified in 1-bit units. (1) Port mode These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input or output ports with a port mode register 1 (PM1).
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CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries) 4.2.4 P30 to P37 (Port 3) These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock output, and buzzer output. The following operating modes can be specified in 1-bit units. (1) Port mode These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input or output ports with port mode register 3 (PM3).
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CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries) 4.2.6 P50 to P57 (Port 5) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address bus. Port 5 can drive LEDs directly. The following operating modes can be specified in 1-bit units. (1) Port mode These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input/output ports with port mode register 5 (PM5).
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CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries) 4.2.8 P70 to P72 (Port 7) This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/ output and clock input/output functions. The following operating modes can be specified in 1-bit units. (1) Port mode Port 7 functions as a 3-bit input/output port. 1-bit-units specification as an input port or output port is possible by means of port mode register 7 (PM7).
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CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries) 4.2.10 P130 and P131 (Port 13) These are 2-bit input/output ports. Besides serving as input/output ports, they are used for D/A converter analog output. The following operating modes can be specified in 1-bit units. (1) Port mode These ports function as 2-bit input/output ports. They can be specified in 1-bit units as input or output ports with port mode register 13 (PM13).
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CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries) 4.2.16 X1 and X2 Crystal resonator connect pins for main system clock oscillation. For external clock supply, input it to X1 and its inverted signal to X2. 4.2.17 XT1 and XT2 Crystal resonator connect pins for subsystem clock oscillation. For external clock supply, input it to XT1 and its inverted signal to XT2. 4.2.18 VDD Positive power supply pin 4.2.19 VSS Ground potential pin 4.2.
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CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries) 4.3 Input/output Circuits and Recommended Connection of Unused Pins Table 4-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. Refer to Figure 4-1 for the configuration of the input/output circuit of each type. Table 4-1. Pin Input/Output Circuit Types (1/2) Pin Name Input/Output Circuit Type P00/INTP0/TI00 2 P01/INTP1/TI01 8-A Input/Output Recommended Connection of Unused Pins Input Connect to VSS.
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CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries) Table 4-1. Pin Input/Output Circuit Types (2/2) Pin Name Input/Output Circuit Type P60 to P63 (Mask ROM version) 13-B P60 to P63 (PROM version) 13-D P64/RD 5-A Input/Output Recommended Connection of Unused Pins Input/output Individually connect to VDD via a resistor. Input/output Individually connect to VDD or VSS via a resistor. Input/output Individually connect to VSS via a resistor.
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CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries) Figure 4-1.
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CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries) Figure 4-1.
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CHAPTER 5 CPU ARCHITECTURE 5.1 Memory Spaces Each product of the µPD78054 and 78054Y Subseries can access the memory space of 64 Kbytes. Figures 5-1 to 5-8 show memory maps. Figure 5-1.
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CHAPTER 5 CPU ARCHITECTURE Figure 5-2.
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CHAPTER 5 CPU ARCHITECTURE Figure 5-3.
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CHAPTER 5 CPU ARCHITECTURE Figure 5-4.
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CHAPTER 5 CPU ARCHITECTURE Figure 5-5.
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CHAPTER 5 CPU ARCHITECTURE Figure 5-6.
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CHAPTER 5 CPU ARCHITECTURE Figure 5-7.
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CHAPTER 5 CPU ARCHITECTURE Figure 5-8.
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CHAPTER 5 CPU ARCHITECTURE 5.1.1 Internal program memory space The internal program memory space stores programs and table data. Normally, they are addressed with a program counter (PC). Each product of the µPD78054 and 78054Y Subseries has the internal ROM (or PROM) of the size shown below. Table 5-1.
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CHAPTER 5 CPU ARCHITECTURE 5.1.2 Internal data memory space The µPD78054 and 78054Y subseries units incorporate the following RAMs. (1) Internal high-speed RAM The µPD78054 and 78054Y Subseries are provided with the internal high-speed RAM as shown below. Table 5-3.
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CHAPTER 5 CPU ARCHITECTURE 5.1.5 Data memory addressing The method to specify the address of the instruction to be executed next, or the address of a register or memory to be manipulated when an instruction is executed is called addressing. The address of the instruction to be executed next is addressed by the program counter PC (for details, refer to 5.3 Instruction Address Addressing).
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CHAPTER 5 CPU ARCHITECTURE Figure 5-10.
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CHAPTER 5 CPU ARCHITECTURE Figure 5-11.
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CHAPTER 5 CPU ARCHITECTURE Figure 5-12.
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CHAPTER 5 CPU ARCHITECTURE Figure 5-13.
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CHAPTER 5 CPU ARCHITECTURE Figure 5-14.
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CHAPTER 5 CPU ARCHITECTURE Figure 5-15.
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CHAPTER 5 CPU ARCHITECTURE Figure 5-16.
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CHAPTER 5 CPU ARCHITECTURE 5.2 Processor Registers The µPD78054 and 78054Y subseries units incorporate the following processor registers. 5.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
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CHAPTER 5 CPU ARCHITECTURE (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupts. When ISP = 0, the vectored interrupt whose priority is specified by the priority specify flag registers (PR0L, PR0H, and PR1L) (Refer to 21.
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CHAPTER 5 CPU ARCHITECTURE Figure 5-19. Stack Pointer Configuration 15 SP 0 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. Each stack operation saves/resets data as shown in Figures 5-20 and 5-21. Caution Since RESET input makes SP contents indeterminate, be sure to initialize the SP before instruction execution. Figure 5-20.
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CHAPTER 5 CPU ARCHITECTURE 5.2.2 General registers A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L and H). Each register can also be used as an 8-bit register. Two 8-bit registers can be used in pairs as a 16-bit register (AX, BC, DE and HL).
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CHAPTER 5 CPU ARCHITECTURE Figure 5-22.
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CHAPTER 5 CPU ARCHITECTURE 5.2.3 Special Function Register (SFR) Unlike a general register, each special-function register has special functions. It is allocated in the FF00H to FFFFH area. The special-function register can be manipulated like the general register, with the operation, transfer and bit manipulation instructions. Manipulatable bit units, 1, 8 and 16, depend on the special-function register type. Each manipulation bit unit can be specified as follows.
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CHAPTER 5 CPU ARCHITECTURE Table 5-6.
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CHAPTER 5 CPU ARCHITECTURE Table 5-6.
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CHAPTER 5 CPU ARCHITECTURE Table 5-6.
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CHAPTER 5 CPU ARCHITECTURE 5.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. The contents of PC are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing.
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CHAPTER 5 CPU ARCHITECTURE 5.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. The CALL !addr16 and BR !addr16 instruction can branch in the entire memory space. The CALLF !addr11 instruction branches to an area of addresses 0800H through 0FFFH.
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CHAPTER 5 CPU ARCHITECTURE 5.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. Before the CALLT [addr5] instruction is executed, table indirect addressing is performed. This instruction references an address stored in the memory table at addresses 40H through 7FH, and can branch in the entire memory space.
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CHAPTER 5 CPU ARCHITECTURE 5.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 5.4.1 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general register is automatically (illicitly) addressed. Of the µPD78054 and 78054Y subseries instruction words, the following instructions employ implied addressing.
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CHAPTER 5 CPU ARCHITECTURE 5.4.2 Register addressing [Function] This addressing accesses a general register as an operand. The general register accessed is specified by the register bank select flags (RBS0 and RBS1) and register specify code (Rn or RPn) in an instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.
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CHAPTER 5 CPU ARCHITECTURE 5.4.3 Direct addressing [Function] This addressing directly addresses the memory indicated by the immediate data in an instruction word.
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CHAPTER 5 CPU ARCHITECTURE 5.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space to which this address is applied is a 256-byte space of addresses FE20H through FF1FH. An internal high-speed RAM and a special-function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
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CHAPTER 5 CPU ARCHITECTURE 5.4.5 Special-Function Register (SFR) addressing [Function] The memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing.
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CHAPTER 5 CPU ARCHITECTURE 5.4.6 Register indirect addressing [Function] This addressing addresses the memory with the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register bank select flags (RBS0 and RBS1) and register pair specify code in an instruction code. This addressing can be carried out for all the memory spaces.
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CHAPTER 5 CPU ARCHITECTURE 5.4.7 Based addressing [Function] This addressing addresses the memory by adding 8-bit immediate data to the contents of the HL register pair which is used as a base register and by using the result of the addition. The HL register pair to be accessed is in the register bank specified by the register bank select flags (RBS0 and RBS1). Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored.
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CHAPTER 5 CPU ARCHITECTURE 5.4.8 Based indexed addressing [Function] This addressing addresses the memory by adding the contents of the HL register, which is used as a base register, to the contents of the B or C register specified in the instruction word, and by using the result of the addition. The HL, B, and C registers to be accessed are registers in the register bank specified by the register bank select flags (RBS0 and RBS1).
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CHAPTER 6 PORT FUNCTIONS 6.1 Port Functions The µPD78054 and 78054Y subseries units incorporate two input ports and sixty-seven input/output ports. Figure 6-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. Besides port functions, the ports can also serve as on-chip hardware input/output pins. Figure 6-1.
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CHAPTER 6 PORT FUNCTIONS Table 6-1. Port Functions (µPD78054 subseries) (1/2) Pin Name Function P00 Input only P01 Alternate Function INTP0/TI00 INTP1/TI01 P02 Input/output mode can be specified in 1-bit INTP2 P03 Port 0. units. INTP3 P04 8-bit input/output port. When used as an input port, an on-chip INTP4 pull-up resistor can be used by software. INTP5 P05 P06 INTP6 P07 Input only XT1 Port 1. 8-bit input/output port.
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CHAPTER 6 PORT FUNCTIONS Table 6-1. Port Functions (µPD78054 subseries) (2/2) Pin Name Function P60 N-ch open-drain input/output port. P61 On-chip pull-up resistor can be specified by Alternate Function — P62 Port 6. mask option. (Mask ROM version only). P63 8-bit input/output port. LEDs can be driven directly. P64 Input/output mode can be specified in 1-bit When used as an input port, an on-chip RD P65 units. pull-up resistor can be used by software.
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CHAPTER 6 PORT FUNCTIONS Table 6-2. Port Functions (µPD78054Y subseries) (1/2) Pin Name Function P00 Input only P01 Alternate Function INTP0/TI00 INTP1/TI01 P02 Input/output mode can be specified in 1-bit INTP2 P03 Port 0. units. INTP3 P04 8-bit input/output port. When used as an input port, an on-chip INTP4 pull-up resistor can be used by software. INTP5 P05 P06 INTP6 P07 Input only XT1 Port 1. P10 to P17 8-bit input/output port.
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CHAPTER 6 PORT FUNCTIONS Table 6-2. Port Functions (µPD78054Y subseries) (2/2) Pin Name Function P60 N-ch open drain input/output port. P61 On-chip pull-up resistor can be specified by Alternate Function — P62 Port 6. mask option. (Mask ROM version only). P63 8-bit input/output port. LEDs can be driven directly. P64 Input/output mode can be specified in 1-bit When used as an input port, an on-chip RD P65 units. pull-up resistor can be used by software.
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CHAPTER 6 PORT FUNCTIONS 6.2 Port Configuration A port consists of the following hardware: Table 6-3.
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CHAPTER 6 PORT FUNCTIONS Figure 6-2. P00 and P07 Block Diagram Internal bus RD P00/INTP0/TI00, P07/XT1 Figure 6-3. P01 to P06 Block Diagram VDD WRPUO PUO0 P-ch RD Internal bus Selector WRPORT Output Latch (P01 to P06) P01/INTP1/TI01.
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CHAPTER 6 PORT FUNCTIONS 6.2.2 Port 1 Port 1 is an 8-bit input/output port with output latch. It can specify the input mode/output mode in 1-bit units with a port mode register 1 (PM1). When P10 to P17 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL). Alternate functions include an A/D converter analog input. RESET input sets port 1 to input mode. Figure 6-4 shows a block diagram of port 1.
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CHAPTER 6 PORT FUNCTIONS 6.2.3 Port 2 (µPD78054 Subseries) Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (PM2). When P20 to P27 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).
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CHAPTER 6 PORT FUNCTIONS Figure 6-6.
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CHAPTER 6 PORT FUNCTIONS 6.2.4 Port 2 (µPD78054Y Subseries) Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (PM2). When P20 to P27 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).
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CHAPTER 6 PORT FUNCTIONS Figure 6-8.
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CHAPTER 6 PORT FUNCTIONS 6.2.5 Port 3 Port 3 is an 8-bit input/output port with output latch. P30 to P37 pins can specify the input mode/output mode in 1-bit units with the port mode register 3 (PM3). When P30 to P37 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL). Alternate functions include timer input/output, clock output and buzzer output. RESET input sets port 3 to input mode.
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CHAPTER 6 PORT FUNCTIONS 6.2.6 Port 4 Port 4 is an 8-bit input/output port with output latch. P40 to P47 pins can specify the input mode/output mode in 8-bit units with the memory expansion mode register (MM). When P40 to P47 pins are used as input ports, an onchip pull-up resistor can be used to them in 8-bit units with pull-up resistor option register L (PUOL). The test input flag (KRIF) can be set to 1 by detecting falling edges.
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CHAPTER 6 PORT FUNCTIONS 6.2.7 Port 5 Port 5 is an 8-bit input/output port with output latch. P50 to P57 pins can specify the input mode/output mode in 1-bit units with the port mode register 5 (PM5). When P50 to P57 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL). Port 5 can drive LEDs directly. Alternate function includes address bus function in external memory expansion mode.
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CHAPTER 6 PORT FUNCTIONS 6.2.8 Port 6 Port 6 is an 8-bit input/output port with output latch. P60 to P67 pins can specify the input mode/output mode in 1-bit units with the port mode register 6 (PM6). This port has functions related to pull-up resistors as shown below. These functions depending on whether the higher 4 bits or lower 4 bits of a port are used, and whether the mask ROM model or PROM model is used. Table 6-4.
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CHAPTER 6 PORT FUNCTIONS Figure 6-13. P60 to P63 Block Diagram VDD RD Mask Option Resistor Mask ROM products only. PROM versions have no pull-up resistor. Internal bus Selector WRPORT Output Latch (P60 to P63) P60-P63 WRPM PM60-PM63 PM : Port mode register RD : Port 6 read signal WR : Port 6 write signal Figure 6-14.
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CHAPTER 6 PORT FUNCTIONS 6.2.9 Port 7 This is a 3-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 7 (PM7). When pins P70 to P72 are used as input port pins, an on-chip pull-up resistor can be used as a 3-bit unit by means of pull-up resistor option register L (PUOL). Alternate functions include serial interface channel 2 data input/output and clock input/output. RESET input sets the input mode.
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CHAPTER 6 PORT FUNCTIONS Figure 6-16.
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CHAPTER 6 PORT FUNCTIONS 6.2.10 Port 12 This is an 8-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 12 (PM12). When pins P120 to P127 are used as input port pins, an on-chip pull-up resistor can be used as an 8-bit unit by means of pull-up resistor option register H (PUOH). Alternate function includes real-time output. RESET input sets the input mode. Figure 6-17 shows a block diagram of port 12. Figure 6-17.
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CHAPTER 6 PORT FUNCTIONS 6.2.11 Port 13 This is a 2-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 13 (PM13). When pins P130 and P131 are used as input port pins, an on-chip pull-up resistor can be used as a 2-bit unit by means of pull-up resistor option register H (PUOH). Alternate function includes D/A converter analog output. RESET input sets the input mode. Figure 6-18 shows a block diagram of port 13.
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CHAPTER 6 PORT FUNCTIONS 6.3 Port Function Control Registers The following four types of registers control the ports. • Port mode registers (PM0 to PM3, PM5 to PM7, PM12, PM13) • Pull-up resistor option register (PUOH, PUOL) • Memory expansion mode register (MM) • Key return mode register (KRM) (1) Port mode registers (PM0 to PM3, PM5 to PM7, PM12, PM13) These registers are used to set port input/output in 1-bit units.
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CHAPTER 6 PORT FUNCTIONS Table 6-5.
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CHAPTER 6 PORT FUNCTIONS Figure 6-19.
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CHAPTER 6 PORT FUNCTIONS (2) Pull-up resistor option register (PUOH, PUOL) This register is used to set whether to use an internal pull-up resistor at each port or not. A pull-up resistor is internally used at bits which are set to the input mode at a port where on-chip pull-up resistor use has been specified with PUOH, PUOL. No on-chip pull-up resistors can be used to the bits set to the output mode or to the bits used as an analog input pin, irrespective of PUOH or PUOL setting.
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CHAPTER 6 PORT FUNCTIONS (3) Memory expansion mode register (MM) This register is used to set input/output of port 4. MM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 10H. Figure 6-21.
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CHAPTER 6 PORT FUNCTIONS (4) Key return mode register (KRM) This register sets enabling/disabling of standby function release by a key return signal (falling edge detection of port 4). KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM to 02H. Figure 6-22.
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CHAPTER 6 PORT FUNCTIONS 6.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 6.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again.
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CHAPTER 6 PORT FUNCTIONS 6.4.3 Operations on input/output port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. (2) Input mode The output latch contents are undefined, but since the output buffer is OFF, the pin status does not change.
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[MEMO] 158
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CHAPTER 7 CLOCK GENERATOR 7.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates at frequencies of 1 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PCC). (2) Subsystem clock oscillator The circuit oscillates at a frequency of 32.768 kHz.
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CHAPTER 7 CLOCK GENERATOR Figure 7-1.
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CHAPTER 7 CLOCK GENERATOR 7.3 Clock Generator Control Register The clock generator is controlled by the following two registers: • Processor clock control register (PCC) • Oscillation mode selection register (OSMS) (1) Processor clock control register (PCC) The PCC sets whether to use CPU clock selection, the ratio of division, main system clock oscillator operation/ stop and subsystem clock oscillator internal feedback resistor. The PCC is set with a 1-bit or 8-bit memory manipulation instruction.
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CHAPTER 7 CLOCK GENERATOR Figure 7-3.
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CHAPTER 7 CLOCK GENERATOR The fastest instruction of the µPD78054 and 78054Y Subseries is executed with two clocks of the CPU clock. Therefore, relationships between the CPU clock (fCPU) and the minimum instruction execution time are as shown in Table 7-2. Table 7-2. Relationship between CPU Clock and Minimum Instruction Execution Time CPU Clock (fCPU) Minimum Instruction Execution Time: 2/fCPU fX 0.4 µs fX/2 0.8 µs fX/22 1.6 µs fX/23 3.2 µs fX/24 6.4 µs fX/25 12.
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CHAPTER 7 CLOCK GENERATOR (2) Oscillation mode selection register (OSMS) This register specifies whether the clock output from the main system clock oscillator without passing through the scaler is used as the main system clock, or the clock output via the scaler is used as the main system clock. OSMS is set with 8-bit memory manipulation instruction. RESET input sets OSMS to 00H. Figure 7-4.
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CHAPTER 7 CLOCK GENERATOR 7.4 System Clock Oscillator 7.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin and an antiphase clock signal to the X2 pin. Figure 7-6 shows an external circuit of the main system clock oscillator. Figure 7-6.
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CHAPTER 7 CLOCK GENERATOR 7.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the XT1 pin and an antiphase clock signal to the XT2 pin. Figure 7-7 shows an external circuit of the subsystem clock oscillator. Figure 7-7.
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CHAPTER 7 CLOCK GENERATOR Figure 7-8. Examples of Incorrect Oscillator Connection (2/2) (c) Changing high current is too near a signal conductor (d) Current flows through the grounding line of the oscillator (potential at points A, B, and C fluctuate) VDD Pnm IC X2 X1 IC X2 X1 High Current A B C High Current (e) Signals are fetched IC Remark X1 X2 When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. Cautions 2.
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CHAPTER 7 CLOCK GENERATOR 7.4.3 Scaler The scaler divides the main system clock oscillator output (fXX) and generates various clocks. 7.4.4 When no subsystem clocks are used If it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect the XT1 and XT2 pins as follows. XT1 : Connect to VDD. XT2 : Leave open. In this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator when the main system clock stops.
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CHAPTER 7 CLOCK GENERATOR 7.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode. • Main system clock • Subsystem clock • CPU clock fXX fXT fCPU • Clock to peripheral hardware The following clock generator functions and operations are determined with the processor clock control register (PCC) and the oscillation mode selection register (OSMS).
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CHAPTER 7 CLOCK GENERATOR 7.5.1 Main system clock operations When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 0), the following operations are carried out by PCC setting. (a) Because the operation guarantee instruction execution speed depends on the power supply voltage, the minimum instruction execution time can be changed by bits 0 to 2 (PCC0 to PCC2) of the PCC.
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CHAPTER 7 CLOCK GENERATOR Figure 7-9. Main System Clock Stop Function (2/2) (c) Operation when CSS is set after setting MCC with main system clock operation MCC CSS CLS Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock 7.5.2 Subsystem clock operations When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1), the following operations are carried out.
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Set Values before Switchover Set Values After Switchover MSC = 1 MSC = 0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 0 0 0 1 0 0 1 0 0 1 16 instructions 0 1 0 8 instructions 4 instructions 2 instructions 0 0 1 16 instructions 8 instructions 4 instructions 2 instructions 0 0 0 1 1 16 instructions 8 instructions 4 instructions 2 instructions 0 1 0 0 16 instr
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CHAPTER 7 CLOCK GENERATOR 7.6.2 System clock and CPU clock switching procedure This section describes switching procedure between system clock and CPU clock. Figure 7-10. System Clock and CPU Clock Switching VDD RESET Interrupt Request Signal System Clock CPU Clock fXX fXX Minimum Maximum Speed Operation Speed Operation Wait (26.2 ms : 5.
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[MEMO] 174
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.1 Outline of Timers Incorporated in the µPD78054, 78054Y Subseries This chapter explains 16-bit timer/event counter. Before that, the timers incorporated into the µPD78054, 78054Y Subseries and related circuits are outlined below.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-1.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.2 16-Bit Timer/Event Counter Functions The 16-bit timer/event counter (TM0) has the following functions. • Interval timer • PWM output • Pulse width measurement • External event counter • Square-wave output • One-shot pulse output PWM output and pulse width measurement can be used at the same time. (1) Interval timer TM0 generates interrupt requests at the preset time interval. Table 8-2.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (5) Square-wave output TM0 can output a square wave with any selected frequency. Table 8-3. 16-Bit Timer/Event Counter Square-Wave Output Ranges Minimum Pulse Width MCS = 1 MCS = 0 Maximum Pulse Width MCS = 1 2 × TI00 input cycle 216 × 1/fX 2 × 1/fX 22 (400 ns) (800 ns) 22 × 1/fX (800 ns) 23 × 1/fX (1.6 µs) 216 — (400 ns) 23 × 1/fX (1.6 µs) 24 × 1/fX (3.2 µs) 2 × watch timer output cycle 216 × 1/fX (13.1 ms) 217 × 1/fX (26.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.3 16-Bit Timer/Event Counter Configuration The 16-bit timer/event counter consists of the following hardware. Table 8-4.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-2.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (1) Capture/compare register 00 (CR00) CR00 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC00) of capture/compare control register 0 (CRC0).
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Caution If the valid edge of the TIO0/P00 pin is input while CR01 is read, CR01 does not perform the capture operation and retains the current data. However, the interrupt request flag (PIF0) is set. (3) 16-bit timer register (TM0) TM0 is a 16-bit register which counts the count pulses. TM0 is read by a 16-bit memory manipulation instruction. When TM0 is read, capture/compare register 01 (CR01) should first be set as a capture register. RESET input sets TM0 to 0000H.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-3. Timer Clock Selection Register 0 Format Symbol <7> 6 5 4 3 2 1 0 Address After Reset R/W FF40H 00H R/W TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00 PCL Output Clock Selection TCL03 TCL02 TCL01 TCL00 MCS = 1 MCS = 0 0 0 0 0 fXT (32.768 kHz) 0 1 0 1 fXX fX (5.0 MHz) fX/2 0 1 1 0 fXX/2 fX/2 (2.
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CHAPTER 8 Remarks 1. fXX 16-BIT TIMER/EVENT COUNTER : Main system clock frequency (fX or fX/2) 2. fX : Main system clock oscillation frequency 3. fXT : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5. TM0 : 16-bit timer register 6. MCS : Bit 0 of oscillation mode selection register (OSMS) 7. Figures in parentheses apply to operation with fX = 5.0 MHz of fXT = 32.768 kHz.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-4.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) Capture/compare control register 0 (CRC0) This register controls the operation of the capture/compare registers (CR00, CR01). CRC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CRC0 value to 04H. Figure 8-5.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-6.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (5) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P30/TO0 pin for timer output, set PM30 and output latch of P30 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 value to FFH. Figure 8-7.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (6) External interrupt mode register 0 (INTM0) This register is used to set INTP0 to INTP2 valid edges. INTM0 is set with an 8-bit memory manipulation instruction. RESET input sets INTM0 value to 00H. Figure 8-8.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (7) Sampling clock select registers (SCS) This register sets clocks which undergo clock sampling of valid edges to be input to INTP0. When remote controlled reception is carried out using INTP0, digital noise is removed with sampling clock. SCS is set with an 8-bit memory manipulation instruction. RESET input sets SCS value to 00H. Figure 8-9.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5 16-Bit Timer/Event Counter Operations 8.5.1 Interval timer operations Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-10 allows operation as an interval timer. Interrupt requests are generated repeatedly using the count value set in 16-bit capture/compare register 00 (CR00) beforehand as the interval.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-11. Interval Timer Configuration Diagram 16-Bit Capture/Compare Register 00 (CR00) INTTM00 INTTM3 fXX/2 2 Selector 2fXX fXX OVF0 16-Bit Timer Register (TM0) fXX/2 TI00/P00/INTP0 Clear Circuit Figure 8-12.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-6. 16-Bit Timer/Event Counter Interval Times Minimum Interval Time Maximum Interval Time Resolution TCL06 TCL05 TCL04 0 0 0 0 0 1 Setting prohibited 2 × 1/fX (400 ns) Setting prohibited 216 × 1/fX (13.1 ms) Setting prohibited 1/fX (200 ns) 0 1 0 2 × 1/fX (400 ns) 22 × 1/fX (800 ns) 216 × 1/fX (13.1 ms) 217 × 1/fX (26.2 ms) 1/fX (200 ns) 2 × 1/fX (400 ns) 0 1 1 22 × 1/fX (800 ns) 23 × 1/fX (1.6 µs) 217 × 1/fX (26.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-13.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER By integrating 14-bit resolution PWM pulses with an external low-pass filter, they can be converted to an analog voltage and used for electronic tuning and D/A converter applications, etc. The analog output voltage (VAN) used for D/A conversion with the configuration shown in Figure 8-14 is as follows. VAN = VREF × capture/compare register 00 (CR00) value 216 VREF: External switching circuit reference voltage Figure 8-14.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.3 PPG output operations Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-16 allows operation as PPG (Programmable Pulse Generator) output.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.4 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00/P00 pin and TI01/P01 pin using the 16-bit timer register (TM0). There are two measurement methods: measuring with TM0 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI00/P00 pin.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-18. Configuration Diagram for Pulse Width Measurement by Free-Running Counter INTTM3 Selector 2fXX fXX fXX/2 fXX/2 16-Bit Timer Register (TM0) OVF0 2 16-Bit Capture/Compare Register 01 (CR01) TI00/P00/INTP00 INTP0 Internal Bus Figure 8-19.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) Measurement of two pulse widths with free-running counter When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-20), it is possible to simultaneously measure the pulse widths of the two signals input to the TI00/P00 pin and the TI01/P01 pin.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-21.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) Pulse width measurement with free-running counter and two capture registers When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-22), it is possible to measure the pulse width of the signal input to the TI00/P00 pin.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-23.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Pulse width measurement by means of restart When input of a valid edge to the TI00/P00 pin is detected, the count value of the 16-bit timer register (TM0) is taken into 16-bit capture/compare register 01 (CR01), and then the pulse width of the signal input to the TI00/P00 pin is measured by clearing TM0 and restarting the count (see register settings in Figure 8-24).
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.5 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI00/P00 pin with the 16-bit timer register (TM0). TM0 is incremented each time the valid edge specified with the external interrupt mode register 0 (INTM0) is input. When the TM0 counted value matches the 16-bit capture/compare register 00 (CR00) value, TM0 is cleared to 0 and the interrupt request signal (INTTM00) is generated.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-27. External Event Counter Configuration Diagram 16-Bit Capture/Compare Register 00 (CR00) INTTM00 Clear OVF0 16-Bit Timer Register (TM0) TI00 Valid Edge INTP0 16-Bit Capture/Compare Register 01 (CR01) Internal Bus Figure 8-28.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.6 Square-wave output operation Operates as square wave output with any selected frequency at intervals of the count value preset to the 16-bit capture/compare register 00 (CR00). The TO0/P30 pin output status is reversed at intervals of the count value preset to CR00 by setting bit 0 (TOE0) and bit 1 (TOC01) of the 16-bit timer output control register (TOC0) to 1. This enables a square wave with any selected frequency to be output. Figure 8-29.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-30. Square-Wave Output Operation Timing Count Clock TM0 Count Value 0000 0001 CR00 0002 N-1 N 0000 0001 0002 N-1 N 0000 N INTTM0 TO0 Pin Output Table 8-7. 16-Bit Timer/Event Count Square-Wave Output Ranges Minimum Pulse Width MCS = 1 MCS = 0 2 × TI00 input cycle Maximum Pulse Width MCS = 1 216 × TI00 input cycle 2 × 1/fX — MCS = 0 Resolution MCS = 1 TI00 input edge cycle 216 × 1/fX — (400 ns) MCS = 0 1/fX — (13.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.7 One-shot pulse output operation It is possible to output one-shot pulses synchronized with a software trigger or an external trigger (TI00/P00 pin input).
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-32. Timing of One-Shot Pulse Output Operation Using Software Trigger Set 0CH to TMC0 (TM0 count start) Count Clock TM0 Count Value 0000 0001 N N+1 0000 N-1 N M-1 M 0000 0001 0002 CR01 Set Value N N N N CR00 Set Value M M M M OSPT INTTM01 INTTM00 TO0 Pin Output Caution The 16-bit timer register starts operation at the moment a value other than 0, 0, 0 (operation stop mode) is set to TMC01 to TMC03, respectively.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) One-shot pulse output using external trigger If the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16-bit timer output control register (TOC0) are set as shown in Figure 8-33, a one-shot pulse is output from the TO0/ P30 pin with a TI00/P00 valid edge as an external trigger.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-34.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.6 16-Bit Timer/Event Counter Operating Precautions (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. This is because the 16-bit timer register (TM0) starts asynchronously with the count pulse. Figure 8-35.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Capture register data retention timings If the valid edge of the TI00/P00 pin is input during 16-bit capture/compare register 01 (CR01) read, CR01 holds data without carrying out capture operation. However, the interrupt request flag (PIF0) is set upon detection of the valid edge. Figure 8-37.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (7) Operation of OVF0 flag OFV0 flag is set to 1 in the following case. The clear & start mode on match between TM0 and CR00 is selected. ↓ CR00 is set to FFFFH. ↓ When TM0 is counted up from FFFFH to 0000H. Figure 8-38.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.1 8-Bit Timer/Event Counters 1 and 2 Functions For the 8-bit timer/event counters 1 and 2, two modes are available. One is a mode for two-channel 8-bit timer/ event counters to be used separately (the 8-bit timer/event counter mode) and the other is a mode for the 8-bit timer/ event counter to be used as 16-bit timer/event counter (the 16-bit timer/event counter mode). 9.1.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (1) 8-bit interval timer Interrupt requests are generated at the preset time intervals. Table 9-1. 8-Bit Timer/Event Counters 1 and 2 Interval Times Minimum Interval Time Maximum Interval Time MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 2 × 1/fX 22 × 1/fX 29 × 1/fX 210 × 1/fX 2 × 1/fX 22 × 1/fX (400 ns) (800 ns) (102.4 µs) (204.8 µs) (400 ns) (800 ns) 22 × 1/fX 23 × 1/fX 210 × 1/fX 211 × 1/fX 22 × 1/fX 23 × 1/fX (800 ns) (1.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 9-2. 8-Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges Minimum Pulse Width Maximum Pulse Width Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 2 × 1/fX 22 × 1/fX 29 × 1/fX 210 × 1/fX 2 × 1/fX 22 × 1/fX (400 ns) (800 ns) (102.4 µs) (204.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.1.2 16-bit timer/event counter mode (1) 16-bit interval timer Interrupt requests can be generated at the preset time intervals. Table 9-3. Interval Times when 8-Bit Timer/Event Counters 1 and 2 are Used as 16-Bit Timer/Event Counters Minimum Interval Time Maximum Interval Time MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 2 × 1/fX 22 × 1/fX 217 × 1/fX 218 × 1/fX 2 × 1/fX 22 × 1/fX (400 ns) (800 ns) (26.2 ms) (52.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 9-4.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.2 8-Bit Timer/Event Counters 1 and 2 Configurations The 8-bit timer/event counters 1 and 2 consist of the following hardware. Table 9-5.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-1.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-2. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1 Level F/F (LV1) LVR1 R Q TO1/P31 S LVS1 TOC11 P31 Output Latch INV PM31 INTTM1 TOE1 Remark The section in the broken line is an output control circuit. Figure 9-3. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 2 Level F/F (LV2) fSCK LVR2 R Q LVS2 TOC15 TO2/P32 S P32 Output Latch INV INTTM2 TOE2 Remarks 1.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (1) Compare registers 10 and 20 (CR10, CR20) These are 8-bit registers to compare the value set to CR10 to the 8-bit timer register 1 (TM1) count value, and the value set to CR20 to the 8-bit timer register 2 (TM2) count value, and, if they match, generate an interrupt request (INTTM1 and INTTM2, respectively). This register can also be used as the register which holds the interval time when setting TM1 and TM2 to interval timer operation.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-4.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) 8-bit timer mode control register (TMC1) This register enables/stops operation of 8-bit timer registers 1 and 2 and sets the operating mode of 8-bit timer register 1 and 2. TMC1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC1 to 00H. Figure 9-5.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) 8-bit timer output control register (TOC1) This register controls operation of 8-bit timer/event counter output control circuits 1 and 2. It sets/resets the R-S flip-flops (LV1 and LV2) and enables/disables inversion and 8-bit timer output of 8-bit timer registers 1 and 2. TOC1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TOC1 to 00H. Figure 9-6.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (4) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P31/TO1 and P32/TO2 pins for timer output, set PM31, PM32, and output latches of P31 and P32 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH. Figure 9-7.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.4 8-Bit Timer/Event Counters 1 and 2 Operations 9.4.1 8-bit timer/event counter mode (1) Interval timer operations The 8-bit timer/event counters 1 and 2 operate as interval timers which generate interrupt requests repeatedly at intervals of the count value preset to 8-bit compare registers 10 and 20 (CR10 and CR20).
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Table 9-6.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Table 9-7.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter operation The external event counter counts the number of external clock pulses to be input to the TI1/P33 and TI2/ P34 pins with 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 and TM2 are incremented each time the valid edge specified with the timer clock select register (TCL1) is input. Either the rising or falling edge can be selected.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) Square-wave output operation Operates as square wave output with any selected frequency at intervals of the count value preset to 8-bit compare register 10 and 20 (CR10, CR20). The TO1/P31 or TO2/P32 pin output status is reversed at intervals of the count value preset to CR10 or CR20 by setting bit 0 (TOE1) or bit 4 (TOE2) of the 8-bit timer output control register (TOC1) to 1. This enables a square wave with any selected frequency to be output. Table 9-8.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-10. Square-Wave Output Operation Timing Count Clock TM1 Count Value 00 CR10 01 02 N-1 N 00 01 02 N-1 N 00 N INTTM1 TO1 Pin OutputNote Note The initial value of TO1 pin output can be set with the bits 2 and 3 (LVR1, LVS1) of 8-bit timer output control register (TOC1).
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.4.2 16-bit timer/event counter mode When bit 2 (TMC12) of the 8-bit timer mode control register (TMC1) is set to 1, the 16-bit timer/event counter mode is set. In this mode, the count clock is set with bits 0 to 3 (TCL10 to TCL13) of timer clock select register 1 (TCL1), and the overflow signal of 8-bit timer register 1 (TM1) becomes the count clock of 8-bit timer register 2 (TM2).
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Table 9-9.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter operations The external event counter counts the number of external clock pulses to be input to the TI1/P33 pin with 2channel 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 is incremented each time the valid edge specified with the timer clock select register 1 (TCL1) is input. When TM1 overflows, TM2 is incremented with the overflow signal as the count clock. Either the rising or falling edge can be selected.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) Square-wave output operation Operates as square wave output with any selected frequency at intervals of the count value preset to 8-bit compare registers 10 and 20 (CR10, CR20). When setting the count value, set the value of higher 8 bits to CR20 and the value of lower 8 bits to CR10.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-13. Square-Wave Output Operation Timing Count Clock TM1, TM2 Count Value 0000 0001 0002 CR10, CR20 N-1 N 0000 0001 0002 N-1 N 0000 N INTTM2 TO2 Pin OutputNote Note The initial value of TO2 pin output can be set with the bits 6 and 7 (LVR2, LVS2) of 8-bit timer output control register (TOC1). 9.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) 8-bit compare register 10 and 20 setting The 8-bit compare registers 10 and 20 (CR10 and CR20) can be set to 00H. Thus, when these 8-bit compare registers are used as event counters, one-pulse count operation can be carried out. When the 8-bit compare register is used as 16-bit timer/event counter, write data to CR10 and CR20 after setting bit 0 (TCE1) of the 8-bit timer mode control register 1 to 0 and stopping timer operation. Figure 9-15.
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[MEMO] 240
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CHAPTER 10 WATCH TIMER 10.1 Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. (1) Watch timer When the 32.768 kHz subsystem clock is used, a flag (WTIF) is set at 0.5 second or 0.25 second intervals. When the 4.19 MHz (standard: 4.194304 MHz) main system clock is used, a flag (WTIF) is set at 0.5 second or 0.25 second intervals. Caution 0.5-second intervals cannot be generated with the 5.
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CHAPTER 10 WATCH TIMER 10.2 Watch Timer Configuration The watch timer consists of the following hardware. Table 10-2. Watch Timer Configuration Item Counter Control register Configuration 5 bits × 1 Timer clock select register 2 (TCL2) Watch timer mode control register (TMC2) 10.3 Watch Timer Control Registers The following two types of registers are used to control the watch timer.
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CHAPTER 10 WATCH TIMER Figure 10-1.
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CHAPTER 10 WATCH TIMER Figure 10-2. Timer Clock Select Register 2 Format Symbol 7 5 6 4 3 TCL2 TCL27 TCL26 TCL25 TCL24 0 2 1 0 TCL22 TCL21 TCL20 Address FF42H After Reset 00H R/W R/W Watchdog Timer Count Clock Selection TCL22 TCL21 TCL20 MCS = 1 MCS = 0 0 0 0 f XX /2 3 f X /23 (625 kHz) f X /24 (313 kHz) 0 0 1 f XX /24 f X /24 (313 kHz) f X /25 (156 kHz) 0 1 0 f XX /25 f X /25 (156 kHz) f X /26 (78.1 kHz) 0 1 1 f XX /26 f X /26 (78.1 kHz) f X /27 (39.
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CHAPTER 10 WATCH TIMER (2) Watch timer mode control register (TMC2) This register sets the watch timer operating mode, watch flag set time and prescaler interval time and enables/ disables prescaler and 5-bit counter operations. TMC2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC2 to 00H. Figure 10-3.
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CHAPTER 10 WATCH TIMER 10.4 Watch Timer Operations 10.4.1 Watch timer operation When the 32.768-kHz subsystem clock or 4.19-MHz main system clock is used, the timer operates as a watch timer with a 0.5-second or 0.25-second interval. The watch timer sets the test input flag (WTIF) to 1 at the constant time interval. The standby state (STOP mode/ HALT mode) can be cleared by setting WTIF to 1.
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CHAPTER 11 WATCHDOG TIMER 11.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM) (The watchdog timer and interval timer cannot be used at the same time). (1) Watchdog timer mode An inadvertent program loop (runaway) is detected. Upon detection of the runaway, a non-maskable interrupt request or RESET can be generated. Table 11-1.
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CHAPTER 11 WATCHDOG TIMER (2) Interval timer mode Interrupt requests are generated at the preset time intervals. Table 11-2. Interval Times Interval Time MCS = 1 CS = 0 211 × 1/fXX 211 × 1/fX (410 µs) 212 × 1/fX (819 µs) 212 × 1/fXX 212 × 1/fX (819 µs) 213 × 1/fX (1.64 ms) 213 × 1/fXX 213 × 1/fX (1.64 ms) 214 × 1/fX (3.28 ms) 214 × 1/fXX 214 × 1/fX (3.28 ms) 215 × 1/fX (6.55 ms) 215 × 1/fXX 215 × 1/fX (6.55 ms) 216 × 1/fX (13.1 ms) 216 × 1/fXX 216 × 1/fX (13.1 ms) 217 × 1/fX (26.
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CHAPTER 11 WATCHDOG TIMER 11.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 11-3. Watchdog Timer Configuration Item Configuration Timer clock select register 2 (TCL2) Control register Watchdog timer mode control register (WDTM) Figure 11-1.
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CHAPTER 11 WATCHDOG TIMER 11.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock. TCL2 is set with 8-bit memory manipulation instruction. RESET input sets TCL2 to 00H.
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CHAPTER 11 WATCHDOG TIMER Figure 11-2. Timer Clock Select Register 2 Format Symbol 7 5 6 4 3 TCL2 TCL27 TCL26 TCL25 TCL24 0 2 1 0 TCL22 TCL21 TCL20 Address FF42H After Reset 00H R/W R/W Watchdog Timer Count Clock Selection TCL22 TCL21 TCL20 MCS = 1 3 MCS = 0 3 0 0 0 f XX /2 f X /2 (625 kHz) f X /24 (313 kHz) 0 0 1 f XX /24 f X /24 (313 kHz) f X /25 (156 kHz) 0 1 0 f XX /25 f X /25 (156 kHz) f X /26 (78.1 kHz) 0 1 1 f XX /26 f X /26 (78.1 kHz) f X /27 (39.
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CHAPTER 11 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 11-3.
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CHAPTER 11 WATCHDOG TIMER 11.4 Watchdog Timer Operations 11.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any runaway. The watchdog timer count clock (runaway detection time interval) can be selected with bits 0 to 2 (TCL20 to TCL22) of the timer clock select register 2 (TCL2). Watchdog timer starts by setting bit 7 (RUN) of WDTM to 1.
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CHAPTER 11 WATCHDOG TIMER 11.4.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0. A count clock (interval time) can be selected by the bits 0 through 2 (TCL20 through TCL22) of the timer clock select register 2 (TCL2). By setting the bit 7 (RUN) of WDTM to 1, the watchdog timer starts operating as an interval timer.
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CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI. Clocks selected with the timer clock select register 0 (TCL0) are output from the PCL/ P35 pin. Follow the procedure below to output clock pulses. (1) Select the clock pulse output frequency (with clock pulse output disabled) with bits 0 to 3 (TCL00 to TCL03) of TCL0.
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CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.2 Clock Output Control Circuit Configuration The clock output control circuit consists of the following hardware. Table 12-1. Clock Output Control Circuit Configuration Item Control register Configuration Timer clock select register 0 (TCL0) Port mode register 3 (PM3) Figure 12-2.
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CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.3 Clock Output Function Control Registers The following two types of registers are used to control the clock output function. • Timer clock select register 0 (TCL0) • Port mode register 3 (PM3) (1) Timer clock select register 0 (TCL0) This register sets PCL output clock. TCL0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TCL0 to 00H. Remark Besides setting PCL output clock, TCL0 sets the 16-bit timer register count clock.
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CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT Figure 12-3. Timer Clock Select Register 0 Format Symbol <7> 6 5 4 3 2 1 0 Address TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00 FF40H After Reset 00H R/W R/W PCL Output Clock Selection TCL03 TCL02 TCL01 TCL00 MCS = 1 MCS = 0 f X /2 (2.5 MHz) 0 0 0 0 f XT (32.768 kHz) 0 1 0 1 f XX fX 0 1 1 0 f XX /2 f X /2 (2.5 MHz) f X /22 (1.25 MHz) 0 1 1 1 f XX /22 f X /22 (1.
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CHAPTER 12 Remarks 1. fXX CLOCK OUTPUT CONTROL CIRCUIT : Main system clock frequency (fX or fX/2) 2. fX : Main system clock oscillation frequency 3. fXT : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5. TM0 : 16-bit timer register 6. MCS : Oscillation mode selection register (OSMS) bit 0 7. Figures in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz. (2) Port mode register 3 (PM3) This register set port 3 input/output in 1-bit units.
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[MEMO] 260
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CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13.1 Buzzer Output Control Circuit Functions The buzzer output control circuit outputs 1.2 kHz, 2.4 kHz, 4.9 kHz, or 9.8 kHz frequency square waves. The buzzer frequency selected with timer clock select register 2 (TCL2) is output from the BUZ/P36 pin. Follow the procedure below to output the buzzer frequency. (1) Select the buzzer output frequency with bits 5 to 7 (TCL25 to TCL27) of TCL2. (2) Set the P36 output latch to 0.
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CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13.3 Buzzer Output Function Control Registers The following two types of registers are used to control the buzzer output function. • Timer clock select register 2 (TCL2) • Port mode register 3 (PM3) (1) Timer clock select register 2 (TCL2) This register sets the buzzer output frequency. TCL2 is set with an 8-bit memory manipulation instruction. RESET input sets TCL2 to 00H.
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CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT Figure 13-2. Timer Clock Select Register 2 Format Symbol 7 5 6 4 3 TCL2 TCL27 TCL26 TCL25 TCL24 0 2 1 0 TCL22 TCL21 TCL20 Address FF42H After Reset 00H R/W R/W Watchdog Timer Count Clock Selection TCL22 TCL21 TCL20 MCS = 1 MCS = 0 0 0 0 f XX /23 f X /23 (625 kHz) f X /24 (313 kHz) 0 0 1 f XX /24 f X /24 (313 kHz) f X /25 (156 kHz) 0 1 0 f XX /25 f X /25 (156 kHz) f X /26 (78.1 kHz) 0 1 1 f XX /26 f X /26 (78.
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CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT (2) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P36/BUZ pin for buzzer output function, set PM36 and output latch of P36 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH. Figure 13-3.
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CHAPTER 14 A/D CONVERTER 14.1 A/D Converter Functions The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an 8-bit resolution. The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/D conversion result register (ADCR). The following two ways are available to start A/D conversion. (1) Hardware start Conversion is started by trigger input (INTP3).
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CHAPTER 14 A/D CONVERTER Figure 14-1.
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CHAPTER 14 A/D CONVERTER (1) Successive approximation register (SAR) This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string and holds the result from the most significant bit (MSB). When up to the least significant bit (LSB) is held (termination of A/D conversion), the SAR contents are transferred to the A/D conversion result register (ADCR).
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CHAPTER 14 A/D CONVERTER (7) AVREF0 pin This pin inputs the A/D converter reference voltage. It converts signals input to ANI0 to ANI7 into digital signals according to the voltage applied between AVREF0 and AVSS. The current flowing in the series resistor string can be reduced by setting the voltage to be input to the AVREF0 pin to AVSS level in standby mode. Caution A serial resistor string of approximately 10 kΩ is connected between the AVREF0 pin and the AVSS pin.
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CHAPTER 14 A/D CONVERTER 14.3 A/D Converter Control Registers The following three types of registers are used to control the A/D converter. • A/D converter mode register (ADM) • A/D converter input select register (ADIS) • External interrupt mode register 1 (INTM1) (1) A/D converter mode register (ADM) This register sets the analog input channel for A/D conversion, conversion time, conversion start/stop and external trigger. ADM is set with a 1-bit or 8-bit memory manipulation instruction.
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CHAPTER 14 A/D CONVERTER Figure 14-3. A/D Converter Mode Register Format Symbol <7> <6> 5 ADM CS TRG FR1 4 3 2 1 0 FR0 ADM3 ADM2 ADM1 HSC ADM3 ADM2 ADM1 After Reset 01H Address FF80H R/W R/W Analog Input Channel Selection 0 0 0 ANI0 0 0 1 ANI1 0 1 0 ANI2 0 1 1 ANI3 1 0 0 ANI4 1 0 1 ANI5 1 1 0 ANI6 1 1 1 ANI7 Note 1 A/D Conversion Time Selection FR1 FR0 HSC fX = 5.0 MHz Operation MCS = 1 fX = 4.19 MHz Operation MCS = 0 MCS = 1 MCS = 0 160/f X (38.
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CHAPTER 14 A/D CONVERTER (2) A/D converter input select register (ADIS) This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels or ports. Pins other than those selected as analog input can be used as input/output ports. ADIS is set with an 8-bit memory manipulation instruction. RESET input sets ADIS to 00H. Cautions 1. Set the analog input channel in the following order. (1) Set the number of analog input channels with ADIS.
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CHAPTER 14 A/D CONVERTER (3) External interrupt mode register 1 (INTM1) This register sets the valid edge for INTP3 to INTP6. INTM1 is set with an 8-bit memory manipulation instruction. RESET input sets INTM1 to 00H. Figure 14-5.
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CHAPTER 14 A/D CONVERTER 14.4 A/D Converter Operations 14.4.1 Basic operations of A/D converter (1) Set the number of analog input channels with A/D converter input select register (ADIS). (2) From among the analog input channels set with ADIS, select one channel for A/D conversion with A/D converter mode register (ADM). (3) Sample & hold circuit samples the voltage input to the selected analog input channel.
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CHAPTER 14 A/D CONVERTER Figure 14-6. A/D Converter Basic Operation Conversion Time Sampling Time A/D Converter Operation Sampling SAR Undefined A /D Conversion 80H C0H or 40H ADCR Conversion Result Conversion Result INTAD A/D conversion operations are performed continuously until bit 7 (CS) of ADM is reset (0) by software.
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CHAPTER 14 A/D CONVERTER 14.4.2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (the value stored in A/D conversion result register (ADCR)) is shown by the following expression. VIN ADCR = INT ( × 256 + 0.5) AVREF0 or (ADCR – 0.5) × Where, AVREF0 ≤ VIN < (ADCR + 0.5) × AVREF0 256 256 INT( ) : Function which returns integer parts of value in parentheses.
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CHAPTER 14 A/D CONVERTER 14.4.3 A/D converter operating mode Select one analog input channel from ANI0 to ANI7 with A/D converter input select register (ADIS) and A/D converter mode register (ADM), and start A/D conversion. The following two ways are available to start A/D conversion. • Hardware start: Conversion is started by trigger input (INTP3). • Software start: Conversion is started by setting ADM.
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CHAPTER 14 A/D CONVERTER (2) A/D conversion operation in software start When bit 6 (TRG) and bit 7 (CS) of A/D converter mode register (ADM) are set to 0 and 1, respectively, the A/D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (ADM1 to ADM3) of ADM. Upon termination of the A/D conversion, the conversion result is stored in the A/D conversion result register (ADCR) and the interrupt request signal (INTAD) is generated.
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CHAPTER 14 A/D CONVERTER 14.5 A/D Converter Cautions (1) Power consumption in standby mode The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode or in HALT mode with the subsystem clock. As a current still flows in the AVREF0 pin at this time, this current must be cut in order to minimize the overall system power dissipation. In Figure 14-10, the power dissipation can be reduced by outputting a low-level signal to the output port in standby mode.
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CHAPTER 14 A/D CONVERTER (3) Noise countermeasures In order to maintain 8-bit resolution, attention must be paid to noise on pins AVREF0 and ANI0 to ANI7. Since the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 14-11 in order to reduce noise. Figure 14-11.
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CHAPTER 14 A/D CONVERTER (6) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the A/D converter mode register (ADM) is changed. If an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may have been set immediately before the ADM rewrite.
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CHAPTER 15 D/A CONVERTER 15.1 D/A Converter Functions The D/A converter converts a digital input into an analog value. It consists of two 8-bit resolution channels of voltage output type D/A converter. The conversion method used is the R-2R resistor ladder method. Start the A/D conversion by setting the DACE0 and DACE1 of the D/A converter mode register (DAM). There are two types of modes for the D/A converter, as follows.
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CHAPTER 15 D/A CONVERTER 15.2 D/A Converter Configuration The D/A converter consists of the following hardware. Table 15-1. D/A Converter Configuration Item Configuration D/A conversion value set register 0 (DACS0) Register D/A conversion value set register 1 (DACS1) Control register D/A converter mode register (DAM) Figure 15-1.
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CHAPTER 15 D/A CONVERTER (1) D/A conversion value set register 0, 1 (DACS0, DACS1) DACS0 and DACS1 are registers that set the values to determine analog voltage output to the ANO0 and ANO1 pins, respectively. DACS0 and DACS1 are set with 8-bit memory manipulation instructions. RESET input sets these registers to 00H. Analog voltage output to the ANO0 and ANO1 pins is determined by the following expression. ANOn output voltage = AVREF1 × where, DACSn 256 n = 0, 1 Cautions 1.
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CHAPTER 15 D/A CONVERTER 15.3 D/A Converter Control Registers The D/A converter mode register (DAM) controls the D/A converter. This register sets D/A converter operation enable/stop. The DAM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 15-2.
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CHAPTER 15 D/A CONVERTER 15.4 Operations of D/A Converter (1) Select the channel 0 operating mode and channel 1 operating mode by DAM4 and DAM5 of D/A converter mode register (DAM), respectively. (2) Set the data corresponding to the analog voltages output to the ANO0/P130 and ANO1/P131 pins to the D/A conversion value setting registers 0 and 1 (DACS0 and DACS1), respectively. (3) The channel 0 and channel 1 D/A conversion operations can be started by setting DACE0 and DACE1 of the DAM, respectively.
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CHAPTER 15 D/A CONVERTER 15.5 Cautions Related to D/A Converter (1) Output impedance of D/A converter Because the output impedance of the D/A converter is high, use of current flowing from the ANOn pins (n = 0,1) is prohibited. If the input impedance of the load for the converter is low, insert a buffer amplifier between the load and the ANOn pins. In addition, wiring from the ANOn pins to the buffer amplifier or the load should be as short as possible (because of high output impedance).
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) The µPD78054 subseries incorporates three channels of serial interfaces. Differences between channels 0, 1, and 2 are as follows (Refer to CHAPTER 18 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1. Refer to CHAPTER 19 SERIAL INTERFACE CHANNEL 2 for details of the serial interface channel 2). Table 16-1.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) 16.1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following four modes. • Operation stop mode • 3-wire serial I/O mode • SBI (serial bus interface) mode • 2-wire serial I/O mode Caution Do not switch the operation mode (3-wire serial I/O, 2-wire serial I/O, SBI) of serial interface channel 0. Switch the operation mode after stopping the serial operation.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) (4) 2-wire serial I/O mode (MSB-first) This mode is used for 8-bit data transfer using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1). This mode enables to cope with any one of the possible data transfer formats by controlling the SCK0 level and the SB0 or SB1 output level. Thus, the handshake line previously necessary for connection of two or more devices can be used as input/output ports. Figure 16-1.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) 16.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware. Table 16-2.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) Figure 16-2.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-bit memory manipulation instruction. When bit 7 (CSIE0) of serial operating mode register 0 (CSIM0) is 1, writing data to SIO0 starts serial operation.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) (3) SO0 latch This latch holds SI0/SB0/P25 and SO0/SB1/P26 pin levels. It can be directly controlled also by software. In the SBI mode, this latch is set upon termination of the 8th serial clock. (4) Serial clock counter This counter counts the serial clocks to be output and input during transmission/reception and to check whether 8-bit data has been transmitted/received.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) 16.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. • Timer clock select register 3 (TCL3) • Serial operating mode register 0 (CSIM0) • Serial bus interface control register (SBIC) • Interrupt timing specify register (SINT) (1) Timer clock select register 3 (TCL3) This register sets the serial clock of serial interface channel 0.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) Figure 16-3. Timer Clock Select Register 3 Format Symbol 7 6 5 4 3 2 1 0 TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 Address After Reset FF43H 88H R/W R/W Serial Interface Channel 0 Serial Clock Selection TCL33 TCL32 TCL31 TCL30 MCS = 1 MCS = 0 0 1 1 0 fXX/2 Setting prohibited fX/22 (1.25 MHz) 0 1 1 1 fXX/22 fX/22 (1.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) (2) Serial operating mode register 0 (CSIM0) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal. CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H. Caution Do not switch the operation mode (3-wire serial I/O, 2-wire serial I/O, SBI) of serial interface channel 0.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) Figure 16-4.
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SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) CHAPTER 16 (3) Serial bus interface control register (SBIC) This register sets serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Figure 16-5.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) Figure 16-5. Serial Bus Interface Control Register Format (2/2) R/W ACKE 0 Acknowledge Signal Automatic Output Control Acknowledge signal automatic output disable (output with ACKT enable) Before completion of transfer Acknowledge signal is output in synchronization with the 9th clock falling edge of SCK0 (automatically output when ACKE = 1).
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/P27 pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Figure 16-6.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) 16.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. • Operation stop mode • 3-wire serial I/O mode • SBI mode • 2-wire serial I/O mode 16.4.1 Operation stop mode Serial transfer is not carried out in the operation stop mode. Thus, power consumption can be reduced.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) 16.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K series. Communication is carried out with three lines of serial clock (SCK0), serial output (SO0), and serial input (SI0).
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CHAPTER 16 Symbol <7> <6> <5> CSIM0 CSIE0 COI R/W R/W SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) 4 WUP 3 2 1 CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 FF60H After Reset 00H 0 × Input Clock to SCK0 pin from off-chip 1 0 8-bit timer register 2 (TM2) output 1 1 Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) CSIM CSIM CSIM Operation PM25 P25 PM26 P26 PM27 P27 03 Mode 02 0 × 0 R/W Address R/W R/WNote 1 Serial Interface Channel 0 Clock Selection CSIM01
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> <2> <1> <0> SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT R/W R/W FF61H After Reset 00H R/W R/W RELT When RELT = 1, SO0 Iatch is set to 1. After SO0 Iatch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0). The transmitted data is held in the SO0 latch and is output from the SO0 pin.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 16-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form. MSB/LSB switching as the start bit can be specified with bit 2 (CSIM02) of the serial operating mode register 0 (CSIM0). Figure 16-9.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) 16.4.3 SBI mode operation SBI (Serial Bus Interface) is a high-speed serial interface in compliance with the NEC serial bus format. SBI uses a single master device and employs the clocked serial I/O format with the addition of a bus configuration function. This function enables devices to communicate using only two lines.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) (1) SBI functions In the conventional serial I/O format, when a serial bus is configured by connecting two or more devices, many ports and wiring are necessary, to provide chip select signal to identify command and data, and to judge the busy state, because only the data transfer function is available. If these operations are to be controlled by software, the software must be heavily loaded.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) (2) SBI definition The SBI serial data format and the signals to be used are defined as follows. Serial data to be transferred with SBI consists of three kinds of data: “address”, “command”, and “data”. Figure 16-11 shows the address, command, and data transfer timings. Figure 16-11.
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SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) CHAPTER 16 (a) Bus release signal (REL) The bus release signal is a signal with the SB0 (SB1) line which has changed from the low level to the high level when the SCK0 line is at the high level (without serial clock output). This signal is output by the master device. Figure 16-12. Bus Release Signal SCK0 "H" SB0 (SB1) Caution A transition of the SB0 (SB1) pin from low to high while the SCK0 line is high is interpreted as a bus release signal.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) (c) Address An address is 8-bit data which the master device outputs to the slave device connected to the bus line in order to select a particular slave device. Figure 16-14. Addresses 1 SCK0 A7 SB0 (SB1) 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 A0 Address Bus Release Signal Command Signal 8-bit data following bus release and command signals is defined as an “address”.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) (d) Command and data The master device transmits commands to, and transmits/receives data to/from the slave device selected by address transmission. Figure 16-16. Commands SCK0 1 SB0 (SB1) C7 2 C6 3 C5 4 5 C4 C3 6 7 8 C2 C1 C0 6 7 8 Command Command Signal Figure 16-17. Data SCK0 SB0 (SB1) 1 D7 2 D6 3 D5 4 5 D4 D3 D2 D1 D0 Data 8-bit data following a command signal is defined as “command” data.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) (e) Acknowledge signal (ACK) The acknowledge signal is used to check serial data reception between transmitter and receiver. Figure 16-18. Acknowledge Signal [When output in synchronization with 11th clock SCK0] SCK0 8 9 SB0 (SB1) 10 11 ACK [When output in synchronization with 9th clock SCK0] SCK0 SB0 (SB1) Remark 8 9 ACK The dotted line indicates READY status.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) (f) Busy signal (BUSY) and ready signal (READY) The BUSY signal is intended to report to the master device that the slave device is preparing for data transmission/reception. The READY signal is intended to report to the master device that the slave device is ready for data transmission/reception. Figure 16-19.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) (3) Register setting The SBI mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specify register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.
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SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) CHAPTER 16 (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. The shaded area is used in the SBI mode. Symbol <7> <6> <5> <4> <3> <2> <1> <0> SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT R/W R/WNote CMDT Used for command signal output. When CMDT = 1, SO0 Iatch is cleared to (0). After SO0 latch clearance, automatically cleared to (0).
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CHAPTER 16 R ACKD SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) Acknowledge Detection Clear Conditions (ACKD = 0) • SCK0 fall immediately after the busy mode is released during the transfer start instruction execution.
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SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) CHAPTER 16 (c) Interrupt timing specify register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) (4) Various signals Figures 16-20 to 16-25 show various signals and flag operations in SBI. Table 16-3 lists various signals in SBI. Figure 16-20. RELT, CMDT, RELD, and CMDD Operations (Master) Slave address write to SIO0 (Transfer Start Instruction) SIO0 SCK0 SB0 (SB1) RELT CMDT RELD CMDD Figure 16-21.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) Figure 16-22. ACKT Operation SCK0 SB0 (SB1) 6 7 D2 8 D1 9 D0 ACK ACKT When set during this period Caution Do not set ACKT before termination of transfer.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) Figure 16-23.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) Figure 16-24.
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Table 16-3. Various Signals in SBI Mode (1/2) Signal Name Bus release signal (REL) Busy signal (BUSY) SB0 (SB1) rising edge when SCK0 = 1 SCK0 Condition Master Master/ slave Slave SB0 (SB1) falling edge when SCK0 = 1 Low-level signal to be output to SB0 (SB1) during one-clock period of SCK0 after completion of serial reception • CMDT set • CMDD set i) Transmit data is an address after REL signal output. ii) REL signal is not output and transmit data is an command.
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Table 16-3. Various Signals in SBI Mode (2/2) Signal Name Master Synchronous clock to output address/command/ data, ACK signal, synchronous BUSY signal, etc. Address/command/ data are transferred with the first eight synchronous clocks.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) (5) Pin configuration The serial clock pin SCK0 and serial data bus pin SB0 (SB1) have the following configurations. (a) SCK0 ............ Serial clock input/output pin <1> Master ... CMOS and push-pull output <2> Slave ..... Schmitt input (b) SB0 (SB1) .... Serial data input/output dual-function pin Both master and slave devices have an N-ch open drain output and a Schmitt input.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) (6) Address match detection method In the SBI mode, the master transmits a slave address to select a specific slave device. Coincidence of the addresses can be automatically detected by hardware. CSIIF0 is set only when the slave address transmitted by the master coincides with the address set to SVA when the wake-up function specify bit (WUP) = 1.
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Figure 16-27.
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Figure 16-28.
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Figure 16-29.
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Figure 16-30.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) (9) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. • Serial interface channel 0 operation control bit (CSIE0) = 1 • Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer. Cautions 1. If CSIE0 is set to “1” after data write to SIO0, transfer does not start. 2.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) (10) Discrimination of slave busy state When device is in the master mode, follow the procedure below to judge whether slave device is in the busy state or not. <1> Detect acknowledge signal (ACK) or interrupt request signal generation. <2> Set the port mode register PM25 (or PM26) of the SB0/P25 (or SB1/P26) pin into the input mode. <3> Read out the pin state (when the pin level is high, the READY state is set).
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) 16.4.4 2-wire serial I/O mode operation The 2-wire serial I/O mode can cope with any communication format by program. Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or SB1). Figure 16-31.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) (1) Register setting The 2-wire serial I/O mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specify register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> <2> <1> <0> SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT R/W R/W Address FF61H After Reset 00H R/W R/W RELT When RELT = 1, SO0 Iatch is set to 1. After SO0 Iatch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) (c) Interrupt timing specify register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H.
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SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) CHAPTER 16 (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge of the serial clock (SCK0).
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) (3) Other signals Figure 16-33 shows RELT and CMDT operations. Figure 16-33. RELT and CMDT Operations SO0 Latch RELT CMDT (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. • Serial interface channel 0 operation control bit (CSIE0) = 1 • Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer. Cautions 1.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries) 16.4.5 SCK0/P27 pin output manipulation Because the SCK0/P27 pin incorporates an output latch, static output is also possible by software in addition to normal serial clock output. P27 output latch manipulation enables any value of SCK0 to be set by software. (SI0/SB0 and SO0/SB1 pin to be controlled with the RELT and CMDT bits of serial bus interface control register (SBIC).) SCK0/P27 pin output manipulating procedure is described below.
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[MEMO] 340
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) The µPD78054Y subseries incorporates three channels of serial interfaces. Differences between channels 0, 1, and 2 are as follows (Refer to CHAPTER 18 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1. Refer to CHAPTER 19 SERIAL INTERFACE CHANNEL 2 for details of the serial interface channel 2). Table 17-1.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) 17.1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following four modes. • Operation stop mode • 3-wire serial I/O mode • 2-wire serial I/O mode • I2C (Inter IC) bus mode Caution Do not switch the operation mode (3-wire serial I/O, 2-wire serial I/O, I2C bus) while the operation of serial interface channel 0 is enabled. Stop the serial operation before switching the operation mode.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (4) I2C (Inter IC) bus mode (MSB-first) This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCL) and serial data bus (SDA0 or SDA1). This mode is in compliance with the I2C bus format. In this mode, the transmitter can output three kinds of data onto the serial data bus: “start condition”, “data”, and “stop condition”, to be actually sent or received.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) 17.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware. Table 17-2.
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SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) CHAPTER 17 Figure 17-2.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel-serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-bit memory manipulation instruction. When bit 7 (CSIE0) of serial operating mode register 0 (CSIM0) is 1, writing data to SIO0 starts serial operation.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (6) Interrupt request signal generator This circuit controls interrupt request signal generation. It generates interrupt request signals according to the settings of interrupt timing specification register (SINT) bits 0 and 1 (WAT0, WAT1) and serial operation mode register 0 (CSIM0) bit 5 (WUP), as shown in Table 17-3.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) 17.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. • Timer clock select register 3 (TCL3) • Serial operating mode register 0 (CSIM0) • Serial bus interface control register (SBIC) • Interrupt timing specify register (SINT) (1) Timer clock select register 3 (TCL3) This register sets the serial clock of serial interface channel 0.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) Figure 17-3. Timer Clock Select Register 3 Format Symbol 7 6 5 4 3 2 1 0 Address TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 After Reset FF43H 88H R/W R/W TCL33 TCL32 TCL31 TCL30 Serial Interface Channel 0 Serial Clock Selection Serial Clock in I2 C Bus Mode Serial Clock in 2-Wire or 3-Wire Serial I/O Mode MCS = 1 MCS = 0 5 M CS = 1 MCS = 0 0 1 1 0 f XX/2 Setting prohibited f X/2 (78.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (2) Serial operating mode register 0 (CSIM0) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal. CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) Figure 17-4.
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SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) CHAPTER 17 (3) Serial bus interface control register (SBIC) This register sets serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Figure 17-5.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) Figure 17-5. Serial Bus Interface Control Register Format (2/2) R/W ACKE 0 1 R ACKD Acknowledge Signal Output Control Note 1 Disables acknowledge signal automatic output. (However, output with ACKT is enabled) Used for reception when 8-clock wait mode is selected or for transmission. Note 2 Enables acknowledge signal automatic output.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/SCL pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Figure 17-6.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) Figure 17-6. Interrupt Timing Specify Register Format (2/2) R/W R/W R SVAM SVA Bit to be Used as Slave Address 0 Bits 0 to 7 1 Bits 1 to 7 SIC INTCSI0 Interrupt Cause Selection Note1 0 CSIIF0 is set to 1 upon termination of serial interface channel 0 transfer 1 CSIIF0 is set to 1 upon stop condition detection or termination of serial interface channel 0 transfer CLD SCK0/SCL Pin Level Note 2 0 Low level 1 High level Notes 1.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) 17.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. • Operation stop mode • 3-wire serial I/O mode • 2-wire serial I/O mode • I2C (Inter IC) bus mode 17.4.1 Operation stop mode Serial transfer is not carried out in the operation stop mode. Thus, power consumption can be reduced.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) 17.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K series. Communication is carried out with three lines of serial clock (SCK0), serial output (SO0), and serial input (SI0).
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> <2> <1> <0> SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT R/W R/W After Reset FF61H 00H R/W R/W RELT When RELT = 1, SO0 Iatch is set to 1. After SO0 Iatch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0). The transmitted data is held in the SO0 latch and is output from the SO0 pin.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 17-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form. MSB/LSB switching as the start bit can be specified with bit 2 (CSIM02) of the serial operating mode register 0 (CSIM0). Figure 17-9.
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CHAPTER 17 17.4.3 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) 2-wire serial I/O mode operation The 2-wire serial I/O mode can cope with any communication format by program. Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or SB1). Figure 17-10.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> <2> <1> <0> SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT R/W R/W Address FF61H After Reset 00H R/W R/W RELT When RELT = 1, SO0 Iatch is set to 1. After SO0 Iatch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (c) Interrupt timing specify register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge of the serial clock (SCK0).
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (3) Other signals Figure 17-12 shows RELT and CMDT operations. Figure 17-12. RELT and CMDT Operations SO0 Latch RELT CMDT (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. • Serial interface channel 0 operation control bit (CSIE0) = 1 • Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer. Cautions 1.
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CHAPTER 17 17.4.4 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) I2C bus mode operation The I2C bus mode is provided for when communication operations are performed between a single master device and multiple slave devices.
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SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) CHAPTER 17 (1) I2C bus mode functions In the I2C bus mode, the following functions are available. (a) Automatic identification of serial data Slave devices automatically detect and identifies start condition, data, and stop condition signals sent in series through the serial data bus.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (a) Start condition When the SDA0 (SDA1) pin level is changed from high to low while the SCL pin is high, this transition is recognized as the start condition signal. This start condition signal, which is created using the SCL and SDA0 (or SDA1) pins, is output from the master device to slave devices to initiate a serial transfer. See section 17.4.5, "Cautions on Use of I2C Bus Mode," for details of the start condition output.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (d) Acknowledge signal (ACK) The acknowledge signal indicates that the transferred serial data has definitely been received. This signal is used between the sending side and receiving side devices for confirmation of correct data transfer. In principle, the receiving side device returns an acknowledge signal to the sending device each time it receives 8-bit data.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (f) Wait signal (WAIT) The wait signal is output by a slave device to inform the master device that the slave device is in wait state due to preparing for transmitting or receiving data. During the wait state, the slave device continues to output the wait signal by keeping the SCL pin low to delay subsequent transfers. When the wait state is released, the master device can start the next transfer.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (3) Register setting The I2C mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specify register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets 00H.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (b) Serial bus interface control register (SBIC) SBIC is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> <2> <1> <0> SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT Address After Reset FF61H 00H R/W R/WNote R/W RELT Use for stop condition output. When RELT = 1, SO0 latch is set to 1. After SO0 latch setting, automatically cleared to 0.
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CHAPTER 17 R/W R R/W ACKE SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) Acknowledge Signal Automatic Output ControlNote 1 0 Disabled (with ACKT enabled). Used when receiving data in the 8-clock wait mode or when transmitting data.Note 2 1 Enabled. After completion of transfer, acknowledge signal is output in synchronization with the 9th falling edge of SCL clock (automatically output when ACKE = 1). However, not automatically cleared to 0 after acknowledge signal output.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (c) Interrupt timing specification register (SINT) SINT is set by the 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (4) Various signals A list of signals in the I2C bus mode is given in Table 17-4. Table 17-4. Signals in I2C Bus Mode Signal name Description Start condition Definition : SDA0 (SDA1) falling edge when SCL is highNote 1 Function : Indicates that serial communication starts and subsequent data are address data. Signaled by : Master Signaled when : CMDT is set. Affected flag(s) : CMDD (is set.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (5) Pin configurations The configurations of the serial clock pin SCL and the serial data bus pins SDA0 (SDA1) are shown below. (a) SCL Pin for serial clock input/output dual-function pin. <1> Master ..... N-ch open-drain output <2> Slave ....... Schmitt input (b) SDA0 (SDA1) Serial data input/output dual-function pin. Uses N-ch open-drain output and Schmitt-input buffers for both master and slave devices.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (7) Error detection In the I2C bus mode, transmission error detection can be performed by the following methods because the serial bus SDA0 (SDA1) status during transmission is also taken into the serial I/O shift register 0 (SIO0) register of the transmitting device. (a) Comparison of SIO0 data before and after transmission In this case, a transmission error is judged to have occurred if the two data values are different.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) Figure 17-22.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) Figure 17-22.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) Figure 17-22.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) Figure 17-23.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) Figure 17-23.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) Figure 17-23.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) 17.4.5 Cautions on use of I2C bus mode (1) Start condition output (master) The SCL pin normally outputs a low-level signal when no serial clock is output. It is necessary to change the SCL pin to high in order to output a start condition signal. Set 1 in CLC of interrupt timing specify register (SINT) to drive the SCL pin high. After setting CLC, clear CLC to 0 and return the SCL pin to low. If CLC remains 1, no serial clock is output.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (2) Slave wait release (slave transmission) Slave wait status is released by WREL flag (bit 2 of interrupt timing specify register (SINT)) setting or execution of an serial I/O shift register 0 (SIO0) write instruction. If the slave sends data, the wait is immediately released by execution of an SIO0 write instruction and the clock rises without the start transmission bit being output in the data line.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (3) Slave wait release (slave reception) The slave is released from the wait status when the WREL flag (bit 2 of the interrupt timing specify register (SINT)) is set or when an instruction that writes data to the serial I/O shift register 0 (SIO0) is executed.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) (4) Reception completion of salve In the reception completion processing of the slave, check the bit 3 (CMDD) of the serial bus interface control register (SBIC) and bit 6 (COI) of the serial operation mode register 0 (CSIM0) (when CMDD = 1).
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) • Example of program releasing serial transfer status SET1 P2.5; <1> SET1 PM2.5; <2> SET1 PM2.7; <3> CLR1 CSIE0; <4> SET1 CSIE0; <5> SET1 RELT; <6> CLR1 PM2.7; <7> CLR1 P2.5; <8> CLR1 PM2.5; <9> <1> This instruction prevents the SDA0 pin from outputting a low level when the I2C bus mode is restored by instruction <5>. The output of the SDA0 pin goes into a high-impedance state.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) 17.4.7 SCK0/SCL/P27 pin output manipulation The SCK0/SCL/P27 pin can execute static output via software, in addition to outputting the normal serial clock. The value of serial clocks can also be arbitrarily set by software (the SI0/SB0/SDA0 and SO0/SB1/SDA1 pins are controlled with the RELT and CMDT bits of serial bus interface control register (SBIC)). The SCK0/SCL/P27 pin output should be manipulated as described below.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) Figure 17-29. Logic Circuit of SCL Signal CLC (manipulated by bit manipulation instruction) SCL Wait request signal Serial clock (low while transfer is stopped) Remarks 1. This figure indicates the relation of the signals and does not indicate the internal circuit. 2.
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[MEMO] 392
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.1 Serial Interface Channel 1 Functions Serial interface channel 1 employs the following three modes. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function (1) Operation stop mode This mode is used when serial transfer is not carried out to reduce power consumption.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.2 Serial Interface Channel 1 Configuration Serial interface channel 1 consists of the following hardware. Table 18-1.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-1.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (1) Serial I/O shift register 1 (SIO1) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO1 is set with an 8-bit memory manipulation instruction. When the value in bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) is 1, writing data to SIO1 starts serial operation.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.3 Serial Interface Channel 1 Control Registers The following four types of registers are used to control serial interface channel 1. • Timer clock select register 3 (TCL3) • Serial operating mode register 1 (CSIM1) • Automatic data transmit/receive control register (ADTC) • Automatic data transmit/receive interval specify register (ADTI) (1) Timer clock select register 3 (TCL3) This register sets the serial clock of serial interface channel 1.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-2. Timer Clock Select Register 3 Format Symbol 7 6 5 4 3 2 1 0 TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 Address FF43H After Reset 88H R/W R/W Serial Interface Channel 1 Serial Clock Selection TCL37 TCL36 TCL35 TCL34 MCS = 1 MCS = 0 0 1 1 0 fXX/2 Setting prohibited fX/22 (1.25 MHz) 0 1 1 1 fXX/22 fX/22 (1.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Serial operating mode register 1 (CSIM1) This register sets serial interface channel 1 serial clock, operating mode, operation enable/stop and automatic transmit/receive operation enable/stop. CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM1 to 00H. Figure 18-3.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (3) Automatic data transmit/receive control register (ADTC) This register sets automatic transmit/receive enable/disable, the operating mode, strobe output enable/ disable, busy input enable/disable, error check enable/disable and displays automatic transmit/receive execution and error detection. ADTC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTC to 00H. Figure 18-4.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (4) Automatic data transmit/receive interval specify register (ADTI) This register sets the automatic data transmit/receive function data transfer interval. ADTI is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H. Figure 18-5.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (2/4) Symbol 7 ADTI ADTI7 6 5 0 0 4 3 2 1 0 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Address After Reset FF6BH 00H R/W R/W Data Transfer Interval Specification (fXX = 5.0 MHz Operation) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 MinimumNote MaximumNote 1 0 0 0 0 223.2 µ s + 0.5/fSCK 224.8 µ s + 1.5/fSCK 1 0 0 0 1 236.0 µ s + 0.5/fSCK 237.6 µ s + 1.5/fSCK 1 0 0 1 0 248.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (3/4) Symbol 7 ADTI ADTI7 ADTI7 6 5 0 0 4 3 2 1 0 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Address FF6BH After Reset 00H R/W R/W Data Transfer Interval Control 0 No control of interval by ADTINote 1 1 Control of interval by ADTI (ADTI0 to ADTI4) Data Transfer Interval Specification (fXX = 2.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (4/4) Symbol 7 ADTI ADTI7 6 5 0 0 4 3 2 1 0 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Address After Reset FF6BH 00H R/W R/W Data Transfer Interval Specification (fXX = 2.5 MHz Operation) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 MinimumNote MaximumNote 1 0 0 0 0 446.4 µ s + 0.5/fSCK 449.6 µ s + 1.5/fSCK 1 0 0 0 1 472.0 µ s + 0.5/fSCK 475.2 µ s + 1.5/fSCK 1 0 0 1 0 497.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.4 Serial Interface Channel 1 Operations The following three operating modes are available to the serial interface channel 1. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function 18.4.1 Operation stop mode Serial transfer is not carried out in the operation stop mode. Thus, power consumption can be reduced.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous serial interface such as the 75X/XL, 78K and 17K series. Communication is carried out with three lines of serial clock (SCK1), serial output (SO1) and serial input (SI1). (1) Register setting The 3-wire serial I/O mode is set with the serial operating mode register 1 (CSIM1).
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 1 (SIO1) is carried out at the falling edge of the serial clock SCK1. The transmit data is held in the SO1 latch and is output from the SO1 pin.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (3) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 18-7 shows the configuration of the serial I/O shift register 1 (SIO1) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form. MSB/LSB switching as the start bit can be specified with bit 6 (DIR) of the serial operating mode register 1 (CSIM1). Figure 18-7.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.4.3 3-wire serial I/O mode operation with automatic transmit/receive function This 3-wire serial I/O mode is used for transmission/reception of a maximum of 32-byte data without the use of software. Once transfer is started, the data prestored in the RAM can be transmitted by the set number of bytes, and data can be received and stored in the RAM by the set number of bytes.
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CHAPTER 18 Symbol <7> 6 CSIM1 CSIE1 DIR <5> 4 3 2 ATE 0 0 0 SERIAL INTERFACE CHANNEL 1 1 0 CSIM11 CSIM10 Address After Reset FF68H 00H R/W Serial Interface Channel 1 Clock Selection CSIM11 CSIM10 0 × Clock externally input to SCK1 pinNote 1 1 0 8-bit timer register 2 (TM2) output 1 1 Clock specified with bits 4 to 7 of timer clock select register 3 (TCL3) ATE R/W Serial Interface Channel 1 Operating Mode Selection 0 3-wire serial I/O mode 1 3-wire serial I/O mode with
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (b) Automatic data transmit/receive control register (ADTC) ADTC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTC to 00H.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Automatic data transmit/receive interval specify register (ADTI) This register sets the automatic data transmit/receive function data transfer interval. ADTI is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H.
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CHAPTER 18 Symbol 7 ADTI ADTI7 6 5 0 0 4 3 2 SERIAL INTERFACE CHANNEL 1 1 0 Address ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 After Reset FF6BH 00H R/W R/W Data Transfer Interval Specification (fXX = 5.0 MHz Operation) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 MinimumNote MaximumNote 1 0 0 0 0 223.2 µ s + 0.5/fSCK 224.8 µ s + 1.5/fSCK 1 0 0 0 1 236.0 µ s + 0.5/fSCK 237.6 µ s + 1.5/fSCK 1 0 0 1 0 248.8 µ s + 0.5/fSCK 250.4 µ s + 1.5/fSCK 1 0 0 1 1 261.6 µ s + 0.5/fSCK 263.2 µ s + 1.
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CHAPTER 18 Symbol 7 ADTI ADTI7 ADTI7 6 5 0 0 4 3 2 SERIAL INTERFACE CHANNEL 1 1 0 Address ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 FF6BH After Reset 00H R/W R/W Data Transfer Interval Control 0 No control of interval by ADTINote 1 1 Control of interval by ADTI (ADTI0 to ADTI4) Data Transfer Interval Specification (fXX = 2.5 MHz Operation) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 MinimumNote 2 MaximumNote 2 0 0 0 0 0 36.8 µ s + 0.5/fSCK 40.0 µ s + 1.5/fSCK 0 0 0 0 1 62.4 µ s + 0.5/fSCK 65.
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CHAPTER 18 Symbol 7 ADTI ADTI7 6 5 0 0 4 3 2 SERIAL INTERFACE CHANNEL 1 1 0 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Address After Reset FF6BH 00H R/W R/W Data Transfer Interval Specification (fXX = 2.5 MHz Operation) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 MinimumNote MaximumNote 1 0 0 0 0 446.4 µ s + 0.5/fSCK 449.6 µ s + 1.5/fSCK 1 0 0 0 1 472.0 µ s + 0.5/fSCK 475.2 µ s + 1.5/fSCK 1 0 0 1 0 497.6 µ s + 0.5/fSCK 500.8 µ s + 1.5/fSCK 1 0 0 1 1 523.2 µ s + 0.5/fSCK 526.4 µ s + 1.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Automatic transmit/receive data setting (a) Transmit data setting <1> Write transmit data from the least significant address FAC0H of buffer RAM (up to FADFH at maximum). The transmit data should be in the order from high-order address to low-order address. <2> Set to the automatic data transmit/receive address pointer (ADTP) the value obtained by subtracting 1 from the number of transmit data bytes.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (3) Communication operation (a) Basic transmission/reception mode This transmission/reception mode is the same as the 3-wire serial I/O mode in which specified number of data are transmitted/received in 8-bit units. Serial transfer is started when any data is written to the serial I/O shift register 1 (SIO1) while bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1) is set to 1.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-9.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission/reception (ARLD=0, RE=1) in basic transmit/receive mode, buffer RAM operates as follows. (i) Before transmission/reception (Refer to Figure 18-10 (a)) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-10.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (b) Basic transmission mode In this mode, the specified number of 8-bit unit data are transmitted. Serial transfer is started when any data is written to the serial I/O shift register 1 (SIO1) while bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1) is set to 1. The interrupt request flag (CSIIF1) is set upon completion of transmission of the last byte.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-12.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission (ARLD=0, RE=0) in basic transmit mode, buffer RAM operates as follows. (i) Before transmission (Refer to Figure 18-13 (a)) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1. When transmission of the first byte is completed, automatic data transmit/receive address pointer (ADTP) is decremented.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-13.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Repeat transmission mode In this mode, data stored in the buffer RAM is transmitted repeatedly. Serial transfer is started by writing any data to serial I/O shift register 1 (SIO1) when 1 is set in bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1).
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-15.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission (ARLD=1, RE=0) in repeat transmit mode, buffer RAM operates as follows. (i) Before transmission (Refer to Figure 18-16 (a)) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1. When transmission of the first byte is completed, automatic data transmit/receive address pointer (ADTP) is decremented.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-16.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (d) Automatic transmission/reception suspending and restart Automatic transmission/reception can be temporarily suspended by setting bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1) to 0. If during 8-bit data transfer, the transmission/reception is not suspended if bit 7 (CSIE1) is set to 0. It is suspended upon completion of 8-bit data transfer.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (4) Synchronization Control Busy control and strobe control are functions for synchronizing sending and receiving between the master device and slave device. By using these functions, it is possible to detect bit slippage during sending and receiving.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Furthermore, in the case that the busy control option is used, select the internal clock for the serial clock. The busy signal cannot be controlled with an external clock. The operation timing when the busy control option is used is shown in Figure 18-19. Caution Busy control cannot be used at the same time as interval timing control using the auto data send and receive interval instruction register (ADTI).
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-20. Busy Signal and Wait Cancel (when BUSY0 = 0) SCK1 SO1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SI1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY (Active High) 1.5 clocks (min.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-21. Operation Timings when Using Busy & Strobe Control Option (BUSY0 = 0) SCK1 SO1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SI1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 STB BUSY CSIIF1 Busy Input Clear Busy Input Valid TRF Caution When TRF is cleared, the SO1 pin becomes low level.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Bit Slippage Detection Function Through the Busy Signal During an auto send and receive operation, noise occur in the serial clock signal output by the master device and bit slippage may occur in the slave device side serial clock. At this time, if the strobe control option is not used, this bit slippage will have an effect on sending of the next byte.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (5) Automatic transmit/receive interval time When using the automatic transmit/receive function, the read/write operations from/to the buffer RAM are performed after transmitting/receiving one byte. Therefore, an interval is inserted before the next transmit/ receive.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (a) When the automatic transmit/receive function is used by the internal clock If bit 1 (CSIM11) of serial operation mode register 1 (CSIM1) is set at (1), the internal clock operates. If the auto send and receive function is operated by the internal clock, interval timing by CPU processing is as follows. When bit 7 (ADTI7) of automatic data transmit/receive interval specify register (ADTI) is set to 0, the interval depends on the CPU processing.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (b) When the automatic transmit/receive function is used by the external clock If bit 1 (CSIM11) of serial operation mode register 1 (CSIM1) is cleared to 0, external clock operation is set. When the automatic transmit/receive function is used by the external clock, it must be selected so that the interval may be longer than the values shown as follows. Table 18-3.
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[MEMO] 438
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.1 Serial Interface Channel 2 Functions Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not carried out to reduce power consumption. (2) Asynchronous serial interface (UART) mode In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.2 Serial Interface Channel 2 Configuration Serial interface channel 2 consists of the following hardware. Table 19-1.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-1.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-2.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (1) Transmit shift register (TXS) This register is used to set the transmit data. The data written in TXS is transmitted as serial data. If the data length is specified as 7 bits, bits 0 to 6 of the data written in TXS are transferred as transmit data. Writing data to TXS starts the transmit operation. TXS is written to with an 8-bit memory manipulation instruction. It cannot be read. TXS value is FFH after RESET input.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.3 Serial Interface Channel 2 Control Registers Serial interface channel 2 is controlled by the following four registers. • Serial Operating Mode Register 2 (CSIM2) • Asynchronous Serial Interface Mode Register (ASIM) • Asynchronous Serial Interface Status Register (ASIS) • Baud Rate Generator Control Register (BRGC) (1) Serial operating mode register 2 (CSIM2) This register is set when serial interface channel 2 is used in the 3-wire serial I/O mode.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (2) Asynchronous serial interface mode register (ASIM) This register is set when serial interface channel 2 is used in the asynchronous serial interface mode. ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H. Figure 19-4.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Table 19-2.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (3) Asynchronous serial interface status register (ASIS) This is a register which displays the type of error when a reception error is generated in the asynchronous serial interface mode. ASIS is read with a 8-bit memory manipulation instruction. In 3-wire serial I/O mode, the contents of the ASIS are undefined. RESET input sets ASIS to 00H. Figure 19-5.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (4) Baud rate generator control register (BRGC) This register sets the serial clock for serial interface channel 2. BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H. Figure 19-6.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-6. Baud Rate Generator Control Register Format (2/2) 5-Bit Counter Source Clock Selection TPS3 TPS2 TPS1 TPS0 n MCS = 1 MCS = 0 0 0 0 0 fXX/210 fXX/210 (4.9 kHz) fX/211 (2.4 kHz) 11 0 1 0 1 fXX fX (5.0 MHz) fX/2 (2.5 MHz) 1 0 1 1 0 fXX/2 fX/2 (2.5 MHz) fX/22 (1.25 MHz) 2 fX/22 (1.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (a) Generation of baud rate transmit/receive clock by means of main system clock The transmit/receive clocks generated by scaling the main system clock. The baud rate generated from the main system clock is found from the following expression.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression. fASCK [Baud rate] = 2 × (k+16) [Hz] fASCK : Frequency of clock input to ASCK pin k : Value set in MDL0 to MDL3 (0 ≤ k ≤ 14) Table 19-4.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4 Serial Interface Channel 2 Operation Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode 19.4.1 Operation stop mode In the operation stop mode, serial transfer is not performed, and therefore power consumption can be reduced. In the operation stop mode, the P70/SI2/RxD, P71/SO2/TxD and P72/SCK2/ASCK pins can be used as normal input/output ports.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4.2 Asynchronous serial interface (UART) mode In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible. A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud rates. In addition, the baud rate can be defined also by scaling the input clock to the ASCK pin. The MIDI standard baud rate (31.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (c) Asynchronous serial interface status register (ASIS) ASIS is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIS to 00H.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (d) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 5-Bit Counter Source Clock Selection TPS3 TPS2 TPS1 TPS0 n MCS = 1 MCS = 0 0 0 0 0 fXX/210 fX/210 (4.9 kHz) fX/211 (2.4 kHz) 11 0 1 0 1 fXX fX (5.0 MHz) fX/2 (2.5 MHz) 1 0 1 1 0 fXX/2 fX/2 (2.5 MHz) fX/22 (1.25 MHz) 2 0 1 1 1 fXX/22 fX/22 (1.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (i) Generation of baud rate transmit/receive clock by means of main system clock The transmit/receive clock is generated by scaling the main system clock. The baud rate generated from the main system clock is obtained with the following expression.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression. fASCK 2 × (k+16) [Baud rate] = where, [Hz] fASCK : Frequency of clock input to ASCK pin k Value set in MDL0 to MDL3 (0 ≤ k ≤ 14) : Table 19-6.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (2) Communication operation (a) Data format The transmit/receive data format is as shown in Figure 19-7. Figure 19-7. Asynchronous Serial Interface Transmit/Receive Data Format One Data Frame Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit Character Bits One data frame consists of the following bits. • Start bits .................. 1 bit • Character bits ......... 7 bits/8 bits • Parity bits ................
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) error can be detected. With 0 parity and no parity, an error cannot be detected.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (c) Transmission A transmit operation is started by writing transmit data to the transmit shift register (TXS). The start bit, parity bit and stop bit(s) are added automatically. When the transmit operation starts, the data in the transmit shift register (TXS) is shifted out, and when the transmit shift register (TXS) is empty, a transmission completion interrupt request (INTST) is generated. Figure 19-8.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (d) Reception When the bit 6 (RXE) of the asynchronous serial interface mode register (ASIM) is set (1), a receive operation is enabled and sampling of the RxD pin input is performed. RxD pin input sampling is performed using the serial clock specified by ASIM.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (e) Receive errors Three kinds of errors can occur during a receive operation: a parity error, framing error, or overrun error. When the data reception result error flag is set in the asynchronous serial interface status register (ASIS), a receive error interrupt request (INTSER) is generated. INTSER is generated before receive completion interrupt request (INTSR). Receive error causes are shown in Table 19-7.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (3) UART mode cautions (a) When bit 7 (TXE) of the asynchronous serial interface mode register (ASIM) is cleared and the transmission operation is stopped during transmission, be sure to set the transmit shift register (TXS) to FFH, then set the TXE to 1 before executing the next transmission.
PAGE 467
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional synchronous clocked serial interface, such as the 75X/XL series, 78K series, 17K series, etc. Communication is performed using three lines: the serial clock (SCK2), serial output (SO2), and serial input (SI2).
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H. When the 3-wire serial I/O mode is selected, 00H should be set in ASIM.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (c) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 5-Bit Counter Source Clock Selection TPS3 TPS2 TPS1 TPS0 n MCS = 1 MCS = 0 0 0 0 0 fXX/210 fX/210 (4.9 kHz) fX/211 (2.4 kHz) 11 0 1 0 1 fXX fX (5.0 MHz) fX/2 (2.5 MHz) 1 0 1 1 0 fXX/2 fX/2 (2.5 MHz) fX/22 (1.25 MHz) 2 fX/22 (1.25 MHz) fX/23 (625 kHz) 3 (625 kHz) fX/24 (313 kHz) 4 (156 kHz) 5 0 1 1 1 fXX/22 1 0 0 0 fXX/23 fX/23 fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) 6 (39.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 When the 3-wire serial I/O mode is used, set BRGC as described below. (i) When the baud rate generator is not used: Select a serial clock frequency with TPS0 to TPS3. Be sure then to set MDL0 to MDL3 to 1,1,1,1. The serial clock frequency becomes 1/2 of the source clock frequency for the 5-bit counter. (ii) When the baud rate generator is used: Select a serial clock frequency with TPS0 to TPS3. Be sure then to set MDL0 to MDL3 to 1,1,1,1.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/ received bit by bit in synchronization with the serial clock. Transmit shift register (TXS/SIO2) and receive shift register (RXS) shift operations are performed in synchronization with the fall of the serial clock SCK2. Then transmit data is held in the SO2 latch and output from the SO2 pin.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (3) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 19-13 shows the configuration of the transmit shift register (TXS/SIO2) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form. MSB/LSB switching as the start bit can be specified with bit 2 (CSIM22) of the serial operating mode register 2 (CSIM2). Figure 19-13.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4.4 Limitations when UART mode is used In the UART mode, the reception completion interrupt request (INTSR) occurs a certain time after the reception error interrupt request (INTSER) has occurred and then cleared. Consequently, the following phenomenon may occur. • Description If bit 1 (ISRM) of the asynchronous serial interface mode register (ASIM) is set to 1, the reception completion interrupt request (INTSR) does not occur on occurrence of a reception error.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 • In case of parity error Disable the receive buffer register (RXB) from being read for a certain time (T1 + T2 in Figure 19-15) after the reception error interrupt request (INTSER) has occurred. Figure 19-15.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 [Example] UART reception error interrupt (INTSER) servicing Main processing EI Occurrence of INTSER 7 clocks of CPU clock (MIN.) (time from interrupt request to servicing) Instructions equivalent to 2205 CPU clocks (MIN.) are necessary.
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CHAPTER 20 REAL-TIME OUTPUT PORT 20.1 Real-Time Output Port Functions Data set previously in the real-time output buffer register can be transferred to the output latch by hardware concurrently with timer interrupt requests or external interrupt request generation, then output externally. This is called the real-time output function. The pins that output data externally are called real-time output ports. By using a real-time output, a signal which has no jitter can be output.
PAGE 478
CHAPTER 20 REAL-TIME OUTPUT PORT 20.2 Real-Time Output Port Configuration The real-time output port consists of the following hardware. Table 20-1. Real-time Output Port Configuration Item Configuration Register Real-time output buffer register (RTBL, RTBH) Control register Port mode register 12 (PM12) Real-time output port mode register (RTPM) Real-time output port control register (RTPC) Figure 20-1.
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CHAPTER 20 REAL-TIME OUTPUT PORT (1) Real-time output buffer register (RTBL, RTBH) Addresses of RTBL and RTBH are mapped individually in the Special function register (SFR) area as shown in Figure 20-2. When specifying 4 bits × 2 channels as the operating mode, data are set individually in RTBL and RTBH. When specifying 8 bits × 1 channel as the operating mode, data are set to both RTBL and RTBH by writing 8-bit data to either RTBL or RTBH. Table 20-2 shows operations during manipulation of RTBL and RTBH.
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CHAPTER 20 REAL-TIME OUTPUT PORT 20.3 Real-Time Output Port Control Registers The following three registers control the real-time output port. • Port mode register 12 (PM12) • Real-time output port mode register (RTPM) • Real-time output port control register (RTPC) (1) Port mode register 12 (PM12) This register sets the input or output mode of port 12 pins (P120 through P127) which are multiplexed with real-time output pins (RTP0 through RTP7).
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CHAPTER 20 REAL-TIME OUTPUT PORT (3) Real-time output port control register (RTPC) This register sets the real-time output port operating mode and output trigger. Table 20-3 shows the relation between the operating mode of the real-time output port and output trigger. RTPC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 20-5.
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CHAPTER 20 [MEMO] 482 REAL-TIME OUTPUT PORT
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in the interrupt disabled status. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. It generates a standby release signal. Non-maskable interrupt includes one interrupt request source from watchdog timer.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.2 Interrupt Sources and Configuration Interrupt sources includes total of 22 non-maskbale, maskable, software interrupts (refer to Table 21-1). Table 21-1.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Table 21-1.
PAGE 486
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-1.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-1.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input. IF0L, IF0H, and IF1L are set with a 1-bit or 8-bit memory manipulation instruction.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to set standby clear enable/disable. MK0L, MK0H, and MK1L are set with a 1-bit or 8-bit memory manipulation instruction. If MK0L and MK0H are used as a 16-bit register MK0, use a 16-bit memory manipulation instruction for the setting. RESET input sets these registers to FFH. Figure 21-3.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (3) Priority specify flag registers (PR0L, PR0H, and PR1L) The priority specify flag is used to set the corresponding maskable interrupt priority orders. PR0L, PR0H, and PR1L are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are used as a 16-bit register PR0, use a 16-bit memory manipulation instruction for the setting. RESET input sets these registers to FFH. Figure 21-4.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (4) External interrupt mode register (INTM0, INTM1) These registers set the valid edge for INTP0 to INTP6. INTM0 and INTM1 are set by 8-bit memory manipulation instructions. RESET input sets these registers to 00H. Figure 21-5.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-6.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (5) Sampling clock select register (SCS) This register is used to set the valid edge clock sampling clock to be input to INTP0. When remote controlled data reception is carried out using INTP0, digital noise is removed with sampling clocks. SCS is set with an 8-bit memory manipulation instruction. RESET input sets SCS to 00H. Figure 21-7.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS When the sampled INTP0 input level is active twice in succession, the noise eliminator sets interrupt request flag (PIF0) to 1. Figure 21-8 shows the noise eliminator input/output timing. Figure 21-8. Noise Eliminator Input/Output Timing (during rising edge detection) (a) When input is less than the sampling cycle (tSMP) tSMP Sampling Clock INTP0 "L" PIF0 Because INTP0 level is not high level at the time of sampling, PIF0 flag remains at low level.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (6) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt processing are mapped. Besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction and dedicated instructions (EI and DI).
PAGE 497
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4 Interrupt Servicing Operations 21.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state. It does not undergo interrupt priority control and has highest priority over all other interrupt requests.
PAGE 498
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-10.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-12. Non-Maskable Interrupt Request Acknowledge Operation (a) If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution Main Routine NMI Request <1> NMI Request <2> 1 Instruction Execution NMI Request <1> is executed. NMI Request <2> is reserved. Reserved NMI Request <2> is processed.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enable state (with IE flag set to 1). However, a low-priority interrupt request is not acknowledged during high-priority interrupt service (with ISP flag reset to 0).
PAGE 501
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-13.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-14. Interrupt Request Acknowledge Timing (Minimum Time) 6 Clocks CPU Processing Instruction Instruction PSW and PC Save, Jump to Interrupt Servicing Interrupt Servicing Program × × IF (× × PR=1) 8 Clocks × × IF (× × PR=0) 7 Clocks Remark 1 clock : 1 (fCPU: CPU clock) fCPU Figure 21-15.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.3 Software interrupt request acknowledge operation A software interrupt request is acknowledged by BRK instruction execution. Software interrupt cannot be disabled. If a software interrupt request is acknowledged, the contents is saved in the stacks, program status word (PSW) and program counter (PC), in that order, the IE flag is reset to 0 and the contents of the vector tables (003EH and 003FH) are loaded into PC and branched.
PAGE 504
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-16. Multiple Interrupt Example (1/2) Example 1. A multiple interrupt is generated at twice INTxx Servicing Main Processing INTyy Servicing IE=0 IE=0 EI EI INTxx (PR=1) INTzz Servicing IE=0 EI INTyy (PR=0) INTzz (PR=0) RETI RETI RETI While servicing interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and a multiple interrupt is generated.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-16. Multiple Interrupt Example (2/2) Example 3. A multiple interrupt is not generated because interrupt is disabled Main Processing EI INTxx Servicing INTyy Servicing IE=0 INTxx (PR=0) 1 Instruction Execution INTyy (PR=0) RETI IE=0 RETI Because interrupts are disabled during interrupt INTxx servicing (EI instruction is not issued), interrupt request INTyy is not acknowledged, and a multiple interrupt is not generated.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.5 Interrupt request reserve In some cases, the acknowledgment of the interrupt request is reserved even an interrupt request is generated during processing of the instruction until the execution of the next instruction is completed. The following shows this type of instructions (interrupt request reserve instruction). • MOV PSW, #byte • MOV A, PSW • MOV PSW, A • MOV1 PSW.bit, CY • MOV1 CY, PSW.bit • AND1 CY, PSW.bit • OR1 CY, PSW.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.5 Test Functions Upon occurrence of watch timer overflow and the detection of the falling falling edge of port 4, the corresponding test input flag is set (1) and a standby release signal is generated. Unlike in the case of interrupt functions, vector processing is not performed. There are two test input sources as shown in Table 21-5. The basic configuration is shown in Figure 21-18. Table 21-5.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (1) Interrupt request flag register 1L (IF1L) It indicates whether a watch timer overflow is detected or not. It is set by a 1-bit memory manipulation instruction and 8-bit memory manipulation instruction. It is set to 00H by the RESET signal input. Figure 21-19.
PAGE 509
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (3) Key return mode register (KRM) This register is used to set enable/disable of standby function clear by key return signal (port 4 falling edge detection). KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM to 02H. Figure 21-21.
PAGE 510
[MEMO] 510
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CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.1 External Device Expansion Functions The external device expansion functions connect external devices to areas other than the internal ROM, RAM, and SFR. Connection of external devices uses ports 4 to 6. Ports 4 to 6 control address/data, read/write strobe, wait, address strobe etc. Table 22-1.
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CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Memory maps when using the external device expansion function are as follows. Figure 22-1.
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CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-1.
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CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-1.
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CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-1.
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CHAPTER 22 22.2 EXTERNAL DEVICE EXPANSION FUNCTION External Device Expansion Function Control Register The external device expansion function is controlled by the memory expansion mode register (MM) and memory size switching register (IMS). (1) Memory expansion mode register (MM) MM sets the wait count and external expansion area, and also sets the input/output of port 4. MM is set with an 1-bit memory or 8-bit memory manipulation instruction. RESET input sets this register to 10H. Figure 22-2.
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CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION (2) Memory size switching register (IMS) This register specifies the internal memory size. In principle, use IMS in a default status. However, when using the external device expansion function with the µPD78058, set IMS so that the internal ROM capacity is 56 Kbytes or lower. IMS is set with an 8-bit memory manipulation instruction. RESET input sets this register to the value indicated in Table 22-3. Figure 22-3.
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CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.3 External Device Expansion Function Timing Timing control signal output pins in the external memory expansion mode are as follows. (1) RD pin (Alternate function: P64) Read strobe signal output pin. The read strobe signal is output in data accesses and instruction fetches from external memory. During internal memory access, the read strobe signal is not output (maintains high level). (2) WR pin (Alternate function: P65) Write strobe signal output pin.
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CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-4.
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CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-5.
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CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-6.
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CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-7.
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CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.4 Example of Connection with Memory This section provides µPD78054 and external memory connection examples in Figure 22-8. SRAMs are used as the external memory in these diagrams. In addition, the external device expansion function is used in the full-address mode, and the address from 0000H to 7FFFH (32 Kbytes) are allocated for internal ROM, and the addresses after 8000H for SRAM. Figure 22-8.
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[MEMO] 524
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CHAPTER 23 STANDBY FUNCTION 23.1 Standby Function and Configuration 23.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. System clock oscillator continues oscillation. In this mode, current consumption cannot be decreased as in the STOP mode.
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CHAPTER 23 STANDBY FUNCTION 23.1.2 Standby function control register A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H. However, it takes 217/fX, not 218/fX, until the STOP mode is cleared by RESET input. Figure 23-1.
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CHAPTER 23 STANDBY FUNCTION 23.2 Standby Function Operations 23.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the subsystem clock. The operating status in the HALT mode is described below. Table 23-1.
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CHAPTER 23 STANDBY FUNCTION (2) HALT mode clear The HALT mode can be cleared with the following four types of sources. (a) Clear upon unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is cleared. If interrupt request acknowledge is enabled, vectored interrupt service is carried out. If disabled, the next address instruction is executed. Figure 23-2.
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CHAPTER 23 STANDBY FUNCTION (d) Clear upon RESET input When a RESET signal is input, the HALT mode is released, and as is the case with normal reset operation, a program is executed after branch to the reset vector address. Figure 23-3. HALT Mode Release by RESET Input Wait (217/f x : 26.2 ms) HALT Instruction RESET Signal Operating Mode HALT Mode Oscillation Clock Reset Period Oscillation stop Oscillation Stabilization Wait Status Operating Mode Oscillation Remarks 1.
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CHAPTER 23 STANDBY FUNCTION 23.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock. Cautions 1. When the STOP mode is set, the X2 pin is internally connected to VDD via a pull-up resistor to minimize the leakage current at the crystal oscillator. Thus, do not use the STOP mode in a system where an external clock is used for the main system clock. 2.
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CHAPTER 23 STANDBY FUNCTION (2) STOP mode release The STOP mode can be cleared with the following three types of sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is cleared. If interrupt request acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out. If interrupt request acknowledge is disabled, the next address instruction is executed. Figure 23-4.
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CHAPTER 23 STANDBY FUNCTION (c) Release by RESET input When a RESET signal is input, the STOP mode is released. And after the lapse of oscillation stabilization time, reset operation is carried out. Figure 23-5. Release by STOP Mode RESET Input Wait 17 (2 /f x : 26.2 ms) STOP Instruction RESET Signal Operating Mode Reset Period STOP Mode Oscillation Oscillation Stabilization Wait Status Oscillation Stop Operating Mode Oscillation Clock Remarks 1. fX: main system clock oscillation frequency 2.
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CHAPTER 24 RESET FUNCTION 24.1 Reset Function The following two operations are available to generate the reset signal. (1) External reset input with RESET pin (2) Internal reset by watchdog timer overrun time detection External reset and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input.
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CHAPTER 24 RESET FUNCTION Figure 24-2. Timing of Reset Input by RESET Input X1 Oscillation Stabilization Time Wait Reset Period (Oscillation Stop) Normal Operation Normal Operation (Reset Processing) RESET Internal Reset Signal Delay Delay Hi-Z Port Pin Figure 24-3.
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CHAPTER 24 RESET FUNCTION Table 24-1. Hardware Status after Reset (1/2) Hardware Program counter (PC) Note1 Status after Reset The contents of reset vector tables (0000H and 0001H) are set.
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CHAPTER 24 RESET FUNCTION Table 24-1.
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CHAPTER 25 ROM CORRECTION 25.1 ROM Correction Functions The µPD78058, 78058Y subseries can replace part of a program in the mask ROM with a program in the internal expansion RAM. Instruction bugs found in the mask ROM can be avoided, and program flow can be changed by using the ROM correction. The ROM correction can correct two places (max.) of the internal ROM (program). Caution The ROM correction cannot be emulated by the in-circuit emulator (IE-78000-R, IE-78000-R-A, IE-78K0-NS, IE-78001-R-A). 25.
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CHAPTER 25 ROM CORRECTION (1) Correction address registers 0 and 1 (CORAD0, CORAD1) These registers set the start address (correction address) of the instruction(s) to be corrected in the mask ROM. The ROM correction corrects two places (max.) of the program. Addresses are set to two registers, CORAD0 and CORAD1. If only one place needs to be corrected, set the address to either of the registers. CORAD0 and CORAD1 are set with a 16-bit memory manipulation instruction.
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CHAPTER 25 ROM CORRECTION 25.3 ROM Correction Control Registers The ROM correction is controlled with the correction control register (CORCN). (1) Correction control register (CORCN) This register controls whether or not the correction branch request signal is generated when the fetch address matches the correction address set in correction address registers 0 and 1. The correction control register consists of correction enable flags (COREN0, COREN1) and correction status flags (CORST0, CORST1).
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CHAPTER 25 ROM CORRECTION 25.4 ROM Correction Application (1) Store the correction address and instruction after correction (patch program) to nonvolatile memory (such as EEPROMTM) outside the microcontroller. When two places should be corrected, store the branch destination judgment program as well. The branch destination judgment program checks which one of the addresses set to CORAD0 or CORAD1 generates the correction branch. Figure 25-4.
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CHAPTER 25 ROM CORRECTION (2) Assemble in advance the initialization routine as shown in Figure 25-6 to correct the program. Figure 25-6. Initialization Routine Initialization ROM correction Is ROM correction used ? Note No Yes Load the contents of external nonvolatile memory into internal expansion RAM Correction address register setting ROM correction enabled Main program Note Whether the ROM correction is used or not should be judged by the port input level.
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CHAPTER 25 ROM CORRECTION Figure 25-7.
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CHAPTER 25 ROM CORRECTION 25.5 ROM Correction Example The example of ROM correction when the instruction at address 1000H “ADD A, #1” is changed to “ADD A, #2” is as follows. Figure 25-8.
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CHAPTER 25 ROM CORRECTION 25.6 Program Execution Flow Figures 25-9 and 25-10 show the program transition diagrams when the ROM correction is used. Figure 25-9.
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CHAPTER 25 ROM CORRECTION Figure 25-10.
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CHAPTER 25 ROM CORRECTION 25.7 Cautions on ROM Correction (1) Address values set in correction address registers 0 and 1 (CORAD0, CORAD1) must be addresses where instruction codes are stored. (2) Correction address registers 0 and 1 (CORAD0, CORAD1) should be set when the correction enable flag (COREN0, COREN1) is 0 (when the correction branch is in disabled state).
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CHAPTER 26 µPD78P054, 78P058 The µPD78054, 78054Y subseries include the µPD78P054, 78P058, 78P058Y as PROM versions. For purposes of simplification, in this chapter, the description of the µPD78P058 applies to both the µPD78P058 and 78P058Y. Similarly, the µPD78052, 78053, 78054, 78055, 78056, and 78058 are treated as the representative models of the mask ROM products. The µPD78P054, 78P058 replace the internal mask ROM of the µPD78054, 78058 with one-time PROM or EPROM.
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CHAPTER 26 µPD78P054, 78P058 Notes 1. The internal ROM and internal high-speed RAM capacities are set as follows by RESET input: Internal PROM: 32K bytes (µPD78P054), 60K bytes (µPD78P058) Internal high-speed RAM: 1024 bytes 2. The internal expansion RAM is set to 1024 bytes by RESET input. Caution The noise immunity and noise radiation differ between PROM versions and mask ROM versions.
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CHAPTER 26 µPD78P054, 78P058 26.1 Memory Size Switching Register (µPD78P054) The µPD78P054 allows users to define its internal ROM and high-speed RAM sizes using the memory size switching register (IMS), so that the same memory mapping as that of a mask ROM version with a different-size internal ROM and high-speed RAM is possible. IMS is set with an 8-bit memory manipulation instruction. RESET input sets IMS to C8H. Figure 26-1.
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CHAPTER 26 µPD78P054, 78P058 26.2 Memory Size Switching Register (µPD78P058) The µPD78P058 allows users to define its internal ROM and high-speed RAM sizes using the memory size switching register (IMS), so that the same memory mapping as that of a mask ROM version with a different-size internal ROM and high-speed RAM is possible. IMS is set with an 8-bit memory manipulation instruction. RESET input sets IMS to CFH. Figure 26-2.
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CHAPTER 26 µPD78P054, 78P058 26.3 Internal Expansion RAM Size Switching Register The µPD78P058 allows users to define its internal expansion RAM size using the internal expansion RAM size switching register (IXS), so that the same memory mapping as that of a mask ROM version with a different-size internal expansion RAM is possible. The IXS is set by an 8-bit memory manipulation instruction. RESET signal input sets IXS to 0AH. Figure 26-3.
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CHAPTER 26 µPD78P054, 78P058 26.4 PROM Programming The µ PD78P054 and 78P058 incorporate a 32-Kbyte and 60-Kbyte PROM as program memory, respectively. To write a program into the µ PD78P054 or 78P058 PROM, make the device enter the PROM programming mode by setting the levels of the VPP and RESET pins as specified. For the connection of unused pins, see paragraph (2) “PROM programming mode” in section 1.5 or 2.5 Pin Configuration (Top View).
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CHAPTER 26 µPD78P054, 78P058 (3) Standby mode Setting CE to H sets the standby mode. In this mode, data output becomes high impedance irrespective of the status of OE. (4) Page data latch mode Setting CE to H, PGM to H, and OE to L at the start of the page write mode sets the page data latch mode. In this mode, 1-page 4-byte data is latched in the internal address/data latch circuit.
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CHAPTER 26 µPD78P054, 78P058 26.4.2 PROM write procedure Figure 26-4. Page Program Mode Flowchart Start Address = G VDD = 6.5 V, VPP = 12.5 V Remark: G = Start address X=0 N = Last address of program Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Address = Address + 1 Latch X=X+1 No X = 10? 0.1-ms program pulse Yes Fail Verify 4 Bytes Pass No Address = N? Yes VDD = 4.5 to 5.
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CHAPTER 26 µPD78P054, 78P058 Figure 26-5. Page Program Mode Timing Page Data Latch Page Program Program Verify A2-A16 A0, A1 Hi-Z D0-D7 Data Input Data Output VPP VPP VDD VDD+1.
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CHAPTER 26 µPD78P054, 78P058 Figure 26-6. Byte Program Mode Flowchart Start Remark: Address = G G = Start address N = Last address of program VDD = 6.5 V, VPP = 12.5 V X=0 X=X+1 No X = 10? 0.1-ms program pulse Address = Address + 1 Verify Yes Fail Pass No Address = N? Yes VDD = 4.5 to 5.
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CHAPTER 26 µPD78P054, 78P058 Figure 26-7. Byte Program Mode Timing Program Program Verify A0-A16 D0-D7 Data Input Hi-Z Data Output VPP VPP VDD VDD+1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL Cautions 1. Be sure to apply VDD before applying VPP, and remove it after removing VPP. 2. VPP must not exceed +13.5 V including overshoot voltage. 3. Disconnecting/inserting the device from/to the on-board socket while +12.
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CHAPTER 26 µPD78P054, 78P058 26.4.3 PROM reading procedure PROM contents can be read onto the external data bus (D0 to D7) using the following procedure. (1) Fix the RESET pin low, and supply +5 V to the VPP pin. Unused pins are handled as shown in paragraph, (2) “PROM programming mode” in section 1.5 or 2.5 Pin Configuration (Top View). (2) Supply +5 V to the VDD and VPP pins. (3) Input the address of data to be read to pins A0 through A16. (4) Read mode is entered.
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CHAPTER 26 µPD78P054, 78P058 26.5 Erasure Procedure (µPD78P054KK-T and 78P058KK-T Only) With the µPD78P054KK-T or 78P058KK-T, it is possible to erase ( or set all contents to FFH) the data contents written in the program memory, and rewrite the memory. The data can be erased by exposing the window to light with a wavelength of approximately 400 nm or shorter. Typically, data is erased by 254-nm ultraviolet light rays. The minimum lighting level to completely erase the written data is shown below.
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[MEMO] 560
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CHAPTER 27 INSTRUCTION SET This chapter describes each instruction set of the µPD78054 and 78054Y subseries as list table. For details of its operation and operation code, refer to the separate document “78K/0 Series User’s Manual, Instruction (U12326E).
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CHAPTER 27 INSTRUCTION SET 27.1 Legends Used in Operation List 27.1.1 Operand identifiers and description methods Operands are described in “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them. Alphabetic letters in capitals and symbols, #, !, $ and [ ] are key words and must be described as they are.
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CHAPTER 27 INSTRUCTION SET 27.1.
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CHAPTER 27 INSTRUCTION SET 27.
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CHAPTER 27 Clock Instruction Mnemonic Group 16-bit data transfer MOVW Operands Byte Flag Operation Z AC CY 6 – rp ← word saddrp, #word 4 8 10 (saddrp) ← word sfrp, #word 4 – 10 sfrp ← word AX, saddrp 2 6 8 AX ← (saddrp) saddrp, AX 2 6 8 (saddrp) ← AX AX, sfrp 2 – 8 AX ← sfrp 2 – 8 sfrp ← AX AX, rp Note 3 1 4 – AX ← rp rp, AX Note 3 1 4 – rp ← AX 3 10 12 + 2n AX ← (addr16) 12 + 2m (addr16) ← AX !addr16, AX AX, rp Note 3 A, #byte saddr, #byte 3 10 1
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CHAPTER 27 Clock Instruction Mnemonic Group Operands Byte A, #byte saddr, #byte 4 – A, CY ← A – byte × × × 3 6 8 (saddr), CY ← (saddr) – byte × × × 4 – A, CY ← A – r × × × 4 – r, CY ← r – A × × × A, saddr 2 4 5 A, CY ← A – (saddr) × × × A, !addr16 3 8 9+n A, CY ← A – (addr16) × × × A, [HL] 1 4 5+n A, CY ← A – (HL) × × × A, [HL + byte] 2 8 9+n A, CY ← A – (HL + byte) × × × A, [HL + B] 2 8 9+n A, CY ← A – (HL + B) × × × A, [HL + C] 2 8
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CHAPTER 27 Clock Instruction Mnemonic Group Operands Byte A, #byte saddr, #byte XOR 2 4 – A ← A ∨ byte × 3 6 8 (saddr) ← (saddr) ∨ byte × Z AC CY 4 – A←A∨r × 2 4 – r←r∨A × A, saddr 2 4 5 A ← A ∨ (saddr) × A, !addr16 3 8 9+n A ← A ∨ (addr16) × Note 3 A, [HL] 1 4 5+n A ← A ∨ (HL) × A, [HL + byte] 2 8 9+n A ← A ∨ (HL + byte) × A, [HL + B] 2 8 9+n A ← A ∨ (HL + B) × A, [HL + C] 2 8 9+n A ← A ∨ (HL + C) × A, #byte 2 4 – A ← A ∨ byte × saddr, #
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CHAPTER 27 Clock Instruction Mnemonic Group 16-bit operation Multiply/ divide Byte Note 1 Note 2 Flag Operation Z AC CY AX, #word 3 6 – AX, CY ← AX + word × × × SUBW AX, #word 3 6 – AX, CY ← AX – word × × × CMPW AX, #word 3 6 – AX – word × × × MULU X 2 16 – AX ← A × X DIVUW C 2 25 – AX (Quotient), C (Remainder) ← AX ÷ C r 1 2 – r←r+1 × × saddr 2 4 6 (saddr) ← (saddr) + 1 × × r 1 2 – r←r–1 × × saddr 2 4 6 (saddr) ← (saddr) – 1 × × INCW
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CHAPTER 27 Clock Instruction Mnemonic Group AND1 OR1 XOR1 Bit manipulate SET1 CLR1 SET1 INSTRUCTION SET Operands Byte Note 1 Note 2 Flag Operation Z AC CY CY, saddr.bit 3 6 7 CY ← CY ∧ (saddr.bit) × CY, sfr.bit 3 – 7 CY ← CY ∧ sfr.bit × CY, A.bit 2 4 – CY ← CY ∧ A.bit × CY, PSW.bit 3 – 7 CY ← CY ∧ PSW.bit × CY, [HL].bit 2 6 7+n CY ← CY ∧ (HL).bit × CY, saddr.bit 3 6 7 CY ← CY ∨ (saddr.bit) × CY, sfr.bit 3 – 7 CY ← CY ∨ sfr.bit × CY, A.
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CHAPTER 27 INSTRUCTION SET Clock Instruction Mnemonic Group Operands Byte Note 1 Note 2 Z AC CY CALL !addr16 3 7 – (SP – 1) ← (PC + 3)H, (SP – 2) ← (PC + 3)L, PC ← addr16, SP ← SP – 2 CALLF !addr11 2 5 – (SP – 1) ← (PC + 2)H, (SP – 2) ← (PC + 2)L, PC15 – 11 ← 00001, PC10 – 0 ← addr11, SP ← SP – 2 1 6 – (SP – 1) ← (PC + 1)H, (SP – 2) ← (PC + 1)L, PCH ← (00000000, addr5 + 1), PCL ← (00000000, addr5), SP ← SP – 2 BRK 1 6 – (SP – 1) ← PSW, (SP – 2) ← (PC + 1)H, (SP – 3) ← (PC + 1)L,
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CHAPTER 27 Clock Instruction Mnemonic Group Operands Byte Note 1 Note 2 Flag Operation Z AC CY saddr.bit, $addr16 3 8 9 PC ← PC + 3 + jdisp8 if(saddr.bit) = 1 sfr.bit, $addr16 4 – 11 PC ← PC + 4 + jdisp8 if sfr.bit = 1 A.bit, $addr16 3 8 – PC ← PC + 3 + jdisp8 if A.bit = 1 PSW.bit, $addr16 3 – 9 PC ← PC + 3 + jdisp8 if PSW.bit = 1 [HL].bit, $addr16 3 10 11 + n PC ← PC + 3 + jdisp8 if (HL).bit = 1 saddr.bit, $addr16 4 10 11 sfr.
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CHAPTER 27 INSTRUCTION SET 27.
PAGE 573
CHAPTER 27 INSTRUCTION SET Second Operand [HL + byte] rNote sfr ADD MOV MOV MOV MOV ADDC SUB XCH ADD XCH XCH ADD XCH ADD SUBC AND ADDC SUB ADDC ADDC SUB SUB ADDC ADDC SUB SUB OR XOR SUBC AND SUBC SUBC AND AND SUBC SUBC AND AND CMP OR XOR OR XOR OR XOR OR XOR OR XOR CMP CMP CMP CMP CMP #byte A saddr !addr16 PSW [DE] [HL] MOV MOV MOV ROR XCH XCH ADD XCH ADD ROL RORC First Operand A r MOV MOV [HL + B] $addr16 [HL + C] 1 None ROLC MOV ADD INC DEC ADDC SU
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CHAPTER 27 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand #word AX rpNote sfrp saddrp !addr16 SP None 1st Operand AX ADDW MOVW SUBW XCHW MOVW MOVW MOVW MOVW CMPW rp MOVW MOVWNote INCW DECW PUSH POP sfrp MOVW MOVW saddrp MOVW MOVW !addr16 MOVW SP MOVW Note MOVW Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second Operand A.bit sfr.bit saddr.
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CHAPTER 27 INSTRUCTION SET (4) Call/instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand AX !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound BT instruction BF BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP 575
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[MEMO] 576
PAGE 577
APPENDIX A DIFFERENCES BETWEEN µPD78054, 78054Y SUBSERIES AND µPD78058F, 78058FY SUBSERIES Table A-1 shows the major differences between the µPD78054, 78054Y Subseries and µPD78058F, 78058FY Subseries.
PAGE 578
APPENDIX A DIFFERENCES BETWEEN µPD78054, 78054Y SUBSERIES AND µPD78058F, 78058FY SUBSERIES Table A-1. Major differences between µPD78054, 78054Y Subseries and µPD78058F, 78058FY Subseries Part Number µPD78054, 78054Y Subseries µPD78058F, 78058FY Subseries Item EMI noise measure None Provided PROM version µPD78P054 µPD78P058F µPD78P058 µPD78P058Y µPD78P058Y Supply voltage VDD = 2.0 to 6.0 V VDD = 2.7 to 6.
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APPENDIX B DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the µPD78054 and 78054Y subseries. Figure B-1 shows the configuration of the development tools.
PAGE 580
APPENDIX B DEVELOPMENT TOOLS Figure B-1. Development Tool Configuration (1/2) (1) When using in-circuit emulator IE-78K0-NS Language processing software Debugging tool • System simulator • Integrated debugger • Device file • Assembler package • C compiler package • C library source file • Device file PROM programming tool • PG-1500 controller Embedded software • Real-time OS • OS Host machine (PC) Interface adapter, PC card interface, etc.
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APPENDIX B DEVELOPMENT TOOLS Figure B-1.
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APPENDIX B DEVELOPMENT TOOLS B.1 Language Processing Software RA78K/0 A program that converts a program written in mnemonic into object Assembler Package codes that microcomputers can process. Provided with functions to automatically perform generation of symbol table, optimizing processing of branch instructions, etc. Used in combination with separately available Device File (DF78054).
PAGE 583
APPENDIX B Remark DEVELOPMENT TOOLS xxxx in the part number differs depending on the host machine and OS used. µSxxxx µSxxxx µSxxxx µSxxxx RA78K0 CC78K0 DF78078 CC78K0-L xxxx Host Machine OS 3.5-inch 2HD FD 3.5-inch 2HC FD AA13 PC-9800 series Japanese AB13 IBM PC/AT™ and Japanese WindowsNotes 1, 2 WindowsNotes 1, 2 BB13 compatibles English 3P16 HP9000 series 700™ HP-UX™ (rel. 9.05) 3K13 SPARCstation™ SunOS™ (rel. 4.1.4) 3K15 3R13 Supply Media WindowsNotes 1, 2 DAT (DDS) 3.
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APPENDIX B DEVELOPMENT TOOLS B.2 PROM Writing Tools B.2.1 Hardware PG-1500 A PROM programmer that, by connecting the attached board and separately PROM Programmer available PROM programmer adapter, is capable of programming singlechip microcomputers incorporating a PROM on stand-alone basis or through operation from the host machine. Also capable of programming typical 256-Kbit to 4-Mbit PROM. PA-78P054GC A PROM programmer adapter for the µPD78P054, 78P058, and 78P058Y.
PAGE 585
APPENDIX B DEVELOPMENT TOOLS B.3 Debugging Tools B.3.1 Hardware (1/2) (1) When using in-circuit emulator IE-78K0-NS IE-78K0-NSNote An in-circuit emulator to debug hardware and software when developing In-circuit Emulator application systems that use the 78K/0 Series. Supports integrated debugger (ID78K0-NS). Used in combination with a power supply unit, emulation probe, and interface adapter to connect to the host machine. IE-70000-MC-PS-B An adapter to supply voltage from AC100 to 240-V outlet.
PAGE 586
APPENDIX B DEVELOPMENT TOOLS B.3.1 Hardware (2/2) (2) When using in-circuit emulator IE-78001-R-A IE-78001-R-ANote 1 An in-circuit emulator to debug hardware and software when developing In-circuit Emulator application systems that use the 78K/0 Series. Supports integrated debugger (ID78K0). Used in combination with an interface adapter to connect to an emulation probe and the host machine.
PAGE 587
APPENDIX B DEVELOPMENT TOOLS B.3.2 Software (1/2) SM78K0 Capable of debugging in C source level or assembler level while simulating System Simulator the operation of the target system on the host machine. The SM78K0 operates on Windows. The use of the SM78K0 enables the verification of logic and performance of applications independently from hardware development without using incircuit emulator and improves the development efficiency and the software quality.
PAGE 588
APPENDIX B DEVELOPMENT TOOLS B.3.2 Software (2/2) ID78K0-NSNote A control program to debug the 78K/0 Series. Integrated debugger Adopting Windows on personal computers and OSF/Motif™ on EWS as (supporting in-circuit emulator graphical user interface, presents the appearance and the operability conforming to them.
PAGE 589
APPENDIX B DEVELOPMENT TOOLS B.4 OS for IBM PC The following OSs are supported for IBM PC. Table B-1. OS for IBM PC OS Version PC DOS Ver. 5.02 to Ver. 6.3 J6.1/VNote to J6.3/VNote IBM DOS™ J5.02/VNote MS-DOS Ver. 5.0 to Ver. 6.22 5.0/VNote to 6.2/VNote Note Only English mode is supported. Caution MS-DOS ver. 5.0 or later has a task swap function, but it cannot be used with the above software. B.
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APPENDIX B DEVELOPMENT TOOLS Drawing and Footprint for Conversion Socket (EV-9200GC-80) Figure B-2. EV-9200GC-80 Drawing (For Reference Only) A E M B N O L K S J C D R F EV-9200GC-80 Q 1 No.1 pin index P G H I EV-9200GC-80-G0 ITEM 590 MILLIMETERS INCHES A 18.0 0.709 B 14.4 0.567 C 14.4 0.567 D 18.0 0.709 E 4-C 2.0 4-C 0.079 F 0.8 0.031 G 6.0 0.236 H 16.0 0.63 I 18.7 0.736 J 6.0 0.236 K 16.0 0.63 L 18.7 0.736 M 8.2 0.323 O 8.0 0.315 N 2.5 0.
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APPENDIX B DEVELOPMENT TOOLS Figure B-3. EV-9200GC-80 Footprint (For Reference Only) Based on EV-9200GC-80 (2) Pad drawing (in mm) G J H D E F K I L C B A EV-9200GC-80-P1E ITEM MILLIMETERS A 19.7 B 15.0 INCHES 0.776 0.591 C 0.65±0.02 × 19=12.35±0.05 D +0.003 0.65±0.02 × 19=12.35±0.05 0.026 +0.001 –0.002 × 0.748=0.486 –0.002 0.026+0.001 –0.002 × 0.748=0.486 +0.003 –0.002 E 15.0 0.591 F 19.7 0.776 G 6.0 ± 0.05 0.236 +0.003 –0.002 H 6.0 ± 0.05 0.236 +0.003 –0.002 I 0.
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APPENDIX B DEVELOPMENT TOOLS Drawing of Conversion Adapter (TGK-080SDW) Figure B-4. TGK-080SDW Drawing (For Reference) (unit: mm) TGK-080SDW (TQPACK080SD + TQSOCKET080SDW) Package dimension (unit: mm) A B C T U V D R Q Q Q M2 screw G F E c e b H P a S O O O N K I JJJ d Z W X Y L L LM g v f k u r t j s i q h p l Protrusion : 4 places n o m ITEM A B Note Product by TOKYO ELETECH CORPORATION. 592 MILLIMETERS 18.0 ITEM MILLIMETERS 0.709 0.463 INCHES a 0.5x19=9.5±0.10 0.
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APPENDIX C EMBEDDED SOFTWARE For efficient program development and maintenance of the µPD78054, 78054Y Subseries, the following embedded software is available. Real-time OS (1/2) A real-time OS conforming to µITRON specifications. RX78K/0 Real-time OS Added with the tool (configurator) to create the RX78K/0 nucleus and multiple information table. Used in combination with separately available Assembler Package (RA78K/0) and Device File (DF78054).
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APPENDIX C REGISTER INDEX Real-time OS (2/2) MX78K0 A µITRON specification subset OS. Added with MX78K0 nucleus. OS Performs task management, event management, and time management. In task management, controls the execution order of tasks and performs processing to change the task to the one executed next. The MX78K0 is a DOS-based application. Use it with DOS prompt on Windows.
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APPENDIX D REGISTER INDEX D.1 Register Index 8-bit timer mode control register (TMC1) .......................................................................................................... 225 8-bit timer output control register (TOC1) ......................................................................................................... 226 8-bit timer register 1 (TM1) ................................................................................................................................
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APPENDIX D REGISTER INDEX [I] IF0H: Interrupt request flag register 0H ................................................................................................... 489 IF0L: Interrupt request flag register 0L .................................................................................................... 489 IF1L: Interrupt request flag register 1L ........................................................................................... 489, 508 IMS: Memory size switching register ....
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APPENDIX D REGISTER INDEX PR0H: Priority specify flag register 0H ...................................................................................................... 491 PR0L: Priority specify flag register 0L ....................................................................................................... 491 PR1L: Priority specify flag register 1L ....................................................................................................... 491 PSW: Program status word .........
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[MEMO] 598
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APPENDIX E REVISION HISTORY Major revisions by edition and revised chapters are shown below. Edition 2nd Major revisions from previous version P40/AD0-P47/AD7 pin I/O circuit types were changed. Revised Chapters CHAPTER 2 Pin Functions Caution on OVF0 flag operations was added. CHAPTER 6 16-Bit Timer/Event Counter Interval time of interval timer was corrected. CHAPTER 8 Watch Timer Buzzer output frequency was corrected.
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APPENDIX E Edition 4th edition REVISION HISTORY Major revisions from previous version Revised Chapters Addition of following package to all devices: • 80-pin plastic QFP (14 × 14 mm, resin thickness: 1.4 mm) (under planning) Addition of following package to µPD78058 • 80-pin plastic TQFP (fine pitch) (12 × 12 mm) Throughout Addition of description to Caution in Figure 8-6. 16-Bit Timer Output Control Register Format CHAPTER 8 Change of Figure 11-3.
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APPENDIX E Edition REVISION HISTORY Major revisions from previous version 4th The µPD78052(A),78053(A), and 78054(A) were added to the edition applicable types. Revised Chapters Throughout The µPD78P054Y was deleted from the applicable types. The following package was deleted from the µPD78052, 78053, 78054, 78055, 78056, 78058, 78P058, 78054Y Subseries: • 80-pin plastic QFP (14 × 14 mm, resin thickness 2.7 mm) Figure 9-10. Square-Wave Output Operation Timing was added.
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[MEMO] 602
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