Electronics America Computer Hardware User Manual

154
µ PD78214 Sub-Series
Fig. 7-59 Timing of Interval Timer Operation (2) (When CR11 Is Used As a Compare Register)
Remark Interval = (n + 1) × x/f
CLK
, 0 ≤ n ≤ FFH
x = 16, 32, 64, 128, 256, 512
Fig. 7-60 Setting of Control Registers for Interval Timer Operation (2)
(a) Timer control register 1 (TMC1)
(b) Prescaler mode register 1 (PRM1)
(c) Capture/compare control register 1 (CRC1)
7654321
0
0
000
1
CRC1
Disables clearing TM1, when CR10
coincides with TM1
Specifies the CR11 register as a compare
register
Enables clearing TM1, when CR11
coincides with TM1
000
0H
TM1
count value
n
Compare register
(CR11)
INTC11
interrupt request
Interrupt accepted
Interval time Interval time
Interrupt accepted
Cleared
Cleared
n
n
Coincidence Coincidence
Count starts
76543210
0
000
1
TMC1
Overflow flag
Enables counting TM1
×
××
76543210
PRS10
0
PRM1
×××
PRS12 PRS11
×
Specifies count clock
(x/fCLK; where x = 16, 32, 64,
128, 256, or 512)