Electronics America Single-Chip Microcontrollers User's Manual

CHAPTER 21 INSTRUCTION SET
336 User’s Manual U15331EJ4V1UD
Mnemonic Operands Bytes Clocks Operation Flag
Z AC CY
SUBC A, #byte 2 4 A, CY ← A − byte − CY x x x
saddr, #byte 3 6 (saddr), CY ← (saddr) − byte − CY x x x
A, r 2 4 A, CY ← A − r − CY x x x
A, saddr 2 4 A, CY ← A − (saddr) − CY x x x
A, !addr16 3 8 A, CY ← A − (addr16) − CY x x x
A, [HL] 1 6 A, CY ← A − (HL) − CY x x x
A, [HL+byte] 2 6 A, CY ← A − (HL + byte) − CY x x x
AND A, #byte 2 4 A ← A ∧ byte x
saddr, #byte 3 6 (saddr) ← (saddr) ∧ byte x
A, r 2 4 A ← A ∧ r x
A, saddr 2 4 A ← A ∧ (saddr) x
A, !addr16 3 8 A ← A ∧ (addr16) x
A, [HL] 1 6 A ← A ∧ (HL) x
A, [HL+byte] 2 6 A ← A ∧ (HL + byte) x
OR A, #byte 2 4 A ← A ∨ byte x
saddr, #byte 3 6 (saddr) ← (saddr) ∨ byte x
A, r 2 4 A ← A ∨ r x
A, saddr 2 4 A ← A ∨ (saddr) x
A, !addr16 3 8 A ← A ∨ (addr16) x
A, [HL] 1 6 A ← A ∨ (HL) x
A, [HL+byte] 2 6 A ← A ∨ (HL + byte) x
XOR A, #byte 2 4 A ← A V byte x
saddr, #byte 3 6 (saddr) ← (saddr) V byte x
A, r 2 4 A ← A V r x
A, saddr 2 4 A ← A V (saddr) x
A, !addr16 3 8 A ← A V (addr16) x
A, [HL] 1 6 A ← A V (HL) x
A, [HL+byte] 2 6 A ← A V (HL + byte) x
Remark One instruction clock cycle is one CPU clock cycle (f
CPU) selected by the processor clock control
register (PCC).