Electronics America Computer Hardware User Manual

410
µ PD78214 Sub-Series
ROR
ROL
RORC
ROLC
SHR
SHL
SHRW
SHLW
ROR4
ROL4
Operation
Mnemonic Operand
No. of
bytes
Flags
r, n 2 (CY, r
7
← r
0
, r
m-1
← r
m
) × n times n=0 to 7 ×
r, n 2 (CY, r
0
← r
7
, r
m+1
← r
m
) × n times n=0 to 7 ×
r, n 2 (CY ← r
0
, r
7
← CY, r
m-1
← r
m
) × n times n=0 to 7 ×
r, n 2 (CY ← r
7
, r
0
← CY, r
m+1
← r
m
) × n times n=0 to 7 ×
r, n 2 (CY ← r
0
, r
7
← 0, r
m-1
← r
m
) × n times n=0 to 7 × 0 ×
r, n 2 (CY ← r
7
, r
0
← 0, r
m+1
← r
m
) × n times n=0 to 7 × 0 ×
rp, n 2 (CY ← rp
0
, rp
15
← 0, rp
m-1
← rp
m
) × n times n=0 to 7 × 0 ×
rp, n 2 (CY ← rp
15
, rp
0
← 0, rp
m+1
← rp
m
) × n times n=0 to 7 × 0 ×
mem1 2 A
3-0
← (mem1)
3-0
, (mem1)
7-4
← A
3-0
,
(mem1)
3-0
← (mem1)
7-4
& mem1 3 A
3-0
← (& mem1)
3-0
, (& mem1)
7-4
← A
3-0
,
(& mem1)
3-0
← (& mem1)
7-4
mem1 2 A
3-0
← (mem1)
7-4
, (mem1)
3-0
← A
3-0
,
(mem1)
7-4
← (mem1)
3-0
& mem1 3 A
3-0
← (& mem1)
7-4
, (& mem1)
3-0
← A
3-0
,
(& mem1)
7-4
← (& mem1)
3-0
ZACCY
INC
DEC
INCW
DECW
Operation
Mnemonic Operand
No. of
bytes
Flags
r1r ← r + 1 ××
saddr 2 (saddr) ← (saddr) + 1 ××
r1r ← r – 1 ××
saddr 2 (saddr) ← (saddr) – 1 ××
rp 1 rp ← rp + 1
rp 1 rp ← rp – 1
ZACCY
(5) Multiply/divide instructions: MULU, DIVUW
MULU
DIVUW
Operation
Mnemonic Operand
No. of
bytes
Flags
ZACCY
r 2 AX ← A × r1
r 2 AX (quotient), r (remainder) ← AX ÷ r
When r = 0, r ← X, AX ← 0FFFFH
(6) Increment/decrement instructions: INC, DEC, INCW, DECW
(7) Shift/rotate instructions: ROR, ROL, RORC, ROLC, SHR, SHL, SHRW, SHLW, ROR4, ROL4