Data Sheet

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74HC08; 74HCT08

Quad 2-input AND gate

Rev. 6 — 13 June 2017 Product data sheet

1 General description

The 74HC08; 74HCT08 is a quad 2-input AND gate. Inputs include clamp diodes. This

enables the use of current limiting resistors to interface inputs to voltages in excess of

2 Features and benefits

• Complies with JEDEC standard JESD7A

• Input levels:

– For 74HC08: CMOS level

– For 74HCT08: TTL level

• ESD protection:

– HBM JESD22-A114F exceeds 2 000 V

– MM JESD22-A115-A exceeds 200 V

• Multiple package options

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

3 Ordering information

Table 1. Ordering information

PackageType

number

Temperature range Name Description Version

74HC08D

74HCT08D

-40 °C to +125 °C SO14 plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74HC08DB

74HCT08DB

-40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads;

body width 5.3 mm

SOT337-1

74HC08PW

74HCT08PW

-40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

74HC08BQ

74HCT08BQ

-40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced

very thin quad flat package; no leads; 14 terminals;

body 2.5 × 3 × 0.85 mm

SOT762-1

Summary of content (16 pages)

PAGE 1
74HC08; 74HCT08 Quad 2-input AND gate Rev. 6 — 13 June 2017 1 Product data sheet General description The 74HC08; 74HCT08 is a quad 2-input AND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
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74HC08; 74HCT08 Nexperia Quad 2-input AND gate 4 Functional diagram 1 & 3 & 6 & 8 2 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B 4 1Y 3 5 2Y 6 9 3Y 10 8 12 11 4Y 11 13 Y B mna223 mna222 Figure 1. Logic symbol 5 A & Figure 2. IEC logic symbol mna221 Figure 3. IEC logic symbol Pinning information 5.
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74HC08; 74HCT08 Nexperia Quad 2-input AND gate 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 4, 9, 12 data input 1B to 4B 2, 5, 10,13 data input 1Y to 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) VCC 14 supply voltage 6 Functional description Table 3. Function table [1] Output Input nA nB nY L L L L H L H L L H H H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 7 Limiting values Table 4.
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74HC08; 74HCT08 Nexperia Quad 2-input AND gate 8 Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC08 74HCT08 Unit Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.
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74HC08; 74HCT08 Nexperia Quad 2-input AND gate Symbol Parameter Conditions 25 °C IO = 5.2 mA; VCC = 6.0 V -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max - 0.16 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1 - ±1 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 2.0 - 20 - 40 μA CI input capacitance - 3.5 - - - - - pF 74HCT08 VIH HIGH-level input voltage VCC = 4.5 V to 5.
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74HC08; 74HCT08 Nexperia Quad 2-input AND gate 10 Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; CL = 50 pF; for test circuit see Figure 7. Symbol Parameter Conditions 25 °C -40 °C to +125 °C Unit Min Typ Max Max (85 °C) Max (125 °C) VCC = 2.0 V - 25 90 115 135 ns VCC = 4.5 V - 9 18 23 27 ns VCC = 5.0 V; CL = 15 pF - 7 - - - ns - 7 15 20 23 ns VCC = 2.0 V - 19 75 95 110 ns VCC = 4.5 V - 7 15 19 22 ns VCC = 6.
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4HC08; 74HCT08 Nexperia Quad 2-input AND gate 10.1 Waveforms and test circuit VI nA, nB input VM GND tPHL VOH VY nY output VOL tTHL tPLH VM VX tTLH aaa-004037 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Figure 6. Input to output propagation delays Table 8. Measurement points Input Output VM VM VX VY 74HC08 0.5VCC 0.5VCC 0.1VCC 0.9VCC 74HCT08 1.3 V 1.3 V 0.1VCC 0.
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74HC08; 74HCT08 Nexperia Quad 2-input AND gate VI negative pulse VM VI GND VM 10 % GND positive pulse tW 90 % tf tr tr tf 90 % VM VM 10 % tW VCC G VI DUT VO RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Figure 7. Test circuit for measuring switching times Table 9.
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74HC08; 74HCT08 Nexperia Quad 2-input AND gate 11 Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 A2 Q A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.
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74HC08; 74HCT08 Nexperia Quad 2-input AND gate SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.
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74HC08; 74HCT08 Nexperia Quad 2-input AND gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm D SOT402-1 E A X c y HE v M A Z 8 14 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 7 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.
PAGE 12
74HC08; 74HCT08 Nexperia Quad 2-input AND gate DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm B D SOT762-1 A A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e v w b 2 6 C A B C y y1 C L 1 7 Eh e 14 8 k 13 9 Dh X k 0 2 Dimensions (mm are the original dimensions) Unit max nom min mm A(1) 1 A1 b 0.05 0.30 0.02 0.25 0.00 0.
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74HC08; 74HCT08 Nexperia Quad 2-input AND gate 12 Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13 Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT08 v.
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74HC08; 74HCT08 Nexperia Quad 2-input AND gate 14 Legal information 14.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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74HC08; 74HCT08 Nexperia Quad 2-input AND gate Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.
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Nexperia 74HC08; 74HCT08 Quad 2-input AND gate Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 10.1 11 12 13 14 General description ............................................ 1 Features and benefits .........................................1 Ordering information .......................................... 1 Functional diagram ............................................. 2 Pinning information ............................................ 2 Pinning ...............................................................