Data Sheet

ManualsBrandsNEXPERIA ManualsLogic ICsLogic IC - Latch D type, Addressable Standard SO 16

1. General description

The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes

of operation. In the addressable latch mode, data on the D input is written into the latch

addressed by the inputs AO to A3. The addressed latch will follow the data input,

non-addressed latches will retain their previous states. In memory mode, all latches retain

their previous states and are unaffected by the data or address inputs. In the 3-to-8

decoding or demultiplexing mode, the addressed output follows the D input and all other

outputs are LOW. In the reset mode, all outputs are forced LOW and unaffected by the

data or address inputs. Inputs include clamp diodes. This enables the use of current

limiting resistors to interface inputs to voltages in excess of V

2. Features and benefits

 Combined demultiplexer and 8-bit latch

 Serial-to-parallel capability

 Output from each storage bit available

 Random (addressable) data entry

 Easily expandable

 Common reset input

 Useful as a 3-to-8 active HIGH decoder

 Complies with JEDEC standard no. 7A

 Input levels:

 For 74HC259: CMOS level

 For 74HCT259: TTL level

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 CDM JESD22E exceeds 1000 V

 Multiple package options

 Specified from 40 C to +85 C and from 40 C to +125 C

74HC259; 74HCT259

8-bit addressable latch

Rev. 6 — 2 February 2016 Product data sheet

Summary of content (21 pages)

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74HC259; 74HCT259 8-bit addressable latch Rev. 6 — 2 February 2016 Product data sheet 1. General description The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs AO to A3. The addressed latch will follow the data input, non-addressed latches will retain their previous states.
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74HC259; 74HCT259 Nexperia 8-bit addressable latch 3. Ordering information Table 1. Ordering information Type number 74HC259D Package Temperature range Name Description Version 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.
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74HC259; 74HCT259 Nexperia 8-bit addressable latch 4 $ 4 $ 4 $ 4 4 RI '(&2'(5 /$7&+(6 /( 4 05 4 ' 4 PQD Fig 3. Functional diagram 5. Pinning information 5.
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74HC259; 74HCT259 Nexperia 8-bit addressable latch 5.2 Pin description Table 2. Pin description Symbol Pin Description A0, A1, A2 1, 2, 3 address input Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 4, 5, 6, 7, 9, 10, 11, 12 latch output GND 8 ground (0 V) D 13 data input LE 14 latch enable input (active LOW) MR 15 conditional reset input (active LOW) VCC 16 supply voltage 6. Functional description Table 3.
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74HC259; 74HCT259 Nexperia 8-bit addressable latch Table 4. Operating mode select table[1] LE MR Mode L H Addressable latch mode H H Memory mode L L Demultiplexer mode H L Reset mode [1] H = HIGH voltage level; L = LOW voltage level. 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +7.
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74HC259; 74HCT259 Nexperia 8-bit addressable latch 8. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC259 74HCT259 Unit Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0 - VCC V output voltage 0 - VCC 0 - VCC V VCC supply voltage VI VO Tamb ambient temperature t/V input transition rise and fall rate 40 - +125 40 - +125 VCC = 2.
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4HC259; 74HCT259 Nexperia 8-bit addressable latch Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter CI 25 C Conditions input capacitance 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max - 3.5 - - - - - pF 74HCT259 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.
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74HC259; 74HCT259 Nexperia 8-bit addressable latch 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12. Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max Min Max - 58 185 - 230 - 280 74HC259 tpd propagation delay [2] D to Qn; see Figure 6 VCC = 2.0 V VCC = 4.5 V - 21 37 - 46 - 56 ns VCC = 5.
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74HC259; 74HCT259 Nexperia 8-bit addressable latch Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12. Symbol Parameter tsu th set-up time hold time 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max Min Max VCC = 2.0 V 80 19 - 100 - 120 - ns VCC = 4.5 V 16 7 - 20 - 24 - ns VCC = 6.
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74HC259; 74HCT259 Nexperia 8-bit addressable latch Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12. Symbol Parameter tsu set-up time 25 C Conditions Min Max Min Max Min Max 17 10 - 21 - 26 - ns 0 8 - 0 - 0 - ns 0 4 - 0 - 0 - ns - 19 - - - - - pF D, An to LE; see Figure 10 and Figure 11 VCC = 4.
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74HC259; 74HCT259 Nexperia 8-bit addressable latch 9&& 90 $Q LQSXW *1' W3/+ W3+/ 92+ 90 4Q RXWSXW 92/ DDK Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Address input to output propagation delays 9&& ' LQSXW *1' 9&& 90 /( LQSXW *1' W: W3+/ 92+ W3/+ 9< 90 4Q RXWSXW 9; 92/ W7+/ W7/+ DDM Measurement points are given in Table 9.
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74HC259; 74HCT259 Nexperia 8-bit addressable latch 9&& /( LQSXW 90 *1' WVX WVX WK 9&& WK 90 ' LQSXW *1' 92+ 4Q RXWSXW 90 4 ' 4 ' 92/ DDK Measurement points are given in Table 9. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical voltage output levels that occur with the output load. Fig 10.
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74HC259; 74HCT259 Nexperia 8-bit addressable latch 9, W: QHJDWLYH SXOVH 90 9 WI WU WU WI 9, SRVLWLYH SXOVH 9 90 90 90 W: 9&& 9&& * 9, 92 5/ 6 RSHQ '87 &/ 57 DDG Test data is given in Table 10. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch Fig 12.
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74HC259; 74HCT259 Nexperia 8-bit addressable latch 12.
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74HC259; 74HCT259 Nexperia 8-bit addressable latch 13. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT259 v.6 20160202 Product data sheet - 74HC_HCT259 v.
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74HC259; 74HCT259 Nexperia 8-bit addressable latch 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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74HC259; 74HCT259 Nexperia 8-bit addressable latch Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use.
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Nexperia 74HC259; 74HCT259 8-bit addressable latch 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 © General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . .