Data Sheet

1. General description
The 74HC75 is a quad bistable transparent latch with complementary outputs. Two
latches are simultaneously controlled by one of two active HIGH enable inputs (LE12 and
LE34). When LEnn is HIGH, the data enters the latches and appears at the nQ outputs.
The nQ outputs follow the data inputs (nD) as long as LEnn is HIGH (transparent). The
data on the nD inputs one set-up time prior to the HIGH-to-LOW transition of the LEnn will
be stored in the latches. The latched outputs remain stable as long as the LEnn is LOW.
Inputs include clamp diodes. This enables the use of current limiting resistors to interface
inputs to voltages in excess of V
CC
.
2. Features and benefits
 Complementary Q and Q outputs
 V
CC
and GND on the center pins
 Low-power dissipation
 Complies with JEDEC standard no. 7A
 Input levels:
 For 74HC75: CMOS level
 ESD protection:
 HBM EIA/JESD22-A114F exceeds 2000 V
 MM EIA/JESD22-A115-A exceeds 200 V
 Multiple package options
 Specified from 40 Cto+80C and from 40 Cto+125C.
3. Ordering information
74HC75
Quad bistable transparant latch
Rev. 4 — 24 February 2016 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC75D 40 C to +125 C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HC75DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74HC75PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package;
16 leads; body width 4.4 mm
SOT403-1