Data Sheet

ManualsBrandsNEXPERIA ManualsLogic ICsLogic IC - Gate and inverter NAND gate 74HCT SO 14

1. General description

The 74HC10; 74HCT10 is a triple 3-input NAND gate. Inputs include clamp diodes that

enable the use of current limiting resistors to interface inputs to voltages in excess of V

2. Features and benefits

 Complies with JEDEC standard JESD7A

 Input levels:

 For74HC10: CMOS level

 For 74HCT10: TTL level

 Complies with JEDEC standard no. 7A

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 Multiple package options

 Specified from 40 C to +85 C and from 40 C to +125 C

3. Ordering information

74HC10; 74HCT10

Triple 3-input NAND gate

Rev. 3 — 5 August 2016 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74HC10D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

74HCT10D

74HC10DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads;

body width 5.3 mm

SOT337-1

74HCT10DB

74HC10PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

74HCT10PW

Summary of content (14 pages)

PAGE 1
74HC10; 74HCT10 Triple 3-input NAND gate Rev. 3 — 5 August 2016 Product data sheet 1. General description The 74HC10; 74HCT10 is a triple 3-input NAND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits  Complies with JEDEC standard JESD7A  Input levels:  For74HC10: CMOS level  For 74HCT10: TTL level  Complies with JEDEC standard no.
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74HC10; 74HCT10 Nexperia Triple 3-input NAND gate 4. Functional diagram % & $ $ < & $ % & $ < < % PQD Fig 1. < % & PQD Logic symbol Fig 2. IEC logic symbol Fig 3. PQD Logic diagram (one gate) 5. Pinning information 5.
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74HC10; 74HCT10 Nexperia Triple 3-input NAND gate 6. Functional description Table 3. Function selection[1] Input Output nA nB nC nY L X X H X L X H X X L H H H H L [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage 0.
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74HC10; 74HCT10 Nexperia Triple 3-input NAND gate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.
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74HC10; 74HCT10 Nexperia Triple 3-input NAND gate Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HCT10 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.
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74HC10; 74HCT10 Nexperia Triple 3-input NAND gate Table 7. Dynamic characteristics …continued GND = 0 V; CL = 50 pF; for test circuit, see Figure 7. Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) - 14 24 30 36 ns - 11 - - - ns 74HCT10 [1] propagation delay nA, nB to nY; see Figure 6 tpd VCC = 4.5 V VCC = 5.0 V; CL = 15 pF tt transition time VCC = 4.
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4HC10; 74HCT10 Nexperia Triple 3-input NAND gate 9, QHJDWLYH SXOVH W: 90 90 *1' WI 9, WI SRVLWLYH SXOVH *1' WU WU 90 90 W: 9&& * 9, 92 '87 57 &/ DDK Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig 7. Table 9.
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74HC10; 74HCT10 Nexperia Triple 3-input NAND gate 12.
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74HC10; 74HCT10 Nexperia Triple 3-input NAND gate 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT10 v.3 20160805 Product data sheet - 74HC_HCT10_CNV v.
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74HC10; 74HCT10 Nexperia Triple 3-input NAND gate 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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74HC10; 74HCT10 Nexperia Triple 3-input NAND gate Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use.
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Nexperia 74HC10; 74HCT10 Triple 3-input NAND gate 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 © General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . .