Data Sheet

1. General description
The 74HC280; 74HCT280 is a 9-bit parity generator or checker. Both even and odd parity
outputs are available. The even parity output (PE) is HIGH when an even number of data
inputs (I0 to I8) is HIGH. The odd parity output (PO) is HIGH when an odd number of data
inputs are HIGH. Expansion to larger word sizes is accomplished by tying the even
outputs (PE) of up to nine parallel devices to the final stage data inputs. Inputs include
clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages
in excess of V
CC
.
2. Features and benefits
 Complies with JEDEC standard no. 7A
 Input levels:
 For 74HC280: CMOS level
 For 74HCT280: TTL level
 Word-length easily expanded by cascading
 Generates either odd or even parity for nine data bits
 ESD protection:
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V
 Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
74HC280; 74HCT280
9-bit odd/even parity generator/checker
Rev. 3 — 15 September 2016 Product data sheet
Table 1. Ordering information
Type number Temperature
range
Name Description Version
74HC280D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
74HCT280D
74HCT280DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body
width 5.3 mm
SOT337-1